sunxi_gpio.c revision 1.19.2.3
1 /* $NetBSD: sunxi_gpio.c,v 1.19.2.3 2019/01/26 22:00:01 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.19.2.3 2019/01/26 22:00:01 pgoyette Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 #include <sys/kmem.h> 41 #include <sys/gpio.h> 42 #include <sys/bitops.h> 43 #include <sys/lwp.h> 44 45 #include <dev/fdt/fdtvar.h> 46 #include <dev/gpio/gpiovar.h> 47 48 #include <arm/sunxi/sunxi_gpio.h> 49 50 #define SUNXI_GPIO_MAX_EINT_BANK 5 51 #define SUNXI_GPIO_MAX_EINT 32 52 53 #define SUNXI_GPIO_PORT(port) (0x24 * (port)) 54 #define SUNXI_GPIO_CFG(port, pin) (SUNXI_GPIO_PORT(port) + 0x00 + (0x4 * ((pin) / 8))) 55 #define SUNXI_GPIO_CFG_PINMASK(pin) (0x7 << (((pin) % 8) * 4)) 56 #define SUNXI_GPIO_DATA(port) (SUNXI_GPIO_PORT(port) + 0x10) 57 #define SUNXI_GPIO_DRV(port, pin) (SUNXI_GPIO_PORT(port) + 0x14 + (0x4 * ((pin) / 16))) 58 #define SUNXI_GPIO_DRV_PINMASK(pin) (0x3 << (((pin) % 16) * 2)) 59 #define SUNXI_GPIO_PULL(port, pin) (SUNXI_GPIO_PORT(port) + 0x1c + (0x4 * ((pin) / 16))) 60 #define SUNXI_GPIO_PULL_DISABLE 0 61 #define SUNXI_GPIO_PULL_UP 1 62 #define SUNXI_GPIO_PULL_DOWN 2 63 #define SUNXI_GPIO_PULL_PINMASK(pin) (0x3 << (((pin) % 16) * 2)) 64 #define SUNXI_GPIO_INT_CFG(bank, eint) (0x200 + (0x20 * (bank)) + (0x4 * ((eint) / 8))) 65 #define SUNXI_GPIO_INT_MODEMASK(eint) (0xf << (((eint) % 8) * 4)) 66 #define SUNXI_GPIO_INT_MODE_POS_EDGE 0x0 67 #define SUNXI_GPIO_INT_MODE_NEG_EDGE 0x1 68 #define SUNXI_GPIO_INT_MODE_HIGH_LEVEL 0x2 69 #define SUNXI_GPIO_INT_MODE_LOW_LEVEL 0x3 70 #define SUNXI_GPIO_INT_MODE_DOUBLE_EDGE 0x4 71 #define SUNXI_GPIO_INT_CTL(bank) (0x210 + 0x20 * (bank)) 72 #define SUNXI_GPIO_INT_STATUS(bank) (0x214 + 0x20 * (bank)) 73 74 static const struct of_compat_data compat_data[] = { 75 #ifdef SOC_SUN4I_A10 76 { "allwinner,sun4i-a10-pinctrl", (uintptr_t)&sun4i_a10_padconf }, 77 #endif 78 #ifdef SOC_SUN5I_A13 79 { "allwinner,sun5i-a13-pinctrl", (uintptr_t)&sun5i_a13_padconf }, 80 { "nextthing,gr8-pinctrl", (uintptr_t)&sun5i_a13_padconf }, 81 #endif 82 #ifdef SOC_SUN6I_A31 83 { "allwinner,sun6i-a31-pinctrl", (uintptr_t)&sun6i_a31_padconf }, 84 { "allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&sun6i_a31_r_padconf }, 85 #endif 86 #ifdef SOC_SUN7I_A20 87 { "allwinner,sun7i-a20-pinctrl", (uintptr_t)&sun7i_a20_padconf }, 88 #endif 89 #ifdef SOC_SUN8I_A83T 90 { "allwinner,sun8i-a83t-pinctrl", (uintptr_t)&sun8i_a83t_padconf }, 91 { "allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&sun8i_a83t_r_padconf }, 92 #endif 93 #ifdef SOC_SUN8I_H3 94 { "allwinner,sun8i-h3-pinctrl", (uintptr_t)&sun8i_h3_padconf }, 95 { "allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&sun8i_h3_r_padconf }, 96 #endif 97 #ifdef SOC_SUN9I_A80 98 { "allwinner,sun9i-a80-pinctrl", (uintptr_t)&sun9i_a80_padconf }, 99 { "allwinner,sun9i-a80-r-pinctrl", (uintptr_t)&sun9i_a80_r_padconf }, 100 #endif 101 #ifdef SOC_SUN50I_A64 102 { "allwinner,sun50i-a64-pinctrl", (uintptr_t)&sun50i_a64_padconf }, 103 { "allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&sun50i_a64_r_padconf }, 104 #endif 105 #ifdef SOC_SUN50I_H5 106 { "allwinner,sun50i-h5-pinctrl", (uintptr_t)&sun8i_h3_padconf }, 107 { "allwinner,sun50i-h5-r-pinctrl", (uintptr_t)&sun8i_h3_r_padconf }, 108 #endif 109 #ifdef SOC_SUN50I_H6 110 { "allwinner,sun50i-h6-pinctrl", (uintptr_t)&sun50i_h6_padconf }, 111 { "allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&sun50i_h6_r_padconf }, 112 #endif 113 { NULL } 114 }; 115 116 struct sunxi_gpio_eint { 117 int (*eint_func)(void *); 118 void *eint_arg; 119 int eint_flags; 120 int eint_bank; 121 int eint_num; 122 }; 123 124 struct sunxi_gpio_softc { 125 device_t sc_dev; 126 bus_space_tag_t sc_bst; 127 bus_space_handle_t sc_bsh; 128 const struct sunxi_gpio_padconf *sc_padconf; 129 kmutex_t sc_lock; 130 131 struct gpio_chipset_tag sc_gp; 132 gpio_pin_t *sc_pins; 133 device_t sc_gpiodev; 134 135 u_int sc_eint_bank_max; 136 137 void *sc_ih; 138 struct sunxi_gpio_eint sc_eint[SUNXI_GPIO_MAX_EINT_BANK][SUNXI_GPIO_MAX_EINT]; 139 }; 140 141 struct sunxi_gpio_pin { 142 struct sunxi_gpio_softc *pin_sc; 143 const struct sunxi_gpio_pins *pin_def; 144 int pin_flags; 145 bool pin_actlo; 146 }; 147 148 #define GPIO_READ(sc, reg) \ 149 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 150 #define GPIO_WRITE(sc, reg, val) \ 151 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 152 153 static int sunxi_gpio_match(device_t, cfdata_t, void *); 154 static void sunxi_gpio_attach(device_t, device_t, void *); 155 156 CFATTACH_DECL_NEW(sunxi_gpio, sizeof(struct sunxi_gpio_softc), 157 sunxi_gpio_match, sunxi_gpio_attach, NULL, NULL); 158 159 static const struct sunxi_gpio_pins * 160 sunxi_gpio_lookup(struct sunxi_gpio_softc *sc, uint8_t port, uint8_t pin) 161 { 162 const struct sunxi_gpio_pins *pin_def; 163 u_int n; 164 165 for (n = 0; n < sc->sc_padconf->npins; n++) { 166 pin_def = &sc->sc_padconf->pins[n]; 167 if (pin_def->port == port && pin_def->pin == pin) 168 return pin_def; 169 } 170 171 return NULL; 172 } 173 174 static const struct sunxi_gpio_pins * 175 sunxi_gpio_lookup_byname(struct sunxi_gpio_softc *sc, const char *name) 176 { 177 const struct sunxi_gpio_pins *pin_def; 178 u_int n; 179 180 for (n = 0; n < sc->sc_padconf->npins; n++) { 181 pin_def = &sc->sc_padconf->pins[n]; 182 if (strcmp(pin_def->name, name) == 0) 183 return pin_def; 184 } 185 186 return NULL; 187 } 188 189 static int 190 sunxi_gpio_setfunc(struct sunxi_gpio_softc *sc, 191 const struct sunxi_gpio_pins *pin_def, const char *func) 192 { 193 uint32_t cfg; 194 u_int n; 195 196 KASSERT(mutex_owned(&sc->sc_lock)); 197 198 const bus_size_t cfg_reg = SUNXI_GPIO_CFG(pin_def->port, pin_def->pin); 199 const uint32_t cfg_mask = SUNXI_GPIO_CFG_PINMASK(pin_def->pin); 200 201 for (n = 0; n < SUNXI_GPIO_MAXFUNC; n++) { 202 if (pin_def->functions[n] == NULL) 203 continue; 204 if (strcmp(pin_def->functions[n], func) == 0) { 205 cfg = GPIO_READ(sc, cfg_reg); 206 cfg &= ~cfg_mask; 207 cfg |= __SHIFTIN(n, cfg_mask); 208 #ifdef SUNXI_GPIO_DEBUG 209 device_printf(sc->sc_dev, "P%c%02d cfg %08x -> %08x\n", 210 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, cfg_reg), cfg); 211 #endif 212 GPIO_WRITE(sc, cfg_reg, cfg); 213 return 0; 214 } 215 } 216 217 /* Function not found */ 218 device_printf(sc->sc_dev, "function '%s' not supported on P%c%02d\n", 219 func, pin_def->port + 'A', pin_def->pin); 220 221 return ENXIO; 222 } 223 224 static int 225 sunxi_gpio_setpull(struct sunxi_gpio_softc *sc, 226 const struct sunxi_gpio_pins *pin_def, int flags) 227 { 228 uint32_t pull; 229 230 KASSERT(mutex_owned(&sc->sc_lock)); 231 232 const bus_size_t pull_reg = SUNXI_GPIO_PULL(pin_def->port, pin_def->pin); 233 const uint32_t pull_mask = SUNXI_GPIO_PULL_PINMASK(pin_def->pin); 234 235 pull = GPIO_READ(sc, pull_reg); 236 pull &= ~pull_mask; 237 if (flags & GPIO_PIN_PULLUP) 238 pull |= __SHIFTIN(SUNXI_GPIO_PULL_UP, pull_mask); 239 else if (flags & GPIO_PIN_PULLDOWN) 240 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DOWN, pull_mask); 241 else 242 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DISABLE, pull_mask); 243 #ifdef SUNXI_GPIO_DEBUG 244 device_printf(sc->sc_dev, "P%c%02d pull %08x -> %08x\n", 245 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, pull_reg), pull); 246 #endif 247 GPIO_WRITE(sc, pull_reg, pull); 248 249 return 0; 250 } 251 252 static int 253 sunxi_gpio_setdrv(struct sunxi_gpio_softc *sc, 254 const struct sunxi_gpio_pins *pin_def, int drive_strength) 255 { 256 uint32_t drv; 257 258 KASSERT(mutex_owned(&sc->sc_lock)); 259 260 if (drive_strength < 10 || drive_strength > 40) 261 return EINVAL; 262 263 const bus_size_t drv_reg = SUNXI_GPIO_DRV(pin_def->port, pin_def->pin); 264 const uint32_t drv_mask = SUNXI_GPIO_DRV_PINMASK(pin_def->pin); 265 266 drv = GPIO_READ(sc, drv_reg); 267 drv &= ~drv_mask; 268 drv |= __SHIFTIN((drive_strength / 10) - 1, drv_mask); 269 #ifdef SUNXI_GPIO_DEBUG 270 device_printf(sc->sc_dev, "P%c%02d drv %08x -> %08x\n", 271 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, drv_reg), drv); 272 #endif 273 GPIO_WRITE(sc, drv_reg, drv); 274 275 return 0; 276 } 277 278 static int 279 sunxi_gpio_ctl(struct sunxi_gpio_softc *sc, const struct sunxi_gpio_pins *pin_def, 280 int flags) 281 { 282 KASSERT(mutex_owned(&sc->sc_lock)); 283 284 if (flags & GPIO_PIN_INPUT) 285 return sunxi_gpio_setfunc(sc, pin_def, "gpio_in"); 286 if (flags & GPIO_PIN_OUTPUT) 287 return sunxi_gpio_setfunc(sc, pin_def, "gpio_out"); 288 289 return EINVAL; 290 } 291 292 static void * 293 sunxi_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 294 { 295 struct sunxi_gpio_softc * const sc = device_private(dev); 296 const struct sunxi_gpio_pins *pin_def; 297 struct sunxi_gpio_pin *gpin; 298 const u_int *gpio = data; 299 int error; 300 301 if (len != 16) 302 return NULL; 303 304 const uint8_t port = be32toh(gpio[1]) & 0xff; 305 const uint8_t pin = be32toh(gpio[2]) & 0xff; 306 const bool actlo = be32toh(gpio[3]) & 1; 307 308 pin_def = sunxi_gpio_lookup(sc, port, pin); 309 if (pin_def == NULL) 310 return NULL; 311 312 mutex_enter(&sc->sc_lock); 313 error = sunxi_gpio_ctl(sc, pin_def, flags); 314 mutex_exit(&sc->sc_lock); 315 316 if (error != 0) 317 return NULL; 318 319 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 320 gpin->pin_sc = sc; 321 gpin->pin_def = pin_def; 322 gpin->pin_flags = flags; 323 gpin->pin_actlo = actlo; 324 325 return gpin; 326 } 327 328 static void 329 sunxi_gpio_release(device_t dev, void *priv) 330 { 331 struct sunxi_gpio_softc * const sc = device_private(dev); 332 struct sunxi_gpio_pin *pin = priv; 333 334 mutex_enter(&sc->sc_lock); 335 sunxi_gpio_ctl(pin->pin_sc, pin->pin_def, GPIO_PIN_INPUT); 336 mutex_exit(&sc->sc_lock); 337 338 kmem_free(pin, sizeof(*pin)); 339 } 340 341 static int 342 sunxi_gpio_read(device_t dev, void *priv, bool raw) 343 { 344 struct sunxi_gpio_softc * const sc = device_private(dev); 345 struct sunxi_gpio_pin *pin = priv; 346 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 347 uint32_t data; 348 int val; 349 350 KASSERT(sc == pin->pin_sc); 351 352 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 353 const uint32_t data_mask = __BIT(pin_def->pin); 354 355 /* No lock required for reads */ 356 data = GPIO_READ(sc, data_reg); 357 val = __SHIFTOUT(data, data_mask); 358 if (!raw && pin->pin_actlo) 359 val = !val; 360 361 #ifdef SUNXI_GPIO_DEBUG 362 device_printf(dev, "P%c%02d rd %08x (%d %d)\n", 363 pin_def->port + 'A', pin_def->pin, data, 364 __SHIFTOUT(val, data_mask), val); 365 #endif 366 367 return val; 368 } 369 370 static void 371 sunxi_gpio_write(device_t dev, void *priv, int val, bool raw) 372 { 373 struct sunxi_gpio_softc * const sc = device_private(dev); 374 struct sunxi_gpio_pin *pin = priv; 375 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 376 uint32_t data; 377 378 KASSERT(sc == pin->pin_sc); 379 380 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 381 const uint32_t data_mask = __BIT(pin_def->pin); 382 383 if (!raw && pin->pin_actlo) 384 val = !val; 385 386 mutex_enter(&sc->sc_lock); 387 data = GPIO_READ(sc, data_reg); 388 data &= ~data_mask; 389 data |= __SHIFTIN(val, data_mask); 390 #ifdef SUNXI_GPIO_DEBUG 391 device_printf(dev, "P%c%02d wr %08x -> %08x\n", 392 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, data_reg), data); 393 #endif 394 GPIO_WRITE(sc, data_reg, data); 395 mutex_exit(&sc->sc_lock); 396 } 397 398 static struct fdtbus_gpio_controller_func sunxi_gpio_funcs = { 399 .acquire = sunxi_gpio_acquire, 400 .release = sunxi_gpio_release, 401 .read = sunxi_gpio_read, 402 .write = sunxi_gpio_write, 403 }; 404 405 static int 406 sunxi_gpio_intr(void *priv) 407 { 408 struct sunxi_gpio_softc * const sc = priv; 409 struct sunxi_gpio_eint *eint; 410 uint32_t status, bit; 411 u_int bank; 412 int ret = 0; 413 414 for (bank = 0; bank <= sc->sc_eint_bank_max; bank++) { 415 status = GPIO_READ(sc, SUNXI_GPIO_INT_STATUS(bank)); 416 if (status == 0) 417 continue; 418 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(bank), status); 419 420 while ((bit = ffs32(status)) != 0) { 421 status &= ~__BIT(bit - 1); 422 eint = &sc->sc_eint[bank][bit - 1]; 423 if (eint->eint_func == NULL) 424 continue; 425 const bool mpsafe = (eint->eint_flags & FDT_INTR_MPSAFE) != 0; 426 if (!mpsafe) 427 KERNEL_LOCK(1, curlwp); 428 ret |= eint->eint_func(eint->eint_arg); 429 if (!mpsafe) 430 KERNEL_UNLOCK_ONE(curlwp); 431 } 432 } 433 434 return ret; 435 } 436 437 static void * 438 sunxi_gpio_establish(device_t dev, u_int *specifier, int ipl, int flags, 439 int (*func)(void *), void *arg) 440 { 441 struct sunxi_gpio_softc * const sc = device_private(dev); 442 const struct sunxi_gpio_pins *pin_def; 443 struct sunxi_gpio_eint *eint; 444 uint32_t val; 445 u_int mode; 446 447 if (ipl != IPL_VM) { 448 aprint_error_dev(dev, "%s: wrong IPL %d (expected %d)\n", 449 __func__, ipl, IPL_VM); 450 return NULL; 451 } 452 453 /* 1st cell is the bank */ 454 /* 2nd cell is the pin */ 455 /* 3rd cell is flags */ 456 const u_int port = be32toh(specifier[0]); 457 const u_int pin = be32toh(specifier[1]); 458 const u_int type = be32toh(specifier[2]) & 0xf; 459 460 switch (type) { 461 case FDT_INTR_TYPE_POS_EDGE: 462 mode = SUNXI_GPIO_INT_MODE_POS_EDGE; 463 break; 464 case FDT_INTR_TYPE_NEG_EDGE: 465 mode = SUNXI_GPIO_INT_MODE_NEG_EDGE; 466 break; 467 case FDT_INTR_TYPE_DOUBLE_EDGE: 468 mode = SUNXI_GPIO_INT_MODE_DOUBLE_EDGE; 469 break; 470 case FDT_INTR_TYPE_HIGH_LEVEL: 471 mode = SUNXI_GPIO_INT_MODE_HIGH_LEVEL; 472 break; 473 case FDT_INTR_TYPE_LOW_LEVEL: 474 mode = SUNXI_GPIO_INT_MODE_LOW_LEVEL; 475 break; 476 default: 477 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 478 __func__, type); 479 return NULL; 480 } 481 482 pin_def = sunxi_gpio_lookup(sc, port, pin); 483 if (pin_def == NULL) 484 return NULL; 485 if (pin_def->functions[pin_def->eint_func] == NULL || 486 strcmp(pin_def->functions[pin_def->eint_func], "irq") != 0) 487 return NULL; 488 489 KASSERT(pin_def->eint_num < SUNXI_GPIO_MAX_EINT); 490 491 mutex_enter(&sc->sc_lock); 492 493 eint = &sc->sc_eint[pin_def->eint_bank][pin_def->eint_num]; 494 if (eint->eint_func != NULL) { 495 mutex_exit(&sc->sc_lock); 496 return NULL; /* in use */ 497 } 498 499 /* Set function */ 500 if (sunxi_gpio_setfunc(sc, pin_def, "irq") != 0) { 501 mutex_exit(&sc->sc_lock); 502 return NULL; 503 } 504 505 eint->eint_func = func; 506 eint->eint_arg = arg; 507 eint->eint_flags = flags; 508 eint->eint_bank = pin_def->eint_bank; 509 eint->eint_num = pin_def->eint_num; 510 511 /* Configure eint mode */ 512 val = GPIO_READ(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num)); 513 val &= ~SUNXI_GPIO_INT_MODEMASK(eint->eint_num); 514 val |= __SHIFTIN(mode, SUNXI_GPIO_INT_MODEMASK(eint->eint_num)); 515 GPIO_WRITE(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num), val); 516 517 /* Enable eint */ 518 val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank)); 519 val |= __BIT(eint->eint_num); 520 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val); 521 522 mutex_exit(&sc->sc_lock); 523 524 return eint; 525 } 526 527 static void 528 sunxi_gpio_disestablish(device_t dev, void *ih) 529 { 530 struct sunxi_gpio_softc * const sc = device_private(dev); 531 struct sunxi_gpio_eint * const eint = ih; 532 uint32_t val; 533 534 KASSERT(eint->eint_func != NULL); 535 536 mutex_enter(&sc->sc_lock); 537 538 /* Disable eint */ 539 val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank)); 540 val &= ~__BIT(eint->eint_num); 541 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val); 542 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(eint->eint_bank), __BIT(eint->eint_num)); 543 544 eint->eint_func = NULL; 545 eint->eint_arg = NULL; 546 eint->eint_flags = 0; 547 548 mutex_exit(&sc->sc_lock); 549 } 550 551 static bool 552 sunxi_gpio_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 553 { 554 struct sunxi_gpio_softc * const sc = device_private(dev); 555 const struct sunxi_gpio_pins *pin_def; 556 557 /* 1st cell is the bank */ 558 /* 2nd cell is the pin */ 559 /* 3rd cell is flags */ 560 if (!specifier) 561 return false; 562 const u_int port = be32toh(specifier[0]); 563 const u_int pin = be32toh(specifier[1]); 564 565 pin_def = sunxi_gpio_lookup(sc, port, pin); 566 if (pin_def == NULL) 567 return false; 568 569 snprintf(buf, buflen, "GPIO %s", pin_def->name); 570 571 return true; 572 } 573 574 static struct fdtbus_interrupt_controller_func sunxi_gpio_intrfuncs = { 575 .establish = sunxi_gpio_establish, 576 .disestablish = sunxi_gpio_disestablish, 577 .intrstr = sunxi_gpio_intrstr, 578 }; 579 580 static const char * 581 sunxi_pinctrl_parse_function(int phandle) 582 { 583 const char *function; 584 585 function = fdtbus_pinctrl_parse_function(phandle); 586 if (function != NULL) 587 return function; 588 589 return fdtbus_get_string(phandle, "allwinner,function"); 590 } 591 592 static const char * 593 sunxi_pinctrl_parse_pins(int phandle, int *pins_len) 594 { 595 const char *pins; 596 int len; 597 598 pins = fdtbus_pinctrl_parse_pins(phandle, pins_len); 599 if (pins != NULL) 600 return pins; 601 602 len = OF_getproplen(phandle, "allwinner,pins"); 603 if (len > 0) { 604 *pins_len = len; 605 return fdtbus_get_string(phandle, "allwinner,pins"); 606 } 607 608 return NULL; 609 } 610 611 static int 612 sunxi_pinctrl_parse_bias(int phandle) 613 { 614 u_int pull; 615 int bias; 616 617 bias = fdtbus_pinctrl_parse_bias(phandle, NULL); 618 if (bias != -1) 619 return bias; 620 621 if (of_getprop_uint32(phandle, "allwinner,pull", &pull) == 0) { 622 switch (pull) { 623 case 0: 624 bias = 0; 625 break; 626 case 1: 627 bias = GPIO_PIN_PULLUP; 628 break; 629 case 2: 630 bias = GPIO_PIN_PULLDOWN; 631 break; 632 } 633 } 634 635 return bias; 636 } 637 638 static int 639 sunxi_pinctrl_parse_drive_strength(int phandle) 640 { 641 int val; 642 643 val = fdtbus_pinctrl_parse_drive_strength(phandle); 644 if (val != -1) 645 return val; 646 647 if (of_getprop_uint32(phandle, "allwinner,drive", &val) == 0) 648 return (val + 1) * 10; 649 650 return -1; 651 } 652 653 static int 654 sunxi_pinctrl_set_config(device_t dev, const void *data, size_t len) 655 { 656 struct sunxi_gpio_softc * const sc = device_private(dev); 657 const struct sunxi_gpio_pins *pin_def; 658 int pins_len; 659 660 if (len != 4) 661 return -1; 662 663 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 664 665 /* 666 * Required: pins, function 667 * Optional: bias, drive strength 668 */ 669 670 const char *function = sunxi_pinctrl_parse_function(phandle); 671 if (function == NULL) 672 return -1; 673 const char *pins = sunxi_pinctrl_parse_pins(phandle, &pins_len); 674 if (pins == NULL) 675 return -1; 676 677 const int bias = sunxi_pinctrl_parse_bias(phandle); 678 const int drive_strength = sunxi_pinctrl_parse_drive_strength(phandle); 679 680 mutex_enter(&sc->sc_lock); 681 682 for (; pins_len > 0; 683 pins_len -= strlen(pins) + 1, pins += strlen(pins) + 1) { 684 pin_def = sunxi_gpio_lookup_byname(sc, pins); 685 if (pin_def == NULL) { 686 aprint_error_dev(dev, "unknown pin name '%s'\n", pins); 687 continue; 688 } 689 if (sunxi_gpio_setfunc(sc, pin_def, function) != 0) 690 continue; 691 692 if (bias != -1) 693 sunxi_gpio_setpull(sc, pin_def, bias); 694 695 if (drive_strength != -1) 696 sunxi_gpio_setdrv(sc, pin_def, drive_strength); 697 } 698 699 mutex_exit(&sc->sc_lock); 700 701 return 0; 702 } 703 704 static struct fdtbus_pinctrl_controller_func sunxi_pinctrl_funcs = { 705 .set_config = sunxi_pinctrl_set_config, 706 }; 707 708 static int 709 sunxi_gpio_pin_read(void *priv, int pin) 710 { 711 struct sunxi_gpio_softc * const sc = priv; 712 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 713 uint32_t data; 714 int val; 715 716 KASSERT(pin < sc->sc_padconf->npins); 717 718 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 719 const uint32_t data_mask = __BIT(pin_def->pin); 720 721 /* No lock required for reads */ 722 data = GPIO_READ(sc, data_reg); 723 val = __SHIFTOUT(data, data_mask); 724 725 return val; 726 } 727 728 static void 729 sunxi_gpio_pin_write(void *priv, int pin, int val) 730 { 731 struct sunxi_gpio_softc * const sc = priv; 732 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 733 uint32_t data; 734 735 KASSERT(pin < sc->sc_padconf->npins); 736 737 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 738 const uint32_t data_mask = __BIT(pin_def->pin); 739 740 mutex_enter(&sc->sc_lock); 741 data = GPIO_READ(sc, data_reg); 742 if (val) 743 data |= data_mask; 744 else 745 data &= ~data_mask; 746 GPIO_WRITE(sc, data_reg, data); 747 mutex_exit(&sc->sc_lock); 748 } 749 750 static void 751 sunxi_gpio_pin_ctl(void *priv, int pin, int flags) 752 { 753 struct sunxi_gpio_softc * const sc = priv; 754 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 755 756 KASSERT(pin < sc->sc_padconf->npins); 757 758 mutex_enter(&sc->sc_lock); 759 sunxi_gpio_ctl(sc, pin_def, flags); 760 sunxi_gpio_setpull(sc, pin_def, flags); 761 mutex_exit(&sc->sc_lock); 762 } 763 764 static void 765 sunxi_gpio_attach_ports(struct sunxi_gpio_softc *sc) 766 { 767 const struct sunxi_gpio_pins *pin_def; 768 struct gpio_chipset_tag *gp = &sc->sc_gp; 769 struct gpiobus_attach_args gba; 770 u_int pin; 771 772 gp->gp_cookie = sc; 773 gp->gp_pin_read = sunxi_gpio_pin_read; 774 gp->gp_pin_write = sunxi_gpio_pin_write; 775 gp->gp_pin_ctl = sunxi_gpio_pin_ctl; 776 777 const u_int npins = sc->sc_padconf->npins; 778 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * npins, KM_SLEEP); 779 780 for (pin = 0; pin < sc->sc_padconf->npins; pin++) { 781 pin_def = &sc->sc_padconf->pins[pin]; 782 sc->sc_pins[pin].pin_num = pin; 783 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 784 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 785 sc->sc_pins[pin].pin_state = sunxi_gpio_pin_read(sc, pin); 786 strlcpy(sc->sc_pins[pin].pin_defname, pin_def->name, 787 sizeof(sc->sc_pins[pin].pin_defname)); 788 } 789 790 memset(&gba, 0, sizeof(gba)); 791 gba.gba_gc = gp; 792 gba.gba_pins = sc->sc_pins; 793 gba.gba_npins = npins; 794 sc->sc_gpiodev = config_found_ia(sc->sc_dev, "gpiobus", &gba, NULL); 795 } 796 797 static int 798 sunxi_gpio_match(device_t parent, cfdata_t cf, void *aux) 799 { 800 struct fdt_attach_args * const faa = aux; 801 802 return of_match_compat_data(faa->faa_phandle, compat_data); 803 } 804 805 static void 806 sunxi_gpio_attach(device_t parent, device_t self, void *aux) 807 { 808 struct sunxi_gpio_softc * const sc = device_private(self); 809 struct fdt_attach_args * const faa = aux; 810 const int phandle = faa->faa_phandle; 811 char intrstr[128]; 812 struct fdtbus_reset *rst; 813 struct clk *clk; 814 bus_addr_t addr; 815 bus_size_t size; 816 int child; 817 818 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 819 aprint_error(": couldn't get registers\n"); 820 return; 821 } 822 823 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) 824 if (clk_enable(clk) != 0) { 825 aprint_error(": couldn't enable clock\n"); 826 return; 827 } 828 829 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 830 if (fdtbus_reset_deassert(rst) != 0) { 831 aprint_error(": couldn't de-assert reset\n"); 832 return; 833 } 834 835 sc->sc_dev = self; 836 sc->sc_bst = faa->faa_bst; 837 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 838 aprint_error(": couldn't map registers\n"); 839 return; 840 } 841 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 842 sc->sc_padconf = (void *)of_search_compatible(phandle, compat_data)->data; 843 844 aprint_naive("\n"); 845 aprint_normal(": PIO\n"); 846 847 fdtbus_register_gpio_controller(self, phandle, &sunxi_gpio_funcs); 848 849 for (child = OF_child(phandle); child; child = OF_peer(child)) { 850 if (!of_hasprop(child, "function") || !of_hasprop(child, "pins")) 851 continue; 852 fdtbus_register_pinctrl_config(self, child, &sunxi_pinctrl_funcs); 853 } 854 855 fdtbus_pinctrl_configure(); 856 857 sunxi_gpio_attach_ports(sc); 858 859 /* Disable all external interrupts */ 860 for (int i = 0; i < sc->sc_padconf->npins; i++) { 861 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[i]; 862 if (pin_def->eint_func == 0) 863 continue; 864 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(pin_def->eint_bank), __BIT(pin_def->eint_num)); 865 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(pin_def->eint_bank), __BIT(pin_def->eint_num)); 866 867 if (sc->sc_eint_bank_max < pin_def->eint_bank) 868 sc->sc_eint_bank_max = pin_def->eint_bank; 869 } 870 KASSERT(sc->sc_eint_bank_max < SUNXI_GPIO_MAX_EINT_BANK); 871 872 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 873 aprint_error_dev(self, "failed to decode interrupt\n"); 874 return; 875 } 876 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, FDT_INTR_MPSAFE, 877 sunxi_gpio_intr, sc); 878 if (sc->sc_ih == NULL) { 879 aprint_error_dev(self, "failed to establish interrupt on %s\n", 880 intrstr); 881 return; 882 } 883 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 884 fdtbus_register_interrupt_controller(self, phandle, 885 &sunxi_gpio_intrfuncs); 886 } 887
Indexes created Thu Oct 16 14:10:15 GMT 2025