sunxi_gpio.c revision 1.29
1 /* $NetBSD: sunxi_gpio.c,v 1.29 2021/01/15 00:38:23 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.29 2021/01/15 00:38:23 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 #include <sys/kmem.h> 41 #include <sys/gpio.h> 42 #include <sys/bitops.h> 43 #include <sys/lwp.h> 44 45 #include <dev/fdt/fdtvar.h> 46 #include <dev/gpio/gpiovar.h> 47 48 #include <arm/sunxi/sunxi_gpio.h> 49 50 #define SUNXI_GPIO_MAX_EINT_BANK 5 51 #define SUNXI_GPIO_MAX_EINT 32 52 53 #define SUNXI_GPIO_MAX_BANK 26 54 55 #define SUNXI_GPIO_PORT(port) (0x24 * (port)) 56 #define SUNXI_GPIO_CFG(port, pin) (SUNXI_GPIO_PORT(port) + 0x00 + (0x4 * ((pin) / 8))) 57 #define SUNXI_GPIO_CFG_PINMASK(pin) (0x7U << (((pin) % 8) * 4)) 58 #define SUNXI_GPIO_DATA(port) (SUNXI_GPIO_PORT(port) + 0x10) 59 #define SUNXI_GPIO_DRV(port, pin) (SUNXI_GPIO_PORT(port) + 0x14 + (0x4 * ((pin) / 16))) 60 #define SUNXI_GPIO_DRV_PINMASK(pin) (0x3U << (((pin) % 16) * 2)) 61 #define SUNXI_GPIO_PULL(port, pin) (SUNXI_GPIO_PORT(port) + 0x1c + (0x4 * ((pin) / 16))) 62 #define SUNXI_GPIO_PULL_DISABLE 0 63 #define SUNXI_GPIO_PULL_UP 1 64 #define SUNXI_GPIO_PULL_DOWN 2 65 #define SUNXI_GPIO_PULL_PINMASK(pin) (0x3U << (((pin) % 16) * 2)) 66 #define SUNXI_GPIO_INT_CFG(bank, eint) (0x200 + (0x20 * (bank)) + (0x4 * ((eint) / 8))) 67 #define SUNXI_GPIO_INT_MODEMASK(eint) (0xfU << (((eint) % 8) * 4)) 68 #define SUNXI_GPIO_INT_MODE_POS_EDGE 0x0 69 #define SUNXI_GPIO_INT_MODE_NEG_EDGE 0x1 70 #define SUNXI_GPIO_INT_MODE_HIGH_LEVEL 0x2 71 #define SUNXI_GPIO_INT_MODE_LOW_LEVEL 0x3 72 #define SUNXI_GPIO_INT_MODE_DOUBLE_EDGE 0x4 73 #define SUNXI_GPIO_INT_CTL(bank) (0x210 + 0x20 * (bank)) 74 #define SUNXI_GPIO_INT_STATUS(bank) (0x214 + 0x20 * (bank)) 75 #define SUNXI_GPIO_INT_DEBOUNCE(bank) (0x218 + 0x20 * (bank)) 76 #define SUNXI_GPIO_INT_DEBOUNCE_CLK_PRESCALE __BITS(6,4) 77 #define SUNXI_GPIO_INT_DEBOUNCE_CLK_SEL __BIT(0) 78 #define SUNXI_GPIO_GRP_CONFIG(bank) (0x300 + 0x4 * (bank)) 79 #define SUNXI_GPIO_GRP_IO_BIAS_CONFIGMASK 0xf 80 81 static const struct of_compat_data compat_data[] = { 82 #ifdef SOC_SUN4I_A10 83 { "allwinner,sun4i-a10-pinctrl", (uintptr_t)&sun4i_a10_padconf }, 84 #endif 85 #ifdef SOC_SUN5I_A13 86 { "allwinner,sun5i-a13-pinctrl", (uintptr_t)&sun5i_a13_padconf }, 87 { "nextthing,gr8-pinctrl", (uintptr_t)&sun5i_a13_padconf }, 88 #endif 89 #ifdef SOC_SUN6I_A31 90 { "allwinner,sun6i-a31-pinctrl", (uintptr_t)&sun6i_a31_padconf }, 91 { "allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&sun6i_a31_r_padconf }, 92 #endif 93 #ifdef SOC_SUN7I_A20 94 { "allwinner,sun7i-a20-pinctrl", (uintptr_t)&sun7i_a20_padconf }, 95 #endif 96 #ifdef SOC_SUN8I_A83T 97 { "allwinner,sun8i-a83t-pinctrl", (uintptr_t)&sun8i_a83t_padconf }, 98 { "allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&sun8i_a83t_r_padconf }, 99 #endif 100 #ifdef SOC_SUN8I_H3 101 { "allwinner,sun8i-h3-pinctrl", (uintptr_t)&sun8i_h3_padconf }, 102 { "allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&sun8i_h3_r_padconf }, 103 #endif 104 #ifdef SOC_SUN9I_A80 105 { "allwinner,sun9i-a80-pinctrl", (uintptr_t)&sun9i_a80_padconf }, 106 { "allwinner,sun9i-a80-r-pinctrl", (uintptr_t)&sun9i_a80_r_padconf }, 107 #endif 108 #ifdef SOC_SUN50I_A64 109 { "allwinner,sun50i-a64-pinctrl", (uintptr_t)&sun50i_a64_padconf }, 110 { "allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&sun50i_a64_r_padconf }, 111 #endif 112 #ifdef SOC_SUN50I_H5 113 { "allwinner,sun50i-h5-pinctrl", (uintptr_t)&sun8i_h3_padconf }, 114 { "allwinner,sun50i-h5-r-pinctrl", (uintptr_t)&sun8i_h3_r_padconf }, 115 #endif 116 #ifdef SOC_SUN50I_H6 117 { "allwinner,sun50i-h6-pinctrl", (uintptr_t)&sun50i_h6_padconf }, 118 { "allwinner,sun50i-h6-r-pinctrl", (uintptr_t)&sun50i_h6_r_padconf }, 119 #endif 120 { NULL } 121 }; 122 123 struct sunxi_gpio_eint { 124 int (*eint_func)(void *); 125 void *eint_arg; 126 bool eint_mpsafe; 127 int eint_bank; 128 int eint_num; 129 }; 130 131 struct sunxi_gpio_softc { 132 device_t sc_dev; 133 bus_space_tag_t sc_bst; 134 bus_space_handle_t sc_bsh; 135 int sc_phandle; 136 const struct sunxi_gpio_padconf *sc_padconf; 137 kmutex_t sc_lock; 138 139 struct gpio_chipset_tag sc_gp; 140 gpio_pin_t *sc_pins; 141 device_t sc_gpiodev; 142 143 struct fdtbus_regulator *sc_pin_supply[SUNXI_GPIO_MAX_BANK]; 144 145 u_int sc_eint_bank_max; 146 147 void *sc_ih; 148 struct sunxi_gpio_eint sc_eint[SUNXI_GPIO_MAX_EINT_BANK][SUNXI_GPIO_MAX_EINT]; 149 }; 150 151 struct sunxi_gpio_pin { 152 struct sunxi_gpio_softc *pin_sc; 153 const struct sunxi_gpio_pins *pin_def; 154 int pin_flags; 155 bool pin_actlo; 156 }; 157 158 #define GPIO_READ(sc, reg) \ 159 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 160 #define GPIO_WRITE(sc, reg, val) \ 161 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 162 163 static int sunxi_gpio_match(device_t, cfdata_t, void *); 164 static void sunxi_gpio_attach(device_t, device_t, void *); 165 166 CFATTACH_DECL_NEW(sunxi_gpio, sizeof(struct sunxi_gpio_softc), 167 sunxi_gpio_match, sunxi_gpio_attach, NULL, NULL); 168 169 static const struct sunxi_gpio_pins * 170 sunxi_gpio_lookup(struct sunxi_gpio_softc *sc, uint8_t port, uint8_t pin) 171 { 172 const struct sunxi_gpio_pins *pin_def; 173 u_int n; 174 175 for (n = 0; n < sc->sc_padconf->npins; n++) { 176 pin_def = &sc->sc_padconf->pins[n]; 177 if (pin_def->port == port && pin_def->pin == pin) 178 return pin_def; 179 } 180 181 return NULL; 182 } 183 184 static const struct sunxi_gpio_pins * 185 sunxi_gpio_lookup_byname(struct sunxi_gpio_softc *sc, const char *name) 186 { 187 const struct sunxi_gpio_pins *pin_def; 188 u_int n; 189 190 for (n = 0; n < sc->sc_padconf->npins; n++) { 191 pin_def = &sc->sc_padconf->pins[n]; 192 if (strcmp(pin_def->name, name) == 0) 193 return pin_def; 194 } 195 196 return NULL; 197 } 198 199 static int 200 sunxi_gpio_setfunc(struct sunxi_gpio_softc *sc, 201 const struct sunxi_gpio_pins *pin_def, const char *func) 202 { 203 uint32_t cfg; 204 u_int n; 205 206 KASSERT(mutex_owned(&sc->sc_lock)); 207 208 const bus_size_t cfg_reg = SUNXI_GPIO_CFG(pin_def->port, pin_def->pin); 209 const uint32_t cfg_mask = SUNXI_GPIO_CFG_PINMASK(pin_def->pin); 210 211 for (n = 0; n < SUNXI_GPIO_MAXFUNC; n++) { 212 if (pin_def->functions[n] == NULL) 213 continue; 214 if (strcmp(pin_def->functions[n], func) == 0) { 215 cfg = GPIO_READ(sc, cfg_reg); 216 cfg &= ~cfg_mask; 217 cfg |= __SHIFTIN(n, cfg_mask); 218 #ifdef SUNXI_GPIO_DEBUG 219 device_printf(sc->sc_dev, "P%c%02d cfg %08x -> %08x\n", 220 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, cfg_reg), cfg); 221 #endif 222 GPIO_WRITE(sc, cfg_reg, cfg); 223 return 0; 224 } 225 } 226 227 /* Function not found */ 228 device_printf(sc->sc_dev, "function '%s' not supported on P%c%02d\n", 229 func, pin_def->port + 'A', pin_def->pin); 230 231 return ENXIO; 232 } 233 234 static int 235 sunxi_gpio_setpull(struct sunxi_gpio_softc *sc, 236 const struct sunxi_gpio_pins *pin_def, int flags) 237 { 238 uint32_t pull; 239 240 KASSERT(mutex_owned(&sc->sc_lock)); 241 242 const bus_size_t pull_reg = SUNXI_GPIO_PULL(pin_def->port, pin_def->pin); 243 const uint32_t pull_mask = SUNXI_GPIO_PULL_PINMASK(pin_def->pin); 244 245 pull = GPIO_READ(sc, pull_reg); 246 pull &= ~pull_mask; 247 if (flags & GPIO_PIN_PULLUP) 248 pull |= __SHIFTIN(SUNXI_GPIO_PULL_UP, pull_mask); 249 else if (flags & GPIO_PIN_PULLDOWN) 250 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DOWN, pull_mask); 251 else 252 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DISABLE, pull_mask); 253 #ifdef SUNXI_GPIO_DEBUG 254 device_printf(sc->sc_dev, "P%c%02d pull %08x -> %08x\n", 255 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, pull_reg), pull); 256 #endif 257 GPIO_WRITE(sc, pull_reg, pull); 258 259 return 0; 260 } 261 262 static int 263 sunxi_gpio_setdrv(struct sunxi_gpio_softc *sc, 264 const struct sunxi_gpio_pins *pin_def, int drive_strength) 265 { 266 uint32_t drv; 267 268 KASSERT(mutex_owned(&sc->sc_lock)); 269 270 if (drive_strength < 10 || drive_strength > 40) 271 return EINVAL; 272 273 const bus_size_t drv_reg = SUNXI_GPIO_DRV(pin_def->port, pin_def->pin); 274 const uint32_t drv_mask = SUNXI_GPIO_DRV_PINMASK(pin_def->pin); 275 276 drv = GPIO_READ(sc, drv_reg); 277 drv &= ~drv_mask; 278 drv |= __SHIFTIN((drive_strength / 10) - 1, drv_mask); 279 #ifdef SUNXI_GPIO_DEBUG 280 device_printf(sc->sc_dev, "P%c%02d drv %08x -> %08x\n", 281 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, drv_reg), drv); 282 #endif 283 GPIO_WRITE(sc, drv_reg, drv); 284 285 return 0; 286 } 287 288 static int 289 sunxi_gpio_ctl(struct sunxi_gpio_softc *sc, const struct sunxi_gpio_pins *pin_def, 290 int flags) 291 { 292 KASSERT(mutex_owned(&sc->sc_lock)); 293 294 if (flags & GPIO_PIN_INPUT) 295 return sunxi_gpio_setfunc(sc, pin_def, "gpio_in"); 296 if (flags & GPIO_PIN_OUTPUT) 297 return sunxi_gpio_setfunc(sc, pin_def, "gpio_out"); 298 299 return EINVAL; 300 } 301 302 static void * 303 sunxi_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 304 { 305 struct sunxi_gpio_softc * const sc = device_private(dev); 306 const struct sunxi_gpio_pins *pin_def; 307 struct sunxi_gpio_pin *gpin; 308 const u_int *gpio = data; 309 int error; 310 311 if (len != 16) 312 return NULL; 313 314 const uint8_t port = be32toh(gpio[1]) & 0xff; 315 const uint8_t pin = be32toh(gpio[2]) & 0xff; 316 const bool actlo = be32toh(gpio[3]) & 1; 317 318 pin_def = sunxi_gpio_lookup(sc, port, pin); 319 if (pin_def == NULL) 320 return NULL; 321 322 mutex_enter(&sc->sc_lock); 323 error = sunxi_gpio_ctl(sc, pin_def, flags); 324 mutex_exit(&sc->sc_lock); 325 326 if (error != 0) 327 return NULL; 328 329 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 330 gpin->pin_sc = sc; 331 gpin->pin_def = pin_def; 332 gpin->pin_flags = flags; 333 gpin->pin_actlo = actlo; 334 335 return gpin; 336 } 337 338 static void 339 sunxi_gpio_release(device_t dev, void *priv) 340 { 341 struct sunxi_gpio_softc * const sc = device_private(dev); 342 struct sunxi_gpio_pin *pin = priv; 343 344 mutex_enter(&sc->sc_lock); 345 sunxi_gpio_ctl(pin->pin_sc, pin->pin_def, GPIO_PIN_INPUT); 346 mutex_exit(&sc->sc_lock); 347 348 kmem_free(pin, sizeof(*pin)); 349 } 350 351 static int 352 sunxi_gpio_read(device_t dev, void *priv, bool raw) 353 { 354 struct sunxi_gpio_softc * const sc = device_private(dev); 355 struct sunxi_gpio_pin *pin = priv; 356 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 357 uint32_t data; 358 int val; 359 360 KASSERT(sc == pin->pin_sc); 361 362 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 363 const uint32_t data_mask = __BIT(pin_def->pin); 364 365 /* No lock required for reads */ 366 data = GPIO_READ(sc, data_reg); 367 val = __SHIFTOUT(data, data_mask); 368 if (!raw && pin->pin_actlo) 369 val = !val; 370 371 #ifdef SUNXI_GPIO_DEBUG 372 device_printf(dev, "P%c%02d rd %08x (%d %d)\n", 373 pin_def->port + 'A', pin_def->pin, data, 374 __SHIFTOUT(val, data_mask), val); 375 #endif 376 377 return val; 378 } 379 380 static void 381 sunxi_gpio_write(device_t dev, void *priv, int val, bool raw) 382 { 383 struct sunxi_gpio_softc * const sc = device_private(dev); 384 struct sunxi_gpio_pin *pin = priv; 385 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 386 uint32_t data; 387 388 KASSERT(sc == pin->pin_sc); 389 390 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 391 const uint32_t data_mask = __BIT(pin_def->pin); 392 393 if (!raw && pin->pin_actlo) 394 val = !val; 395 396 mutex_enter(&sc->sc_lock); 397 data = GPIO_READ(sc, data_reg); 398 data &= ~data_mask; 399 data |= __SHIFTIN(val, data_mask); 400 #ifdef SUNXI_GPIO_DEBUG 401 device_printf(dev, "P%c%02d wr %08x -> %08x\n", 402 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, data_reg), data); 403 #endif 404 GPIO_WRITE(sc, data_reg, data); 405 mutex_exit(&sc->sc_lock); 406 } 407 408 static struct fdtbus_gpio_controller_func sunxi_gpio_funcs = { 409 .acquire = sunxi_gpio_acquire, 410 .release = sunxi_gpio_release, 411 .read = sunxi_gpio_read, 412 .write = sunxi_gpio_write, 413 }; 414 415 static int 416 sunxi_gpio_intr(void *priv) 417 { 418 struct sunxi_gpio_softc * const sc = priv; 419 struct sunxi_gpio_eint *eint; 420 uint32_t status, bit; 421 u_int bank; 422 int ret = 0; 423 424 for (bank = 0; bank <= sc->sc_eint_bank_max; bank++) { 425 status = GPIO_READ(sc, SUNXI_GPIO_INT_STATUS(bank)); 426 if (status == 0) 427 continue; 428 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(bank), status); 429 430 while ((bit = ffs32(status)) != 0) { 431 status &= ~__BIT(bit - 1); 432 eint = &sc->sc_eint[bank][bit - 1]; 433 if (eint->eint_func == NULL) 434 continue; 435 if (!eint->eint_mpsafe) 436 KERNEL_LOCK(1, curlwp); 437 ret |= eint->eint_func(eint->eint_arg); 438 if (!eint->eint_mpsafe) 439 KERNEL_UNLOCK_ONE(curlwp); 440 } 441 } 442 443 return ret; 444 } 445 446 static void * 447 sunxi_intr_enable(struct sunxi_gpio_softc *sc, 448 const struct sunxi_gpio_pins *pin_def, u_int mode, bool mpsafe, 449 int (*func)(void *), void *arg) 450 { 451 uint32_t val; 452 struct sunxi_gpio_eint *eint; 453 454 if (pin_def->functions[pin_def->eint_func] == NULL || 455 strcmp(pin_def->functions[pin_def->eint_func], "irq") != 0) 456 return NULL; 457 458 KASSERT(pin_def->eint_num < SUNXI_GPIO_MAX_EINT); 459 460 mutex_enter(&sc->sc_lock); 461 462 eint = &sc->sc_eint[pin_def->eint_bank][pin_def->eint_num]; 463 if (eint->eint_func != NULL) { 464 mutex_exit(&sc->sc_lock); 465 return NULL; /* in use */ 466 } 467 468 /* Set function */ 469 if (sunxi_gpio_setfunc(sc, pin_def, "irq") != 0) { 470 mutex_exit(&sc->sc_lock); 471 return NULL; 472 } 473 474 eint->eint_func = func; 475 eint->eint_arg = arg; 476 eint->eint_mpsafe = mpsafe; 477 eint->eint_bank = pin_def->eint_bank; 478 eint->eint_num = pin_def->eint_num; 479 480 /* Configure eint mode */ 481 val = GPIO_READ(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num)); 482 val &= ~SUNXI_GPIO_INT_MODEMASK(eint->eint_num); 483 val |= __SHIFTIN(mode, SUNXI_GPIO_INT_MODEMASK(eint->eint_num)); 484 GPIO_WRITE(sc, SUNXI_GPIO_INT_CFG(eint->eint_bank, eint->eint_num), val); 485 486 val = SUNXI_GPIO_INT_DEBOUNCE_CLK_SEL; 487 GPIO_WRITE(sc, SUNXI_GPIO_INT_DEBOUNCE(eint->eint_bank), val); 488 489 /* Enable eint */ 490 val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank)); 491 val |= __BIT(eint->eint_num); 492 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val); 493 494 mutex_exit(&sc->sc_lock); 495 496 return eint; 497 } 498 499 static void 500 sunxi_intr_disable(struct sunxi_gpio_softc *sc, struct sunxi_gpio_eint *eint) 501 { 502 uint32_t val; 503 504 KASSERT(eint->eint_func != NULL); 505 506 mutex_enter(&sc->sc_lock); 507 508 /* Disable eint */ 509 val = GPIO_READ(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank)); 510 val &= ~__BIT(eint->eint_num); 511 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(eint->eint_bank), val); 512 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(eint->eint_bank), __BIT(eint->eint_num)); 513 514 eint->eint_func = NULL; 515 eint->eint_arg = NULL; 516 eint->eint_mpsafe = false; 517 518 mutex_exit(&sc->sc_lock); 519 } 520 521 static void * 522 sunxi_fdt_intr_establish(device_t dev, u_int *specifier, int ipl, int flags, 523 int (*func)(void *), void *arg, const char *xname) 524 { 525 struct sunxi_gpio_softc * const sc = device_private(dev); 526 bool mpsafe = (flags & FDT_INTR_MPSAFE) != 0; 527 const struct sunxi_gpio_pins *pin_def; 528 u_int mode; 529 530 if (ipl != IPL_VM) { 531 aprint_error_dev(dev, "%s: wrong IPL %d (expected %d)\n", 532 __func__, ipl, IPL_VM); 533 return NULL; 534 } 535 536 /* 1st cell is the bank */ 537 /* 2nd cell is the pin */ 538 /* 3rd cell is flags */ 539 const u_int port = be32toh(specifier[0]); 540 const u_int pin = be32toh(specifier[1]); 541 const u_int type = be32toh(specifier[2]) & 0xf; 542 543 switch (type) { 544 case FDT_INTR_TYPE_POS_EDGE: 545 mode = SUNXI_GPIO_INT_MODE_POS_EDGE; 546 break; 547 case FDT_INTR_TYPE_NEG_EDGE: 548 mode = SUNXI_GPIO_INT_MODE_NEG_EDGE; 549 break; 550 case FDT_INTR_TYPE_DOUBLE_EDGE: 551 mode = SUNXI_GPIO_INT_MODE_DOUBLE_EDGE; 552 break; 553 case FDT_INTR_TYPE_HIGH_LEVEL: 554 mode = SUNXI_GPIO_INT_MODE_HIGH_LEVEL; 555 break; 556 case FDT_INTR_TYPE_LOW_LEVEL: 557 mode = SUNXI_GPIO_INT_MODE_LOW_LEVEL; 558 break; 559 default: 560 aprint_error_dev(dev, "%s: unsupported irq type 0x%x\n", 561 __func__, type); 562 return NULL; 563 } 564 565 pin_def = sunxi_gpio_lookup(sc, port, pin); 566 if (pin_def == NULL) 567 return NULL; 568 569 return sunxi_intr_enable(sc, pin_def, mode, mpsafe, func, arg); 570 } 571 572 static void 573 sunxi_fdt_intr_disestablish(device_t dev, void *ih) 574 { 575 struct sunxi_gpio_softc * const sc = device_private(dev); 576 struct sunxi_gpio_eint * const eint = ih; 577 578 sunxi_intr_disable(sc, eint); 579 } 580 581 static bool 582 sunxi_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 583 { 584 struct sunxi_gpio_softc * const sc = device_private(dev); 585 const struct sunxi_gpio_pins *pin_def; 586 587 /* 1st cell is the bank */ 588 /* 2nd cell is the pin */ 589 /* 3rd cell is flags */ 590 if (!specifier) 591 return false; 592 const u_int port = be32toh(specifier[0]); 593 const u_int pin = be32toh(specifier[1]); 594 595 pin_def = sunxi_gpio_lookup(sc, port, pin); 596 if (pin_def == NULL) 597 return false; 598 599 snprintf(buf, buflen, "GPIO %s", pin_def->name); 600 601 return true; 602 } 603 604 static struct fdtbus_interrupt_controller_func sunxi_gpio_intrfuncs = { 605 .establish = sunxi_fdt_intr_establish, 606 .disestablish = sunxi_fdt_intr_disestablish, 607 .intrstr = sunxi_fdt_intrstr, 608 }; 609 610 static void * 611 sunxi_gpio_intr_establish(void *vsc, int pin, int ipl, int irqmode, 612 int (*func)(void *), void *arg) 613 { 614 struct sunxi_gpio_softc * const sc = vsc; 615 bool mpsafe = (irqmode & GPIO_INTR_MPSAFE) != 0; 616 int type = irqmode & GPIO_INTR_MODE_MASK; 617 const struct sunxi_gpio_pins *pin_def; 618 u_int mode; 619 620 switch (type) { 621 case GPIO_INTR_POS_EDGE: 622 mode = SUNXI_GPIO_INT_MODE_POS_EDGE; 623 break; 624 case GPIO_INTR_NEG_EDGE: 625 mode = SUNXI_GPIO_INT_MODE_NEG_EDGE; 626 break; 627 case GPIO_INTR_DOUBLE_EDGE: 628 mode = SUNXI_GPIO_INT_MODE_DOUBLE_EDGE; 629 break; 630 case GPIO_INTR_HIGH_LEVEL: 631 mode = SUNXI_GPIO_INT_MODE_HIGH_LEVEL; 632 break; 633 case GPIO_INTR_LOW_LEVEL: 634 mode = SUNXI_GPIO_INT_MODE_LOW_LEVEL; 635 break; 636 default: 637 aprint_error_dev(sc->sc_dev, "%s: unsupported irq type 0x%x\n", 638 __func__, type); 639 return NULL; 640 } 641 642 if (pin < 0 || pin >= sc->sc_padconf->npins) 643 return NULL; 644 pin_def = &sc->sc_padconf->pins[pin]; 645 646 return sunxi_intr_enable(sc, pin_def, mode, mpsafe, func, arg); 647 } 648 649 static void 650 sunxi_gpio_intr_disestablish(void *vsc, void *ih) 651 { 652 struct sunxi_gpio_softc * const sc = vsc; 653 struct sunxi_gpio_eint * const eint = ih; 654 655 sunxi_intr_disable(sc, eint); 656 } 657 658 static bool 659 sunxi_gpio_intrstr(void *vsc, int pin, int irqmode, char *buf, size_t buflen) 660 { 661 struct sunxi_gpio_softc * const sc = vsc; 662 const struct sunxi_gpio_pins *pin_def; 663 664 if (pin < 0 || pin >= sc->sc_padconf->npins) 665 return NULL; 666 pin_def = &sc->sc_padconf->pins[pin]; 667 668 snprintf(buf, buflen, "GPIO %s", pin_def->name); 669 670 return true; 671 } 672 673 static const char * 674 sunxi_pinctrl_parse_function(int phandle) 675 { 676 const char *function; 677 678 function = fdtbus_pinctrl_parse_function(phandle); 679 if (function != NULL) 680 return function; 681 682 return fdtbus_get_string(phandle, "allwinner,function"); 683 } 684 685 static const char * 686 sunxi_pinctrl_parse_pins(int phandle, int *pins_len) 687 { 688 const char *pins; 689 int len; 690 691 pins = fdtbus_pinctrl_parse_pins(phandle, pins_len); 692 if (pins != NULL) 693 return pins; 694 695 len = OF_getproplen(phandle, "allwinner,pins"); 696 if (len > 0) { 697 *pins_len = len; 698 return fdtbus_get_prop(phandle, "allwinner,pins", pins_len); 699 } 700 701 return NULL; 702 } 703 704 static int 705 sunxi_pinctrl_parse_bias(int phandle) 706 { 707 u_int pull; 708 int bias; 709 710 bias = fdtbus_pinctrl_parse_bias(phandle, NULL); 711 if (bias != -1) 712 return bias; 713 714 if (of_getprop_uint32(phandle, "allwinner,pull", &pull) == 0) { 715 switch (pull) { 716 case 0: 717 bias = 0; 718 break; 719 case 1: 720 bias = GPIO_PIN_PULLUP; 721 break; 722 case 2: 723 bias = GPIO_PIN_PULLDOWN; 724 break; 725 } 726 } 727 728 return bias; 729 } 730 731 static int 732 sunxi_pinctrl_parse_drive_strength(int phandle) 733 { 734 int val; 735 736 val = fdtbus_pinctrl_parse_drive_strength(phandle); 737 if (val != -1) 738 return val; 739 740 if (of_getprop_uint32(phandle, "allwinner,drive", &val) == 0) 741 return (val + 1) * 10; 742 743 return -1; 744 } 745 746 static void 747 sunxi_pinctrl_enable_regulator(struct sunxi_gpio_softc *sc, 748 const struct sunxi_gpio_pins *pin_def) 749 { 750 char supply_prop[16]; 751 uint32_t val; 752 u_int uvol; 753 int error; 754 755 const char c = tolower(pin_def->name[1]); 756 if (c < 'a' || c > 'z') 757 return; 758 const int index = c - 'a'; 759 760 if (sc->sc_pin_supply[index] != NULL) { 761 /* Already enabled */ 762 return; 763 } 764 765 snprintf(supply_prop, sizeof(supply_prop), "vcc-p%c-supply", c); 766 sc->sc_pin_supply[index] = fdtbus_regulator_acquire(sc->sc_phandle, supply_prop); 767 if (sc->sc_pin_supply[index] == NULL) 768 return; 769 770 aprint_debug_dev(sc->sc_dev, "enable \"%s\"\n", supply_prop); 771 error = fdtbus_regulator_enable(sc->sc_pin_supply[index]); 772 if (error != 0) 773 aprint_error_dev(sc->sc_dev, "failed to enable %s: %d\n", supply_prop, error); 774 775 if (sc->sc_padconf->has_io_bias_config) { 776 error = fdtbus_regulator_get_voltage(sc->sc_pin_supply[index], &uvol); 777 if (error != 0) { 778 aprint_error_dev(sc->sc_dev, "failed to get %s voltage: %d\n", 779 supply_prop, error); 780 uvol = 0; 781 } 782 if (uvol != 0) { 783 if (uvol <= 1800000) 784 val = 0x0; /* 1.8V */ 785 else if (uvol <= 2500000) 786 val = 0x6; /* 2.5V */ 787 else if (uvol <= 2800000) 788 val = 0x9; /* 2.8V */ 789 else if (uvol <= 3000000) 790 val = 0xa; /* 3.0V */ 791 else 792 val = 0xd; /* 3.3V */ 793 794 aprint_debug_dev(sc->sc_dev, "set io bias config for port %d to 0x%x\n", 795 pin_def->port, val); 796 val = GPIO_READ(sc, SUNXI_GPIO_GRP_CONFIG(pin_def->port)); 797 val &= ~SUNXI_GPIO_GRP_IO_BIAS_CONFIGMASK; 798 val |= __SHIFTIN(val, SUNXI_GPIO_GRP_IO_BIAS_CONFIGMASK); 799 GPIO_WRITE(sc, SUNXI_GPIO_GRP_CONFIG(pin_def->port), val); 800 } 801 } 802 } 803 804 static int 805 sunxi_pinctrl_set_config(device_t dev, const void *data, size_t len) 806 { 807 struct sunxi_gpio_softc * const sc = device_private(dev); 808 const struct sunxi_gpio_pins *pin_def; 809 int pins_len; 810 811 if (len != 4) 812 return -1; 813 814 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 815 816 /* 817 * Required: pins, function 818 * Optional: bias, drive strength 819 */ 820 821 const char *function = sunxi_pinctrl_parse_function(phandle); 822 if (function == NULL) 823 return -1; 824 const char *pins = sunxi_pinctrl_parse_pins(phandle, &pins_len); 825 if (pins == NULL) 826 return -1; 827 828 const int bias = sunxi_pinctrl_parse_bias(phandle); 829 const int drive_strength = sunxi_pinctrl_parse_drive_strength(phandle); 830 831 mutex_enter(&sc->sc_lock); 832 833 for (; pins_len > 0; 834 pins_len -= strlen(pins) + 1, pins += strlen(pins) + 1) { 835 pin_def = sunxi_gpio_lookup_byname(sc, pins); 836 if (pin_def == NULL) { 837 aprint_error_dev(dev, "unknown pin name '%s'\n", pins); 838 continue; 839 } 840 if (sunxi_gpio_setfunc(sc, pin_def, function) != 0) 841 continue; 842 843 if (bias != -1) 844 sunxi_gpio_setpull(sc, pin_def, bias); 845 846 if (drive_strength != -1) 847 sunxi_gpio_setdrv(sc, pin_def, drive_strength); 848 849 sunxi_pinctrl_enable_regulator(sc, pin_def); 850 } 851 852 mutex_exit(&sc->sc_lock); 853 854 return 0; 855 } 856 857 static struct fdtbus_pinctrl_controller_func sunxi_pinctrl_funcs = { 858 .set_config = sunxi_pinctrl_set_config, 859 }; 860 861 static int 862 sunxi_gpio_pin_read(void *priv, int pin) 863 { 864 struct sunxi_gpio_softc * const sc = priv; 865 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 866 uint32_t data; 867 int val; 868 869 KASSERT(pin < sc->sc_padconf->npins); 870 871 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 872 const uint32_t data_mask = __BIT(pin_def->pin); 873 874 /* No lock required for reads */ 875 data = GPIO_READ(sc, data_reg); 876 val = __SHIFTOUT(data, data_mask); 877 878 return val; 879 } 880 881 static void 882 sunxi_gpio_pin_write(void *priv, int pin, int val) 883 { 884 struct sunxi_gpio_softc * const sc = priv; 885 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 886 uint32_t data; 887 888 KASSERT(pin < sc->sc_padconf->npins); 889 890 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 891 const uint32_t data_mask = __BIT(pin_def->pin); 892 893 mutex_enter(&sc->sc_lock); 894 data = GPIO_READ(sc, data_reg); 895 if (val) 896 data |= data_mask; 897 else 898 data &= ~data_mask; 899 GPIO_WRITE(sc, data_reg, data); 900 mutex_exit(&sc->sc_lock); 901 } 902 903 static void 904 sunxi_gpio_pin_ctl(void *priv, int pin, int flags) 905 { 906 struct sunxi_gpio_softc * const sc = priv; 907 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 908 909 KASSERT(pin < sc->sc_padconf->npins); 910 911 mutex_enter(&sc->sc_lock); 912 sunxi_gpio_ctl(sc, pin_def, flags); 913 sunxi_gpio_setpull(sc, pin_def, flags); 914 mutex_exit(&sc->sc_lock); 915 } 916 917 static void 918 sunxi_gpio_attach_ports(struct sunxi_gpio_softc *sc) 919 { 920 const struct sunxi_gpio_pins *pin_def; 921 struct gpio_chipset_tag *gp = &sc->sc_gp; 922 struct gpiobus_attach_args gba; 923 u_int pin; 924 925 gp->gp_cookie = sc; 926 gp->gp_pin_read = sunxi_gpio_pin_read; 927 gp->gp_pin_write = sunxi_gpio_pin_write; 928 gp->gp_pin_ctl = sunxi_gpio_pin_ctl; 929 gp->gp_intr_establish = sunxi_gpio_intr_establish; 930 gp->gp_intr_disestablish = sunxi_gpio_intr_disestablish; 931 gp->gp_intr_str = sunxi_gpio_intrstr; 932 933 const u_int npins = sc->sc_padconf->npins; 934 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * npins, KM_SLEEP); 935 936 for (pin = 0; pin < sc->sc_padconf->npins; pin++) { 937 pin_def = &sc->sc_padconf->pins[pin]; 938 sc->sc_pins[pin].pin_num = pin; 939 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 940 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 941 if (pin_def->functions[pin_def->eint_func] != NULL && 942 strcmp(pin_def->functions[pin_def->eint_func], "irq") == 0) { 943 sc->sc_pins[pin].pin_intrcaps = 944 GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE | 945 GPIO_INTR_HIGH_LEVEL | GPIO_INTR_LOW_LEVEL | 946 GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_MPSAFE; 947 } 948 sc->sc_pins[pin].pin_state = sunxi_gpio_pin_read(sc, pin); 949 strlcpy(sc->sc_pins[pin].pin_defname, pin_def->name, 950 sizeof(sc->sc_pins[pin].pin_defname)); 951 } 952 953 memset(&gba, 0, sizeof(gba)); 954 gba.gba_gc = gp; 955 gba.gba_pins = sc->sc_pins; 956 gba.gba_npins = npins; 957 sc->sc_gpiodev = config_found_ia(sc->sc_dev, "gpiobus", &gba, NULL); 958 } 959 960 static int 961 sunxi_gpio_match(device_t parent, cfdata_t cf, void *aux) 962 { 963 struct fdt_attach_args * const faa = aux; 964 965 return of_match_compat_data(faa->faa_phandle, compat_data); 966 } 967 968 static void 969 sunxi_gpio_attach(device_t parent, device_t self, void *aux) 970 { 971 struct sunxi_gpio_softc * const sc = device_private(self); 972 struct fdt_attach_args * const faa = aux; 973 const int phandle = faa->faa_phandle; 974 char intrstr[128]; 975 struct fdtbus_reset *rst; 976 struct clk *clk; 977 bus_addr_t addr; 978 bus_size_t size; 979 int child; 980 981 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 982 aprint_error(": couldn't get registers\n"); 983 return; 984 } 985 986 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) 987 if (clk_enable(clk) != 0) { 988 aprint_error(": couldn't enable clock\n"); 989 return; 990 } 991 992 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 993 if (fdtbus_reset_deassert(rst) != 0) { 994 aprint_error(": couldn't de-assert reset\n"); 995 return; 996 } 997 998 sc->sc_dev = self; 999 sc->sc_phandle = phandle; 1000 sc->sc_bst = faa->faa_bst; 1001 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 1002 aprint_error(": couldn't map registers\n"); 1003 return; 1004 } 1005 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 1006 sc->sc_padconf = (void *)of_search_compatible(phandle, compat_data)->data; 1007 1008 aprint_naive("\n"); 1009 aprint_normal(": PIO\n"); 1010 1011 fdtbus_register_gpio_controller(self, phandle, &sunxi_gpio_funcs); 1012 1013 for (child = OF_child(phandle); child; child = OF_peer(child)) { 1014 bool is_valid = 1015 (of_hasprop(child, "function") && of_hasprop(child, "pins")) || 1016 (of_hasprop(child, "allwinner,function") && of_hasprop(child, "allwinner,pins")); 1017 if (!is_valid) 1018 continue; 1019 fdtbus_register_pinctrl_config(self, child, &sunxi_pinctrl_funcs); 1020 } 1021 1022 sunxi_gpio_attach_ports(sc); 1023 1024 /* Disable all external interrupts */ 1025 for (int i = 0; i < sc->sc_padconf->npins; i++) { 1026 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[i]; 1027 if (pin_def->eint_func == 0) 1028 continue; 1029 GPIO_WRITE(sc, SUNXI_GPIO_INT_CTL(pin_def->eint_bank), __BIT(pin_def->eint_num)); 1030 GPIO_WRITE(sc, SUNXI_GPIO_INT_STATUS(pin_def->eint_bank), __BIT(pin_def->eint_num)); 1031 1032 if (sc->sc_eint_bank_max < pin_def->eint_bank) 1033 sc->sc_eint_bank_max = pin_def->eint_bank; 1034 } 1035 KASSERT(sc->sc_eint_bank_max < SUNXI_GPIO_MAX_EINT_BANK); 1036 1037 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 1038 aprint_error_dev(self, "failed to decode interrupt\n"); 1039 return; 1040 } 1041 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, FDT_INTR_MPSAFE, 1042 sunxi_gpio_intr, sc); 1043 if (sc->sc_ih == NULL) { 1044 aprint_error_dev(self, "failed to establish interrupt on %s\n", 1045 intrstr); 1046 return; 1047 } 1048 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 1049 fdtbus_register_interrupt_controller(self, phandle, 1050 &sunxi_gpio_intrfuncs); 1051 } 1052
Indexes created Thu Oct 16 14:10:15 GMT 2025