sunxi_gpio.c revision 1.5
1 /* $NetBSD: sunxi_gpio.c,v 1.5 2017/07/06 10:44:19 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.5 2017/07/06 10:44:19 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 #include <sys/kmem.h> 41 #include <sys/gpio.h> 42 43 #include <dev/fdt/fdtvar.h> 44 #include <dev/gpio/gpiovar.h> 45 46 #include <arm/sunxi/sunxi_gpio.h> 47 48 #define SUNXI_GPIO_PORT(port) (0x24 * (port)) 49 #define SUNXI_GPIO_CFG(port, pin) (SUNXI_GPIO_PORT(port) + 0x00 + (0x4 * ((pin) / 8))) 50 #define SUNXI_GPIO_CFG_PINMASK(pin) (0x7 << (((pin) % 8) * 4)) 51 #define SUNXI_GPIO_DATA(port) (SUNXI_GPIO_PORT(port) + 0x10) 52 #define SUNXI_GPIO_DRV(port, pin) (SUNXI_GPIO_PORT(port) + 0x14 + (0x4 * ((pin) / 16))) 53 #define SUNXI_GPIO_DRV_PINMASK(pin) (0x3 << (((pin) % 16) * 2)) 54 #define SUNXI_GPIO_PULL(port, pin) (SUNXI_GPIO_PORT(port) + 0x1c + (0x4 * ((pin) / 16))) 55 #define SUNXI_GPIO_PULL_DISABLE 0 56 #define SUNXI_GPIO_PULL_UP 1 57 #define SUNXI_GPIO_PULL_DOWN 2 58 #define SUNXI_GPIO_PULL_PINMASK(pin) (0x3 << (((pin) % 16) * 2)) 59 60 static const struct of_compat_data compat_data[] = { 61 #ifdef SOC_SUN6I_A31 62 { "allwinner,sun6i-a31-pinctrl", (uintptr_t)&sun6i_a31_padconf }, 63 { "allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&sun6i_a31_r_padconf }, 64 #endif 65 #ifdef SOC_SUN8I_H3 66 { "allwinner,sun8i-h3-pinctrl", (uintptr_t)&sun8i_h3_padconf }, 67 { "allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&sun8i_h3_r_padconf }, 68 #endif 69 { NULL } 70 }; 71 72 struct sunxi_gpio_softc { 73 device_t sc_dev; 74 bus_space_tag_t sc_bst; 75 bus_space_handle_t sc_bsh; 76 const struct sunxi_gpio_padconf *sc_padconf; 77 kmutex_t sc_lock; 78 79 struct gpio_chipset_tag sc_gp; 80 gpio_pin_t *sc_pins; 81 device_t sc_gpiodev; 82 }; 83 84 struct sunxi_gpio_pin { 85 struct sunxi_gpio_softc *pin_sc; 86 const struct sunxi_gpio_pins *pin_def; 87 int pin_flags; 88 bool pin_actlo; 89 }; 90 91 #define GPIO_READ(sc, reg) \ 92 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 93 #define GPIO_WRITE(sc, reg, val) \ 94 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 95 96 static int sunxi_gpio_match(device_t, cfdata_t, void *); 97 static void sunxi_gpio_attach(device_t, device_t, void *); 98 99 CFATTACH_DECL_NEW(sunxi_gpio, sizeof(struct sunxi_gpio_softc), 100 sunxi_gpio_match, sunxi_gpio_attach, NULL, NULL); 101 102 static const struct sunxi_gpio_pins * 103 sunxi_gpio_lookup(struct sunxi_gpio_softc *sc, uint8_t port, uint8_t pin) 104 { 105 const struct sunxi_gpio_pins *pin_def; 106 u_int n; 107 108 for (n = 0; n < sc->sc_padconf->npins; n++) { 109 pin_def = &sc->sc_padconf->pins[n]; 110 if (pin_def->port == port && pin_def->pin == pin) 111 return pin_def; 112 } 113 114 return NULL; 115 } 116 117 static const struct sunxi_gpio_pins * 118 sunxi_gpio_lookup_byname(struct sunxi_gpio_softc *sc, const char *name) 119 { 120 const struct sunxi_gpio_pins *pin_def; 121 u_int n; 122 123 for (n = 0; n < sc->sc_padconf->npins; n++) { 124 pin_def = &sc->sc_padconf->pins[n]; 125 if (strcmp(pin_def->name, name) == 0) 126 return pin_def; 127 } 128 129 return NULL; 130 } 131 132 static int 133 sunxi_gpio_setfunc(struct sunxi_gpio_softc *sc, 134 const struct sunxi_gpio_pins *pin_def, const char *func) 135 { 136 uint32_t cfg; 137 u_int n; 138 139 KASSERT(mutex_owned(&sc->sc_lock)); 140 141 const bus_size_t cfg_reg = SUNXI_GPIO_CFG(pin_def->port, pin_def->pin); 142 const uint32_t cfg_mask = SUNXI_GPIO_CFG_PINMASK(pin_def->pin); 143 144 for (n = 0; n < SUNXI_GPIO_MAXFUNC; n++) { 145 if (pin_def->functions[n] == NULL) 146 continue; 147 if (strcmp(pin_def->functions[n], func) == 0) { 148 cfg = GPIO_READ(sc, cfg_reg); 149 cfg &= ~cfg_mask; 150 cfg |= __SHIFTIN(n, cfg_mask); 151 #ifdef SUNXI_GPIO_DEBUG 152 device_printf(sc->sc_dev, "P%c%02d cfg %08x -> %08x\n", 153 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, cfg_reg), cfg); 154 #endif 155 GPIO_WRITE(sc, cfg_reg, cfg); 156 return 0; 157 } 158 } 159 160 /* Function not found */ 161 device_printf(sc->sc_dev, "function '%s' not supported on P%c%02d\n", 162 func, pin_def->port + 'A', pin_def->pin); 163 164 return ENXIO; 165 } 166 167 static int 168 sunxi_gpio_setpull(struct sunxi_gpio_softc *sc, 169 const struct sunxi_gpio_pins *pin_def, int flags) 170 { 171 uint32_t pull; 172 173 KASSERT(mutex_owned(&sc->sc_lock)); 174 175 const bus_size_t pull_reg = SUNXI_GPIO_PULL(pin_def->port, pin_def->pin); 176 const uint32_t pull_mask = SUNXI_GPIO_PULL_PINMASK(pin_def->pin); 177 178 pull = GPIO_READ(sc, pull_reg); 179 pull &= ~pull_mask; 180 if (flags & GPIO_PIN_PULLUP) 181 pull |= __SHIFTIN(SUNXI_GPIO_PULL_UP, pull_mask); 182 else if (flags & GPIO_PIN_PULLDOWN) 183 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DOWN, pull_mask); 184 else 185 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DISABLE, pull_mask); 186 #ifdef SUNXI_GPIO_DEBUG 187 device_printf(sc->sc_dev, "P%c%02d pull %08x -> %08x\n", 188 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, pull_reg), pull); 189 #endif 190 GPIO_WRITE(sc, pull_reg, pull); 191 192 return 0; 193 } 194 195 static int 196 sunxi_gpio_setdrv(struct sunxi_gpio_softc *sc, 197 const struct sunxi_gpio_pins *pin_def, int drive_strength) 198 { 199 uint32_t drv; 200 201 KASSERT(mutex_owned(&sc->sc_lock)); 202 203 if (drive_strength < 10 || drive_strength > 40) 204 return EINVAL; 205 206 const bus_size_t drv_reg = SUNXI_GPIO_DRV(pin_def->port, pin_def->pin); 207 const uint32_t drv_mask = SUNXI_GPIO_DRV_PINMASK(pin_def->pin); 208 209 drv = GPIO_READ(sc, drv_reg); 210 drv &= ~drv_mask; 211 drv |= __SHIFTIN((drive_strength / 10) - 1, drv_mask); 212 #ifdef SUNXI_GPIO_DEBUG 213 device_printf(sc->sc_dev, "P%c%02d drv %08x -> %08x\n", 214 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, drv_reg), drv); 215 #endif 216 GPIO_WRITE(sc, drv_reg, drv); 217 218 return 0; 219 } 220 221 static int 222 sunxi_gpio_ctl(struct sunxi_gpio_softc *sc, const struct sunxi_gpio_pins *pin_def, 223 int flags) 224 { 225 KASSERT(mutex_owned(&sc->sc_lock)); 226 227 if (flags & GPIO_PIN_INPUT) 228 return sunxi_gpio_setfunc(sc, pin_def, "gpio_in"); 229 if (flags & GPIO_PIN_OUTPUT) 230 return sunxi_gpio_setfunc(sc, pin_def, "gpio_out"); 231 232 return EINVAL; 233 } 234 235 static void * 236 sunxi_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 237 { 238 struct sunxi_gpio_softc * const sc = device_private(dev); 239 const struct sunxi_gpio_pins *pin_def; 240 struct sunxi_gpio_pin *gpin; 241 const u_int *gpio = data; 242 int error; 243 244 if (len != 16) 245 return NULL; 246 247 const uint8_t port = be32toh(gpio[1]) & 0xff; 248 const uint8_t pin = be32toh(gpio[2]) & 0xff; 249 const bool actlo = be32toh(gpio[3]) & 1; 250 251 pin_def = sunxi_gpio_lookup(sc, port, pin); 252 if (pin_def == NULL) 253 return NULL; 254 255 mutex_enter(&sc->sc_lock); 256 error = sunxi_gpio_ctl(sc, pin_def, flags); 257 mutex_exit(&sc->sc_lock); 258 259 if (error != 0) 260 return NULL; 261 262 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 263 gpin->pin_sc = sc; 264 gpin->pin_def = pin_def; 265 gpin->pin_flags = flags; 266 gpin->pin_actlo = actlo; 267 268 return gpin; 269 } 270 271 static void 272 sunxi_gpio_release(device_t dev, void *priv) 273 { 274 struct sunxi_gpio_pin *pin = priv; 275 276 sunxi_gpio_ctl(pin->pin_sc, pin->pin_def, GPIO_PIN_INPUT); 277 278 kmem_free(pin, sizeof(*pin)); 279 } 280 281 static int 282 sunxi_gpio_read(device_t dev, void *priv, bool raw) 283 { 284 struct sunxi_gpio_softc * const sc = device_private(dev); 285 struct sunxi_gpio_pin *pin = priv; 286 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 287 uint32_t data; 288 int val; 289 290 KASSERT(sc == pin->pin_sc); 291 292 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 293 const uint32_t data_mask = __BIT(pin_def->pin); 294 295 /* No lock required for reads */ 296 data = GPIO_READ(sc, data_reg); 297 val = __SHIFTOUT(data, data_mask); 298 if (!raw && pin->pin_actlo) 299 val = !val; 300 301 #ifdef SUNXI_GPIO_DEBUG 302 device_printf(dev, "P%c%02d rd %08x (%d %d)\n", 303 pin_def->port + 'A', pin_def->pin, data, 304 __SHIFTOUT(val, data_mask), val); 305 #endif 306 307 return val; 308 } 309 310 static void 311 sunxi_gpio_write(device_t dev, void *priv, int val, bool raw) 312 { 313 struct sunxi_gpio_softc * const sc = device_private(dev); 314 struct sunxi_gpio_pin *pin = priv; 315 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 316 uint32_t data; 317 318 KASSERT(sc == pin->pin_sc); 319 320 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 321 const uint32_t data_mask = __BIT(pin_def->pin); 322 323 if (!raw && pin->pin_actlo) 324 val = !val; 325 326 mutex_enter(&sc->sc_lock); 327 data = GPIO_READ(sc, data_reg); 328 data &= ~data_mask; 329 data |= __SHIFTIN(val, data_mask); 330 #ifdef SUNXI_GPIO_DEBUG 331 device_printf(dev, "P%c%02d wr %08x -> %08x\n", 332 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, data_reg), data); 333 #endif 334 GPIO_WRITE(sc, data_reg, data_mask); 335 mutex_exit(&sc->sc_lock); 336 } 337 338 static struct fdtbus_gpio_controller_func sunxi_gpio_funcs = { 339 .acquire = sunxi_gpio_acquire, 340 .release = sunxi_gpio_release, 341 .read = sunxi_gpio_read, 342 .write = sunxi_gpio_write, 343 }; 344 345 static int 346 sunxi_pinctrl_set_config(device_t dev, const void *data, size_t len) 347 { 348 struct sunxi_gpio_softc * const sc = device_private(dev); 349 const struct sunxi_gpio_pins *pin_def; 350 u_int drive_strength; 351 352 if (len != 4) 353 return -1; 354 355 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 356 357 /* 358 * Required: pins, function 359 * Optional: bias-disable, bias-pull-up, bias-pull-down, drive-strength 360 */ 361 362 const char *function = fdtbus_get_string(phandle, "function"); 363 if (function == NULL) 364 return -1; 365 int pins_len = OF_getproplen(phandle, "pins"); 366 if (pins_len <= 0) 367 return -1; 368 const char *pins = fdtbus_get_string(phandle, "pins"); 369 370 mutex_enter(&sc->sc_lock); 371 372 for (pins = fdtbus_get_string(phandle, "pins"); 373 pins_len > 0; 374 pins_len -= strlen(pins) + 1, pins += strlen(pins) + 1) { 375 pin_def = sunxi_gpio_lookup_byname(sc, pins); 376 if (pin_def == NULL) { 377 aprint_error_dev(dev, "unknown pin name '%s'\n", pins); 378 continue; 379 } 380 if (sunxi_gpio_setfunc(sc, pin_def, function) != 0) 381 continue; 382 383 if (of_hasprop(phandle, "bias-disable")) 384 sunxi_gpio_setpull(sc, pin_def, 0); 385 else if (of_hasprop(phandle, "bias-pull-up")) 386 sunxi_gpio_setpull(sc, pin_def, GPIO_PIN_PULLUP); 387 else if (of_hasprop(phandle, "bias-pull-down")) 388 sunxi_gpio_setpull(sc, pin_def, GPIO_PIN_PULLDOWN); 389 390 if (of_getprop_uint32(phandle, "drive-strength", &drive_strength) == 0) 391 sunxi_gpio_setdrv(sc, pin_def, drive_strength); 392 } 393 394 mutex_exit(&sc->sc_lock); 395 396 return 0; 397 } 398 399 static struct fdtbus_pinctrl_controller_func sunxi_pinctrl_funcs = { 400 .set_config = sunxi_pinctrl_set_config, 401 }; 402 403 static int 404 sunxi_gpio_pin_read(void *priv, int pin) 405 { 406 struct sunxi_gpio_softc * const sc = priv; 407 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 408 uint32_t data; 409 int val; 410 411 KASSERT(pin < sc->sc_padconf->npins); 412 413 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 414 const uint32_t data_mask = __BIT(pin_def->pin); 415 416 /* No lock required for reads */ 417 data = GPIO_READ(sc, data_reg); 418 val = __SHIFTOUT(data, data_mask); 419 420 return val; 421 } 422 423 static void 424 sunxi_gpio_pin_write(void *priv, int pin, int val) 425 { 426 struct sunxi_gpio_softc * const sc = priv; 427 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 428 uint32_t data; 429 430 KASSERT(pin < sc->sc_padconf->npins); 431 432 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 433 const uint32_t data_mask = __BIT(pin_def->pin); 434 435 mutex_enter(&sc->sc_lock); 436 data = GPIO_READ(sc, data_reg); 437 if (val) 438 data |= data_mask; 439 else 440 data &= ~data_mask; 441 GPIO_WRITE(sc, data_reg, data); 442 mutex_exit(&sc->sc_lock); 443 } 444 445 static void 446 sunxi_gpio_pin_ctl(void *priv, int pin, int flags) 447 { 448 struct sunxi_gpio_softc * const sc = priv; 449 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 450 451 KASSERT(pin < sc->sc_padconf->npins); 452 453 mutex_enter(&sc->sc_lock); 454 sunxi_gpio_ctl(sc, pin_def, flags); 455 sunxi_gpio_setpull(sc, pin_def, flags); 456 mutex_exit(&sc->sc_lock); 457 } 458 459 static void 460 sunxi_gpio_attach_ports(struct sunxi_gpio_softc *sc) 461 { 462 const struct sunxi_gpio_pins *pin_def; 463 struct gpio_chipset_tag *gp = &sc->sc_gp; 464 struct gpiobus_attach_args gba; 465 u_int pin; 466 467 gp->gp_cookie = sc; 468 gp->gp_pin_read = sunxi_gpio_pin_read; 469 gp->gp_pin_write = sunxi_gpio_pin_write; 470 gp->gp_pin_ctl = sunxi_gpio_pin_ctl; 471 472 const u_int npins = sc->sc_padconf->npins; 473 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * npins, KM_SLEEP); 474 475 for (pin = 0; pin < sc->sc_padconf->npins; pin++) { 476 pin_def = &sc->sc_padconf->pins[pin]; 477 sc->sc_pins[pin].pin_num = pin; 478 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 479 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 480 sc->sc_pins[pin].pin_state = sunxi_gpio_pin_read(sc, pin); 481 strlcpy(sc->sc_pins[pin].pin_defname, pin_def->name, 482 sizeof(sc->sc_pins[pin].pin_defname)); 483 } 484 485 memset(&gba, 0, sizeof(gba)); 486 gba.gba_gc = gp; 487 gba.gba_pins = sc->sc_pins; 488 gba.gba_npins = npins; 489 sc->sc_gpiodev = config_found_ia(sc->sc_dev, "gpiobus", &gba, NULL); 490 } 491 492 static int 493 sunxi_gpio_match(device_t parent, cfdata_t cf, void *aux) 494 { 495 struct fdt_attach_args * const faa = aux; 496 497 return of_match_compat_data(faa->faa_phandle, compat_data); 498 } 499 500 static void 501 sunxi_gpio_attach(device_t parent, device_t self, void *aux) 502 { 503 struct sunxi_gpio_softc * const sc = device_private(self); 504 struct fdt_attach_args * const faa = aux; 505 const int phandle = faa->faa_phandle; 506 bus_addr_t addr; 507 bus_size_t size; 508 int child; 509 510 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 511 aprint_error(": couldn't get registers\n"); 512 return; 513 } 514 515 sc->sc_dev = self; 516 sc->sc_bst = faa->faa_bst; 517 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 518 aprint_error(": couldn't map registers\n"); 519 return; 520 } 521 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 522 sc->sc_padconf = (void *)of_search_compatible(phandle, compat_data)->data; 523 524 aprint_naive("\n"); 525 aprint_normal(": PIO\n"); 526 527 fdtbus_register_gpio_controller(self, phandle, &sunxi_gpio_funcs); 528 529 for (child = OF_child(phandle); child; child = OF_peer(child)) { 530 if (!of_hasprop(child, "function") || !of_hasprop(child, "pins")) 531 continue; 532 fdtbus_register_pinctrl_config(self, child, &sunxi_pinctrl_funcs); 533 } 534 535 fdtbus_pinctrl_configure(); 536 537 sunxi_gpio_attach_ports(sc); 538 } 539
Indexes created Mon Oct 20 20:10:13 GMT 2025