sunxi_gpio.c revision 1.8.4.2
1 /* $NetBSD: sunxi_gpio.c,v 1.8.4.2 2017/07/18 19:13:08 snj Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_gpio.c,v 1.8.4.2 2017/07/18 19:13:08 snj Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/mutex.h> 40 #include <sys/kmem.h> 41 #include <sys/gpio.h> 42 43 #include <dev/fdt/fdtvar.h> 44 #include <dev/gpio/gpiovar.h> 45 46 #include <arm/sunxi/sunxi_gpio.h> 47 48 #define SUNXI_GPIO_PORT(port) (0x24 * (port)) 49 #define SUNXI_GPIO_CFG(port, pin) (SUNXI_GPIO_PORT(port) + 0x00 + (0x4 * ((pin) / 8))) 50 #define SUNXI_GPIO_CFG_PINMASK(pin) (0x7 << (((pin) % 8) * 4)) 51 #define SUNXI_GPIO_DATA(port) (SUNXI_GPIO_PORT(port) + 0x10) 52 #define SUNXI_GPIO_DRV(port, pin) (SUNXI_GPIO_PORT(port) + 0x14 + (0x4 * ((pin) / 16))) 53 #define SUNXI_GPIO_DRV_PINMASK(pin) (0x3 << (((pin) % 16) * 2)) 54 #define SUNXI_GPIO_PULL(port, pin) (SUNXI_GPIO_PORT(port) + 0x1c + (0x4 * ((pin) / 16))) 55 #define SUNXI_GPIO_PULL_DISABLE 0 56 #define SUNXI_GPIO_PULL_UP 1 57 #define SUNXI_GPIO_PULL_DOWN 2 58 #define SUNXI_GPIO_PULL_PINMASK(pin) (0x3 << (((pin) % 16) * 2)) 59 60 static const struct of_compat_data compat_data[] = { 61 #ifdef SOC_SUN6I_A31 62 { "allwinner,sun6i-a31-pinctrl", (uintptr_t)&sun6i_a31_padconf }, 63 { "allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&sun6i_a31_r_padconf }, 64 #endif 65 #ifdef SOC_SUN8I_A83T 66 { "allwinner,sun8i-a83t-pinctrl", (uintptr_t)&sun8i_a83t_padconf }, 67 { "allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&sun8i_a83t_r_padconf }, 68 #endif 69 #ifdef SOC_SUN8I_H3 70 { "allwinner,sun8i-h3-pinctrl", (uintptr_t)&sun8i_h3_padconf }, 71 { "allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&sun8i_h3_r_padconf }, 72 #endif 73 { NULL } 74 }; 75 76 struct sunxi_gpio_softc { 77 device_t sc_dev; 78 bus_space_tag_t sc_bst; 79 bus_space_handle_t sc_bsh; 80 const struct sunxi_gpio_padconf *sc_padconf; 81 kmutex_t sc_lock; 82 83 struct gpio_chipset_tag sc_gp; 84 gpio_pin_t *sc_pins; 85 device_t sc_gpiodev; 86 }; 87 88 struct sunxi_gpio_pin { 89 struct sunxi_gpio_softc *pin_sc; 90 const struct sunxi_gpio_pins *pin_def; 91 int pin_flags; 92 bool pin_actlo; 93 }; 94 95 #define GPIO_READ(sc, reg) \ 96 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 97 #define GPIO_WRITE(sc, reg, val) \ 98 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 99 100 static int sunxi_gpio_match(device_t, cfdata_t, void *); 101 static void sunxi_gpio_attach(device_t, device_t, void *); 102 103 CFATTACH_DECL_NEW(sunxi_gpio, sizeof(struct sunxi_gpio_softc), 104 sunxi_gpio_match, sunxi_gpio_attach, NULL, NULL); 105 106 static const struct sunxi_gpio_pins * 107 sunxi_gpio_lookup(struct sunxi_gpio_softc *sc, uint8_t port, uint8_t pin) 108 { 109 const struct sunxi_gpio_pins *pin_def; 110 u_int n; 111 112 for (n = 0; n < sc->sc_padconf->npins; n++) { 113 pin_def = &sc->sc_padconf->pins[n]; 114 if (pin_def->port == port && pin_def->pin == pin) 115 return pin_def; 116 } 117 118 return NULL; 119 } 120 121 static const struct sunxi_gpio_pins * 122 sunxi_gpio_lookup_byname(struct sunxi_gpio_softc *sc, const char *name) 123 { 124 const struct sunxi_gpio_pins *pin_def; 125 u_int n; 126 127 for (n = 0; n < sc->sc_padconf->npins; n++) { 128 pin_def = &sc->sc_padconf->pins[n]; 129 if (strcmp(pin_def->name, name) == 0) 130 return pin_def; 131 } 132 133 return NULL; 134 } 135 136 static int 137 sunxi_gpio_setfunc(struct sunxi_gpio_softc *sc, 138 const struct sunxi_gpio_pins *pin_def, const char *func) 139 { 140 uint32_t cfg; 141 u_int n; 142 143 KASSERT(mutex_owned(&sc->sc_lock)); 144 145 const bus_size_t cfg_reg = SUNXI_GPIO_CFG(pin_def->port, pin_def->pin); 146 const uint32_t cfg_mask = SUNXI_GPIO_CFG_PINMASK(pin_def->pin); 147 148 for (n = 0; n < SUNXI_GPIO_MAXFUNC; n++) { 149 if (pin_def->functions[n] == NULL) 150 continue; 151 if (strcmp(pin_def->functions[n], func) == 0) { 152 cfg = GPIO_READ(sc, cfg_reg); 153 cfg &= ~cfg_mask; 154 cfg |= __SHIFTIN(n, cfg_mask); 155 #ifdef SUNXI_GPIO_DEBUG 156 device_printf(sc->sc_dev, "P%c%02d cfg %08x -> %08x\n", 157 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, cfg_reg), cfg); 158 #endif 159 GPIO_WRITE(sc, cfg_reg, cfg); 160 return 0; 161 } 162 } 163 164 /* Function not found */ 165 device_printf(sc->sc_dev, "function '%s' not supported on P%c%02d\n", 166 func, pin_def->port + 'A', pin_def->pin); 167 168 return ENXIO; 169 } 170 171 static int 172 sunxi_gpio_setpull(struct sunxi_gpio_softc *sc, 173 const struct sunxi_gpio_pins *pin_def, int flags) 174 { 175 uint32_t pull; 176 177 KASSERT(mutex_owned(&sc->sc_lock)); 178 179 const bus_size_t pull_reg = SUNXI_GPIO_PULL(pin_def->port, pin_def->pin); 180 const uint32_t pull_mask = SUNXI_GPIO_PULL_PINMASK(pin_def->pin); 181 182 pull = GPIO_READ(sc, pull_reg); 183 pull &= ~pull_mask; 184 if (flags & GPIO_PIN_PULLUP) 185 pull |= __SHIFTIN(SUNXI_GPIO_PULL_UP, pull_mask); 186 else if (flags & GPIO_PIN_PULLDOWN) 187 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DOWN, pull_mask); 188 else 189 pull |= __SHIFTIN(SUNXI_GPIO_PULL_DISABLE, pull_mask); 190 #ifdef SUNXI_GPIO_DEBUG 191 device_printf(sc->sc_dev, "P%c%02d pull %08x -> %08x\n", 192 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, pull_reg), pull); 193 #endif 194 GPIO_WRITE(sc, pull_reg, pull); 195 196 return 0; 197 } 198 199 static int 200 sunxi_gpio_setdrv(struct sunxi_gpio_softc *sc, 201 const struct sunxi_gpio_pins *pin_def, int drive_strength) 202 { 203 uint32_t drv; 204 205 KASSERT(mutex_owned(&sc->sc_lock)); 206 207 if (drive_strength < 10 || drive_strength > 40) 208 return EINVAL; 209 210 const bus_size_t drv_reg = SUNXI_GPIO_DRV(pin_def->port, pin_def->pin); 211 const uint32_t drv_mask = SUNXI_GPIO_DRV_PINMASK(pin_def->pin); 212 213 drv = GPIO_READ(sc, drv_reg); 214 drv &= ~drv_mask; 215 drv |= __SHIFTIN((drive_strength / 10) - 1, drv_mask); 216 #ifdef SUNXI_GPIO_DEBUG 217 device_printf(sc->sc_dev, "P%c%02d drv %08x -> %08x\n", 218 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, drv_reg), drv); 219 #endif 220 GPIO_WRITE(sc, drv_reg, drv); 221 222 return 0; 223 } 224 225 static int 226 sunxi_gpio_ctl(struct sunxi_gpio_softc *sc, const struct sunxi_gpio_pins *pin_def, 227 int flags) 228 { 229 KASSERT(mutex_owned(&sc->sc_lock)); 230 231 if (flags & GPIO_PIN_INPUT) 232 return sunxi_gpio_setfunc(sc, pin_def, "gpio_in"); 233 if (flags & GPIO_PIN_OUTPUT) 234 return sunxi_gpio_setfunc(sc, pin_def, "gpio_out"); 235 236 return EINVAL; 237 } 238 239 static void * 240 sunxi_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 241 { 242 struct sunxi_gpio_softc * const sc = device_private(dev); 243 const struct sunxi_gpio_pins *pin_def; 244 struct sunxi_gpio_pin *gpin; 245 const u_int *gpio = data; 246 int error; 247 248 if (len != 16) 249 return NULL; 250 251 const uint8_t port = be32toh(gpio[1]) & 0xff; 252 const uint8_t pin = be32toh(gpio[2]) & 0xff; 253 const bool actlo = be32toh(gpio[3]) & 1; 254 255 pin_def = sunxi_gpio_lookup(sc, port, pin); 256 if (pin_def == NULL) 257 return NULL; 258 259 mutex_enter(&sc->sc_lock); 260 error = sunxi_gpio_ctl(sc, pin_def, flags); 261 mutex_exit(&sc->sc_lock); 262 263 if (error != 0) 264 return NULL; 265 266 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 267 gpin->pin_sc = sc; 268 gpin->pin_def = pin_def; 269 gpin->pin_flags = flags; 270 gpin->pin_actlo = actlo; 271 272 return gpin; 273 } 274 275 static void 276 sunxi_gpio_release(device_t dev, void *priv) 277 { 278 struct sunxi_gpio_pin *pin = priv; 279 280 sunxi_gpio_ctl(pin->pin_sc, pin->pin_def, GPIO_PIN_INPUT); 281 282 kmem_free(pin, sizeof(*pin)); 283 } 284 285 static int 286 sunxi_gpio_read(device_t dev, void *priv, bool raw) 287 { 288 struct sunxi_gpio_softc * const sc = device_private(dev); 289 struct sunxi_gpio_pin *pin = priv; 290 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 291 uint32_t data; 292 int val; 293 294 KASSERT(sc == pin->pin_sc); 295 296 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 297 const uint32_t data_mask = __BIT(pin_def->pin); 298 299 /* No lock required for reads */ 300 data = GPIO_READ(sc, data_reg); 301 val = __SHIFTOUT(data, data_mask); 302 if (!raw && pin->pin_actlo) 303 val = !val; 304 305 #ifdef SUNXI_GPIO_DEBUG 306 device_printf(dev, "P%c%02d rd %08x (%d %d)\n", 307 pin_def->port + 'A', pin_def->pin, data, 308 __SHIFTOUT(val, data_mask), val); 309 #endif 310 311 return val; 312 } 313 314 static void 315 sunxi_gpio_write(device_t dev, void *priv, int val, bool raw) 316 { 317 struct sunxi_gpio_softc * const sc = device_private(dev); 318 struct sunxi_gpio_pin *pin = priv; 319 const struct sunxi_gpio_pins *pin_def = pin->pin_def; 320 uint32_t data; 321 322 KASSERT(sc == pin->pin_sc); 323 324 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 325 const uint32_t data_mask = __BIT(pin_def->pin); 326 327 if (!raw && pin->pin_actlo) 328 val = !val; 329 330 mutex_enter(&sc->sc_lock); 331 data = GPIO_READ(sc, data_reg); 332 data &= ~data_mask; 333 data |= __SHIFTIN(val, data_mask); 334 #ifdef SUNXI_GPIO_DEBUG 335 device_printf(dev, "P%c%02d wr %08x -> %08x\n", 336 pin_def->port + 'A', pin_def->pin, GPIO_READ(sc, data_reg), data); 337 #endif 338 GPIO_WRITE(sc, data_reg, data); 339 mutex_exit(&sc->sc_lock); 340 } 341 342 static struct fdtbus_gpio_controller_func sunxi_gpio_funcs = { 343 .acquire = sunxi_gpio_acquire, 344 .release = sunxi_gpio_release, 345 .read = sunxi_gpio_read, 346 .write = sunxi_gpio_write, 347 }; 348 349 static int 350 sunxi_pinctrl_set_config(device_t dev, const void *data, size_t len) 351 { 352 struct sunxi_gpio_softc * const sc = device_private(dev); 353 const struct sunxi_gpio_pins *pin_def; 354 u_int drive_strength; 355 356 if (len != 4) 357 return -1; 358 359 const int phandle = fdtbus_get_phandle_from_native(be32dec(data)); 360 361 /* 362 * Required: pins, function 363 * Optional: bias-disable, bias-pull-up, bias-pull-down, drive-strength 364 */ 365 366 const char *function = fdtbus_get_string(phandle, "function"); 367 if (function == NULL) 368 return -1; 369 int pins_len = OF_getproplen(phandle, "pins"); 370 if (pins_len <= 0) 371 return -1; 372 const char *pins = fdtbus_get_string(phandle, "pins"); 373 374 mutex_enter(&sc->sc_lock); 375 376 for (pins = fdtbus_get_string(phandle, "pins"); 377 pins_len > 0; 378 pins_len -= strlen(pins) + 1, pins += strlen(pins) + 1) { 379 pin_def = sunxi_gpio_lookup_byname(sc, pins); 380 if (pin_def == NULL) { 381 aprint_error_dev(dev, "unknown pin name '%s'\n", pins); 382 continue; 383 } 384 if (sunxi_gpio_setfunc(sc, pin_def, function) != 0) 385 continue; 386 387 if (of_hasprop(phandle, "bias-disable")) 388 sunxi_gpio_setpull(sc, pin_def, 0); 389 else if (of_hasprop(phandle, "bias-pull-up")) 390 sunxi_gpio_setpull(sc, pin_def, GPIO_PIN_PULLUP); 391 else if (of_hasprop(phandle, "bias-pull-down")) 392 sunxi_gpio_setpull(sc, pin_def, GPIO_PIN_PULLDOWN); 393 394 if (of_getprop_uint32(phandle, "drive-strength", &drive_strength) == 0) 395 sunxi_gpio_setdrv(sc, pin_def, drive_strength); 396 } 397 398 mutex_exit(&sc->sc_lock); 399 400 return 0; 401 } 402 403 static struct fdtbus_pinctrl_controller_func sunxi_pinctrl_funcs = { 404 .set_config = sunxi_pinctrl_set_config, 405 }; 406 407 static int 408 sunxi_gpio_pin_read(void *priv, int pin) 409 { 410 struct sunxi_gpio_softc * const sc = priv; 411 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 412 uint32_t data; 413 int val; 414 415 KASSERT(pin < sc->sc_padconf->npins); 416 417 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 418 const uint32_t data_mask = __BIT(pin_def->pin); 419 420 /* No lock required for reads */ 421 data = GPIO_READ(sc, data_reg); 422 val = __SHIFTOUT(data, data_mask); 423 424 return val; 425 } 426 427 static void 428 sunxi_gpio_pin_write(void *priv, int pin, int val) 429 { 430 struct sunxi_gpio_softc * const sc = priv; 431 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 432 uint32_t data; 433 434 KASSERT(pin < sc->sc_padconf->npins); 435 436 const bus_size_t data_reg = SUNXI_GPIO_DATA(pin_def->port); 437 const uint32_t data_mask = __BIT(pin_def->pin); 438 439 mutex_enter(&sc->sc_lock); 440 data = GPIO_READ(sc, data_reg); 441 if (val) 442 data |= data_mask; 443 else 444 data &= ~data_mask; 445 GPIO_WRITE(sc, data_reg, data); 446 mutex_exit(&sc->sc_lock); 447 } 448 449 static void 450 sunxi_gpio_pin_ctl(void *priv, int pin, int flags) 451 { 452 struct sunxi_gpio_softc * const sc = priv; 453 const struct sunxi_gpio_pins *pin_def = &sc->sc_padconf->pins[pin]; 454 455 KASSERT(pin < sc->sc_padconf->npins); 456 457 mutex_enter(&sc->sc_lock); 458 sunxi_gpio_ctl(sc, pin_def, flags); 459 sunxi_gpio_setpull(sc, pin_def, flags); 460 mutex_exit(&sc->sc_lock); 461 } 462 463 static void 464 sunxi_gpio_attach_ports(struct sunxi_gpio_softc *sc) 465 { 466 const struct sunxi_gpio_pins *pin_def; 467 struct gpio_chipset_tag *gp = &sc->sc_gp; 468 struct gpiobus_attach_args gba; 469 u_int pin; 470 471 gp->gp_cookie = sc; 472 gp->gp_pin_read = sunxi_gpio_pin_read; 473 gp->gp_pin_write = sunxi_gpio_pin_write; 474 gp->gp_pin_ctl = sunxi_gpio_pin_ctl; 475 476 const u_int npins = sc->sc_padconf->npins; 477 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * npins, KM_SLEEP); 478 479 for (pin = 0; pin < sc->sc_padconf->npins; pin++) { 480 pin_def = &sc->sc_padconf->pins[pin]; 481 sc->sc_pins[pin].pin_num = pin; 482 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | 483 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN; 484 sc->sc_pins[pin].pin_state = sunxi_gpio_pin_read(sc, pin); 485 strlcpy(sc->sc_pins[pin].pin_defname, pin_def->name, 486 sizeof(sc->sc_pins[pin].pin_defname)); 487 } 488 489 memset(&gba, 0, sizeof(gba)); 490 gba.gba_gc = gp; 491 gba.gba_pins = sc->sc_pins; 492 gba.gba_npins = npins; 493 sc->sc_gpiodev = config_found_ia(sc->sc_dev, "gpiobus", &gba, NULL); 494 } 495 496 static int 497 sunxi_gpio_match(device_t parent, cfdata_t cf, void *aux) 498 { 499 struct fdt_attach_args * const faa = aux; 500 501 return of_match_compat_data(faa->faa_phandle, compat_data); 502 } 503 504 static void 505 sunxi_gpio_attach(device_t parent, device_t self, void *aux) 506 { 507 struct sunxi_gpio_softc * const sc = device_private(self); 508 struct fdt_attach_args * const faa = aux; 509 const int phandle = faa->faa_phandle; 510 struct fdtbus_reset *rst; 511 struct clk *clk; 512 bus_addr_t addr; 513 bus_size_t size; 514 int child; 515 516 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 517 aprint_error(": couldn't get registers\n"); 518 return; 519 } 520 521 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) 522 if (clk_enable(clk) != 0) { 523 aprint_error(": couldn't enable clock\n"); 524 return; 525 } 526 527 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 528 if (fdtbus_reset_deassert(rst) != 0) { 529 aprint_error(": couldn't de-assert reset\n"); 530 return; 531 } 532 533 sc->sc_dev = self; 534 sc->sc_bst = faa->faa_bst; 535 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 536 aprint_error(": couldn't map registers\n"); 537 return; 538 } 539 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 540 sc->sc_padconf = (void *)of_search_compatible(phandle, compat_data)->data; 541 542 aprint_naive("\n"); 543 aprint_normal(": PIO\n"); 544 545 fdtbus_register_gpio_controller(self, phandle, &sunxi_gpio_funcs); 546 547 for (child = OF_child(phandle); child; child = OF_peer(child)) { 548 if (!of_hasprop(child, "function") || !of_hasprop(child, "pins")) 549 continue; 550 fdtbus_register_pinctrl_config(self, child, &sunxi_pinctrl_funcs); 551 } 552 553 fdtbus_pinctrl_configure(); 554 555 sunxi_gpio_attach_ports(sc); 556 } 557
Indexes created Wed Oct 15 16:09:53 GMT 2025