sunxi_i2s.c revision 1.2.4.2
1 /* $NetBSD: sunxi_i2s.c,v 1.2.4.2 2020/04/08 14:07:31 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_i2s.c,v 1.2.4.2 2020/04/08 14:07:31 martin Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/device.h> 36 #include <sys/kmem.h> 37 #include <sys/gpio.h> 38 39 #include <sys/audioio.h> 40 #include <dev/audio/audio_if.h> 41 #include <dev/audio/linear.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define SUNXI_I2S_CLK_RATE 24576000 46 47 #define DA_CTL 0x00 48 #define DA_CTL_SDO_EN __BIT(8) 49 #define DA_CTL_MS __BIT(5) 50 #define DA_CTL_PCM __BIT(4) 51 #define DA_CTL_TXEN __BIT(2) 52 #define DA_CTL_RXEN __BIT(1) 53 #define DA_CTL_GEN __BIT(0) 54 #define DA_FAT0 0x04 55 #define DA_FAT0_LRCP __BIT(7) 56 #define DA_LRCP_NORMAL 0 57 #define DA_LRCP_INVERTED 1 58 #define DA_FAT0_BCP __BIT(6) 59 #define DA_BCP_NORMAL 0 60 #define DA_BCP_INVERTED 1 61 #define DA_FAT0_SR __BITS(5,4) 62 #define DA_FAT0_WSS __BITS(3,2) 63 #define DA_FAT0_FMT __BITS(1,0) 64 #define DA_FMT_I2S 0 65 #define DA_FMT_LJ 1 66 #define DA_FMT_RJ 2 67 #define DA_FAT1 0x08 68 #define DA_ISTA 0x0c 69 #define DA_RXFIFO 0x10 70 #define DA_FCTL 0x14 71 #define DA_FCTL_HUB_EN __BIT(31) 72 #define DA_FCTL_FTX __BIT(25) 73 #define DA_FCTL_FRX __BIT(24) 74 #define DA_FCTL_TXIM __BIT(2) 75 #define DA_FCTL_RXIM __BITS(1,0) 76 #define DA_FSTA 0x18 77 #define DA_INT 0x1c 78 #define DA_INT_TX_DRQ __BIT(7) 79 #define DA_INT_RX_DRQ __BIT(3) 80 #define DA_TXFIFO 0x20 81 #define DA_CLKD 0x24 82 #define DA_CLKD_MCLKO_EN __BIT(7) 83 #define DA_CLKD_BCLKDIV __BITS(6,4) 84 #define DA_CLKD_BCLKDIV_8 3 85 #define DA_CLKD_BCLKDIV_16 5 86 #define DA_CLKD_MCLKDIV __BITS(3,0) 87 #define DA_CLKD_MCLKDIV_1 0 88 #define DA_TXCNT 0x28 89 #define DA_RXCNT 0x2c 90 91 #define DA_CHSEL_EN __BITS(11,4) 92 #define DA_CHSEL_SEL __BITS(2,0) 93 94 struct sunxi_i2s_config { 95 const char *name; 96 bus_size_t txchsel; 97 bus_size_t txchmap; 98 bus_size_t rxchsel; 99 bus_size_t rxchmap; 100 }; 101 102 static const struct sunxi_i2s_config sun50i_a64_codec_config = { 103 .name = "Audio Codec (digital part)", 104 .txchsel = 0x30, 105 .txchmap = 0x34, 106 .rxchsel = 0x38, 107 .rxchmap = 0x3c, 108 }; 109 110 static const struct of_compat_data compat_data[] = { 111 { "allwinner,sun50i-a64-codec-i2s", 112 (uintptr_t)&sun50i_a64_codec_config }, 113 114 { NULL } 115 }; 116 117 struct sunxi_i2s_softc; 118 119 struct sunxi_i2s_chan { 120 struct sunxi_i2s_softc *ch_sc; 121 u_int ch_mode; 122 123 struct fdtbus_dma *ch_dma; 124 struct fdtbus_dma_req ch_req; 125 126 audio_params_t ch_params; 127 128 bus_addr_t ch_start_phys; 129 bus_addr_t ch_end_phys; 130 bus_addr_t ch_cur_phys; 131 int ch_blksize; 132 133 void (*ch_intr)(void *); 134 void *ch_intrarg; 135 }; 136 137 struct sunxi_i2s_dma { 138 LIST_ENTRY(sunxi_i2s_dma) dma_list; 139 bus_dmamap_t dma_map; 140 void *dma_addr; 141 size_t dma_size; 142 bus_dma_segment_t dma_segs[1]; 143 int dma_nsegs; 144 }; 145 146 struct sunxi_i2s_softc { 147 device_t sc_dev; 148 bus_space_tag_t sc_bst; 149 bus_space_handle_t sc_bsh; 150 bus_dma_tag_t sc_dmat; 151 int sc_phandle; 152 bus_addr_t sc_baseaddr; 153 154 struct sunxi_i2s_config *sc_cfg; 155 156 LIST_HEAD(, sunxi_i2s_dma) sc_dmalist; 157 158 kmutex_t sc_lock; 159 kmutex_t sc_intr_lock; 160 161 struct audio_format sc_format; 162 163 struct sunxi_i2s_chan sc_pchan; 164 struct sunxi_i2s_chan sc_rchan; 165 166 struct audio_dai_device sc_dai; 167 }; 168 169 #define I2S_READ(sc, reg) \ 170 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 171 #define I2S_WRITE(sc, reg, val) \ 172 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 173 174 static int 175 sunxi_i2s_allocdma(struct sunxi_i2s_softc *sc, size_t size, 176 size_t align, struct sunxi_i2s_dma *dma) 177 { 178 int error; 179 180 dma->dma_size = size; 181 error = bus_dmamem_alloc(sc->sc_dmat, dma->dma_size, align, 0, 182 dma->dma_segs, 1, &dma->dma_nsegs, BUS_DMA_WAITOK); 183 if (error) 184 return error; 185 186 error = bus_dmamem_map(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs, 187 dma->dma_size, &dma->dma_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 188 if (error) 189 goto free; 190 191 error = bus_dmamap_create(sc->sc_dmat, dma->dma_size, dma->dma_nsegs, 192 dma->dma_size, 0, BUS_DMA_WAITOK, &dma->dma_map); 193 if (error) 194 goto unmap; 195 196 error = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_addr, 197 dma->dma_size, NULL, BUS_DMA_WAITOK); 198 if (error) 199 goto destroy; 200 201 return 0; 202 203 destroy: 204 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 205 unmap: 206 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 207 free: 208 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 209 210 return error; 211 } 212 213 static void 214 sunxi_i2s_freedma(struct sunxi_i2s_softc *sc, struct sunxi_i2s_dma *dma) 215 { 216 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 217 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 218 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 219 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 220 } 221 222 static int 223 sunxi_i2s_transfer(struct sunxi_i2s_chan *ch) 224 { 225 bus_dma_segment_t seg; 226 227 seg.ds_addr = ch->ch_cur_phys; 228 seg.ds_len = ch->ch_blksize; 229 ch->ch_req.dreq_segs = &seg; 230 ch->ch_req.dreq_nsegs = 1; 231 232 return fdtbus_dma_transfer(ch->ch_dma, &ch->ch_req); 233 } 234 235 static int 236 sunxi_i2s_query_format(void *priv, audio_format_query_t *afp) 237 { 238 struct sunxi_i2s_softc * const sc = priv; 239 240 return audio_query_format(&sc->sc_format, 1, afp); 241 } 242 243 static int 244 sunxi_i2s_set_format(void *priv, int setmode, 245 const audio_params_t *play, const audio_params_t *rec, 246 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 247 { 248 249 if ((setmode & AUMODE_PLAY)) { 250 pfil->codec = audio_internal_to_linear32; 251 } 252 if ((setmode & AUMODE_RECORD)) { 253 rfil->codec = audio_linear32_to_internal; 254 } 255 256 return 0; 257 } 258 259 static void * 260 sunxi_i2s_allocm(void *priv, int dir, size_t size) 261 { 262 struct sunxi_i2s_softc * const sc = priv; 263 struct sunxi_i2s_dma *dma; 264 int error; 265 266 dma = kmem_alloc(sizeof(*dma), KM_SLEEP); 267 268 error = sunxi_i2s_allocdma(sc, size, 16, dma); 269 if (error) { 270 kmem_free(dma, sizeof(*dma)); 271 device_printf(sc->sc_dev, "couldn't allocate DMA memory (%d)\n", 272 error); 273 return NULL; 274 } 275 276 LIST_INSERT_HEAD(&sc->sc_dmalist, dma, dma_list); 277 278 return dma->dma_addr; 279 } 280 281 static void 282 sunxi_i2s_freem(void *priv, void *addr, size_t size) 283 { 284 struct sunxi_i2s_softc * const sc = priv; 285 struct sunxi_i2s_dma *dma; 286 287 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 288 if (dma->dma_addr == addr) { 289 sunxi_i2s_freedma(sc, dma); 290 LIST_REMOVE(dma, dma_list); 291 kmem_free(dma, sizeof(*dma)); 292 break; 293 } 294 } 295 296 static int 297 sunxi_i2s_get_props(void *priv) 298 { 299 300 return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE | 301 AUDIO_PROP_FULLDUPLEX | AUDIO_PROP_INDEPENDENT; 302 } 303 304 static int 305 sunxi_i2s_trigger_output(void *priv, void *start, void *end, int blksize, 306 void (*intr)(void *), void *intrarg, const audio_params_t *params) 307 { 308 struct sunxi_i2s_softc * const sc = priv; 309 struct sunxi_i2s_chan *ch = &sc->sc_pchan; 310 struct sunxi_i2s_dma *dma; 311 bus_addr_t pstart; 312 bus_size_t psize; 313 uint32_t val; 314 int error; 315 316 pstart = 0; 317 psize = (uintptr_t)end - (uintptr_t)start; 318 319 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 320 if (dma->dma_addr == start) { 321 pstart = dma->dma_map->dm_segs[0].ds_addr; 322 break; 323 } 324 if (pstart == 0) { 325 device_printf(sc->sc_dev, "bad addr %p\n", start); 326 return EINVAL; 327 } 328 329 ch->ch_intr = intr; 330 ch->ch_intrarg = intrarg; 331 ch->ch_start_phys = ch->ch_cur_phys = pstart; 332 ch->ch_end_phys = pstart + psize; 333 ch->ch_blksize = blksize; 334 335 /* Flush FIFO */ 336 val = I2S_READ(sc, DA_FCTL); 337 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FTX); 338 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FTX); 339 340 /* Reset TX sample counter */ 341 I2S_WRITE(sc, DA_TXCNT, 0); 342 343 /* Enable transmitter block */ 344 val = I2S_READ(sc, DA_CTL); 345 I2S_WRITE(sc, DA_CTL, val | DA_CTL_TXEN); 346 347 /* Enable TX DRQ */ 348 val = I2S_READ(sc, DA_INT); 349 I2S_WRITE(sc, DA_INT, val | DA_INT_TX_DRQ); 350 351 /* Start DMA transfer */ 352 error = sunxi_i2s_transfer(ch); 353 if (error != 0) { 354 aprint_error_dev(sc->sc_dev, 355 "failed to start DMA transfer: %d\n", error); 356 return error; 357 } 358 359 return 0; 360 } 361 362 static int 363 sunxi_i2s_trigger_input(void *priv, void *start, void *end, int blksize, 364 void (*intr)(void *), void *intrarg, const audio_params_t *params) 365 { 366 struct sunxi_i2s_softc * const sc = priv; 367 struct sunxi_i2s_chan *ch = &sc->sc_rchan; 368 struct sunxi_i2s_dma *dma; 369 bus_addr_t pstart; 370 bus_size_t psize; 371 uint32_t val; 372 int error; 373 374 pstart = 0; 375 psize = (uintptr_t)end - (uintptr_t)start; 376 377 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 378 if (dma->dma_addr == start) { 379 pstart = dma->dma_map->dm_segs[0].ds_addr; 380 break; 381 } 382 if (pstart == 0) { 383 device_printf(sc->sc_dev, "bad addr %p\n", start); 384 return EINVAL; 385 } 386 387 ch->ch_intr = intr; 388 ch->ch_intrarg = intrarg; 389 ch->ch_start_phys = ch->ch_cur_phys = pstart; 390 ch->ch_end_phys = pstart + psize; 391 ch->ch_blksize = blksize; 392 393 /* Flush FIFO */ 394 val = I2S_READ(sc, DA_FCTL); 395 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FRX); 396 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FRX); 397 398 /* Reset RX sample counter */ 399 I2S_WRITE(sc, DA_RXCNT, 0); 400 401 /* Enable receiver block */ 402 val = I2S_READ(sc, DA_CTL); 403 I2S_WRITE(sc, DA_CTL, val | DA_CTL_RXEN); 404 405 /* Enable RX DRQ */ 406 val = I2S_READ(sc, DA_INT); 407 I2S_WRITE(sc, DA_INT, val | DA_INT_RX_DRQ); 408 409 /* Start DMA transfer */ 410 error = sunxi_i2s_transfer(ch); 411 if (error != 0) { 412 aprint_error_dev(sc->sc_dev, 413 "failed to start DMA transfer: %d\n", error); 414 return error; 415 } 416 417 return 0; 418 } 419 420 static int 421 sunxi_i2s_halt_output(void *priv) 422 { 423 struct sunxi_i2s_softc * const sc = priv; 424 struct sunxi_i2s_chan *ch = &sc->sc_pchan; 425 uint32_t val; 426 427 /* Disable DMA channel */ 428 fdtbus_dma_halt(ch->ch_dma); 429 430 /* Disable transmitter block */ 431 val = I2S_READ(sc, DA_CTL); 432 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_TXEN); 433 434 /* Disable TX DRQ */ 435 val = I2S_READ(sc, DA_INT); 436 I2S_WRITE(sc, DA_INT, val & ~DA_INT_TX_DRQ); 437 438 ch->ch_intr = NULL; 439 ch->ch_intrarg = NULL; 440 441 return 0; 442 } 443 444 static int 445 sunxi_i2s_halt_input(void *priv) 446 { 447 struct sunxi_i2s_softc * const sc = priv; 448 struct sunxi_i2s_chan *ch = &sc->sc_rchan; 449 uint32_t val; 450 451 /* Disable DMA channel */ 452 fdtbus_dma_halt(ch->ch_dma); 453 454 /* Disable receiver block */ 455 val = I2S_READ(sc, DA_CTL); 456 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_RXEN); 457 458 /* Disable RX DRQ */ 459 val = I2S_READ(sc, DA_INT); 460 I2S_WRITE(sc, DA_INT, val & ~DA_INT_RX_DRQ); 461 462 return 0; 463 } 464 465 static void 466 sunxi_i2s_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread) 467 { 468 struct sunxi_i2s_softc * const sc = priv; 469 470 *intr = &sc->sc_intr_lock; 471 *thread = &sc->sc_lock; 472 } 473 474 static const struct audio_hw_if sunxi_i2s_hw_if = { 475 .query_format = sunxi_i2s_query_format, 476 .set_format = sunxi_i2s_set_format, 477 .allocm = sunxi_i2s_allocm, 478 .freem = sunxi_i2s_freem, 479 .get_props = sunxi_i2s_get_props, 480 .trigger_output = sunxi_i2s_trigger_output, 481 .trigger_input = sunxi_i2s_trigger_input, 482 .halt_output = sunxi_i2s_halt_output, 483 .halt_input = sunxi_i2s_halt_input, 484 .get_locks = sunxi_i2s_get_locks, 485 }; 486 487 static void 488 sunxi_i2s_dmaintr(void *priv) 489 { 490 struct sunxi_i2s_chan * const ch = priv; 491 struct sunxi_i2s_softc * const sc = ch->ch_sc; 492 493 mutex_enter(&sc->sc_intr_lock); 494 ch->ch_cur_phys += ch->ch_blksize; 495 if (ch->ch_cur_phys >= ch->ch_end_phys) 496 ch->ch_cur_phys = ch->ch_start_phys; 497 498 if (ch->ch_intr) { 499 ch->ch_intr(ch->ch_intrarg); 500 sunxi_i2s_transfer(ch); 501 } 502 mutex_exit(&sc->sc_intr_lock); 503 } 504 505 static int 506 sunxi_i2s_chan_init(struct sunxi_i2s_softc *sc, 507 struct sunxi_i2s_chan *ch, u_int mode, const char *dmaname) 508 { 509 ch->ch_sc = sc; 510 ch->ch_mode = mode; 511 ch->ch_dma = fdtbus_dma_get(sc->sc_phandle, dmaname, sunxi_i2s_dmaintr, ch); 512 if (ch->ch_dma == NULL) { 513 aprint_error(": couldn't get dma channel \"%s\"\n", dmaname); 514 return ENXIO; 515 } 516 517 if (mode == AUMODE_PLAY) { 518 ch->ch_req.dreq_dir = FDT_DMA_WRITE; 519 ch->ch_req.dreq_dev_phys = 520 sc->sc_baseaddr + DA_TXFIFO; 521 } else { 522 ch->ch_req.dreq_dir = FDT_DMA_READ; 523 ch->ch_req.dreq_dev_phys = 524 sc->sc_baseaddr + DA_RXFIFO; 525 } 526 ch->ch_req.dreq_mem_opt.opt_bus_width = 32; 527 ch->ch_req.dreq_mem_opt.opt_burst_len = 8; 528 ch->ch_req.dreq_dev_opt.opt_bus_width = 32; 529 ch->ch_req.dreq_dev_opt.opt_burst_len = 8; 530 531 return 0; 532 } 533 534 static int 535 sunxi_i2s_dai_set_sysclk(audio_dai_tag_t dai, u_int rate, int dir) 536 { 537 struct sunxi_i2s_softc * const sc = audio_dai_private(dai); 538 uint32_t val; 539 540 /* XXX */ 541 542 val = DA_CLKD_MCLKO_EN; 543 val |= __SHIFTIN(DA_CLKD_BCLKDIV_8, DA_CLKD_BCLKDIV); 544 val |= __SHIFTIN(DA_CLKD_MCLKDIV_1, DA_CLKD_MCLKDIV); 545 546 I2S_WRITE(sc, DA_CLKD, val); 547 548 return 0; 549 } 550 551 static int 552 sunxi_i2s_dai_set_format(audio_dai_tag_t dai, u_int format) 553 { 554 struct sunxi_i2s_softc * const sc = audio_dai_private(dai); 555 uint32_t ctl, fat0; 556 557 const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK); 558 const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK); 559 const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK); 560 561 ctl = I2S_READ(sc, DA_CTL); 562 fat0 = I2S_READ(sc, DA_FAT0); 563 564 fat0 &= ~DA_FAT0_FMT; 565 switch (fmt) { 566 case AUDIO_DAI_FORMAT_I2S: 567 fat0 |= __SHIFTIN(DA_FMT_I2S, DA_FAT0_FMT); 568 break; 569 case AUDIO_DAI_FORMAT_RJ: 570 fat0 |= __SHIFTIN(DA_FMT_RJ, DA_FAT0_FMT); 571 break; 572 case AUDIO_DAI_FORMAT_LJ: 573 fat0 |= __SHIFTIN(DA_FMT_LJ, DA_FAT0_FMT); 574 break; 575 default: 576 return EINVAL; 577 } 578 579 fat0 &= ~(DA_FAT0_LRCP|DA_FAT0_BCP); 580 if (AUDIO_DAI_POLARITY_B(pol)) 581 fat0 |= __SHIFTIN(DA_BCP_INVERTED, DA_FAT0_BCP); 582 if (AUDIO_DAI_POLARITY_F(pol)) 583 fat0 |= __SHIFTIN(DA_LRCP_INVERTED, DA_FAT0_LRCP); 584 585 switch (clk) { 586 case AUDIO_DAI_CLOCK_CBM_CFM: 587 ctl |= DA_CTL_MS; /* codec is master */ 588 break; 589 case AUDIO_DAI_CLOCK_CBS_CFS: 590 ctl &= ~DA_CTL_MS; /* codec is slave */ 591 break; 592 default: 593 return EINVAL; 594 } 595 596 ctl &= ~DA_CTL_PCM; 597 598 I2S_WRITE(sc, DA_CTL, ctl); 599 I2S_WRITE(sc, DA_FAT0, fat0); 600 601 return 0; 602 } 603 604 static audio_dai_tag_t 605 sunxi_i2s_dai_get_tag(device_t dev, const void *data, size_t len) 606 { 607 struct sunxi_i2s_softc * const sc = device_private(dev); 608 609 if (len != 4) 610 return NULL; 611 612 return &sc->sc_dai; 613 } 614 615 static struct fdtbus_dai_controller_func sunxi_i2s_dai_funcs = { 616 .get_tag = sunxi_i2s_dai_get_tag 617 }; 618 619 static int 620 sunxi_i2s_clock_init(int phandle) 621 { 622 struct fdtbus_reset *rst; 623 struct clk *clk; 624 int error; 625 626 /* Set module clock to 24.576MHz, suitable for 48 kHz sampling rates */ 627 clk = fdtbus_clock_get(phandle, "mod"); 628 if (clk == NULL) { 629 aprint_error(": couldn't find mod clock\n"); 630 return ENXIO; 631 } 632 error = clk_set_rate(clk, SUNXI_I2S_CLK_RATE); 633 if (error != 0) { 634 aprint_error(": couldn't set mod clock rate: %d\n", error); 635 return error; 636 } 637 error = clk_enable(clk); 638 if (error != 0) { 639 aprint_error(": couldn't enable mod clock: %d\n", error); 640 return error; 641 } 642 643 /* Enable APB clock */ 644 clk = fdtbus_clock_get(phandle, "apb"); 645 if (clk == NULL) { 646 aprint_error(": couldn't find apb clock\n"); 647 return ENXIO; 648 } 649 error = clk_enable(clk); 650 if (error != 0) { 651 aprint_error(": couldn't enable apb clock: %d\n", error); 652 return error; 653 } 654 655 /* De-assert reset */ 656 rst = fdtbus_reset_get(phandle, "rst"); 657 if (rst == NULL) { 658 aprint_error(": couldn't find reset\n"); 659 return ENXIO; 660 } 661 error = fdtbus_reset_deassert(rst); 662 if (error != 0) { 663 aprint_error(": couldn't de-assert reset: %d\n", error); 664 return error; 665 } 666 667 return 0; 668 } 669 670 static int 671 sunxi_i2s_match(device_t parent, cfdata_t cf, void *aux) 672 { 673 struct fdt_attach_args * const faa = aux; 674 675 return of_match_compat_data(faa->faa_phandle, compat_data); 676 } 677 678 static void 679 sunxi_i2s_attach(device_t parent, device_t self, void *aux) 680 { 681 struct sunxi_i2s_softc * const sc = device_private(self); 682 struct fdt_attach_args * const faa = aux; 683 const int phandle = faa->faa_phandle; 684 bus_addr_t addr; 685 bus_size_t size; 686 uint32_t val; 687 688 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 689 aprint_error(": couldn't get registers\n"); 690 return; 691 } 692 693 if (sunxi_i2s_clock_init(phandle) != 0) 694 return; 695 696 sc->sc_dev = self; 697 sc->sc_phandle = phandle; 698 sc->sc_baseaddr = addr; 699 sc->sc_bst = faa->faa_bst; 700 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 701 aprint_error(": couldn't map registers\n"); 702 return; 703 } 704 sc->sc_dmat = faa->faa_dmat; 705 LIST_INIT(&sc->sc_dmalist); 706 sc->sc_cfg = (void *)of_search_compatible(phandle, compat_data)->data; 707 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 708 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 709 710 if (sunxi_i2s_chan_init(sc, &sc->sc_pchan, AUMODE_PLAY, "tx") != 0 || 711 sunxi_i2s_chan_init(sc, &sc->sc_rchan, AUMODE_RECORD, "rx") != 0) { 712 aprint_error(": couldn't setup channels\n"); 713 return; 714 } 715 716 aprint_naive("\n"); 717 aprint_normal(": %s\n", sc->sc_cfg->name); 718 719 /* Reset */ 720 val = I2S_READ(sc, DA_CTL); 721 val &= ~(DA_CTL_TXEN|DA_CTL_RXEN|DA_CTL_GEN); 722 I2S_WRITE(sc, DA_CTL, val); 723 724 val = I2S_READ(sc, DA_FCTL); 725 val &= ~(DA_FCTL_FTX|DA_FCTL_FRX); 726 I2S_WRITE(sc, DA_FCTL, val); 727 728 I2S_WRITE(sc, DA_TXCNT, 0); 729 I2S_WRITE(sc, DA_RXCNT, 0); 730 731 /* Enable */ 732 I2S_WRITE(sc, DA_CTL, DA_CTL_GEN | DA_CTL_SDO_EN); 733 734 /* Setup channels */ 735 I2S_WRITE(sc, sc->sc_cfg->txchmap, 0x76543210); 736 I2S_WRITE(sc, sc->sc_cfg->txchsel, __SHIFTIN(1, DA_CHSEL_SEL) | 737 __SHIFTIN(3, DA_CHSEL_EN)); 738 I2S_WRITE(sc, sc->sc_cfg->rxchmap, 0x76543210); 739 I2S_WRITE(sc, sc->sc_cfg->rxchsel, __SHIFTIN(1, DA_CHSEL_SEL) | 740 __SHIFTIN(3, DA_CHSEL_EN)); 741 742 sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD; 743 sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE; 744 sc->sc_format.validbits = 32; 745 sc->sc_format.precision = 32; 746 sc->sc_format.channels = 2; 747 sc->sc_format.channel_mask = AUFMT_STEREO; 748 sc->sc_format.frequency_type = 1; 749 sc->sc_format.frequency[0] = 48000; 750 751 sc->sc_dai.dai_set_sysclk = sunxi_i2s_dai_set_sysclk; 752 sc->sc_dai.dai_set_format = sunxi_i2s_dai_set_format; 753 sc->sc_dai.dai_hw_if = &sunxi_i2s_hw_if; 754 sc->sc_dai.dai_dev = self; 755 sc->sc_dai.dai_priv = sc; 756 fdtbus_register_dai_controller(self, phandle, &sunxi_i2s_dai_funcs); 757 } 758 759 CFATTACH_DECL_NEW(sunxi_i2s, sizeof(struct sunxi_i2s_softc), 760 sunxi_i2s_match, sunxi_i2s_attach, NULL, NULL); 761
Indexes created Sun Oct 12 09:09:55 GMT 2025