sunxi_i2s.c revision 1.6.2.1
1 /* $NetBSD: sunxi_i2s.c,v 1.6.2.1 2019/11/18 19:31:00 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_i2s.c,v 1.6.2.1 2019/11/18 19:31:00 martin Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/device.h> 36 #include <sys/kmem.h> 37 #include <sys/gpio.h> 38 39 #include <sys/audioio.h> 40 #include <dev/audio/audio_if.h> 41 #include <dev/audio/linear.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define SUNXI_I2S_CLK_RATE 24576000 46 #define SUNXI_I2S_SAMPLE_RATE 48000 47 48 #define DA_CTL 0x00 49 #define DA_CTL_BCLK_OUT __BIT(18) /* sun8i */ 50 #define DA_CLK_LRCK_OUT __BIT(17) /* sun8i */ 51 #define DA_CTL_SDO_EN __BIT(8) 52 #define DA_CTL_MS __BIT(5) /* sun4i */ 53 #define DA_CTL_PCM __BIT(4) /* sun4i */ 54 #define DA_CTL_MODE_SEL __BITS(5,4) /* sun8i */ 55 #define DA_CTL_MODE_SEL_PCM 0 56 #define DA_CTL_MODE_SEL_LJ 1 57 #define DA_CTL_MODE_SEL_RJ 2 58 #define DA_CTL_TXEN __BIT(2) 59 #define DA_CTL_RXEN __BIT(1) 60 #define DA_CTL_GEN __BIT(0) 61 #define DA_FAT0 0x04 62 #define DA_FAT0_LRCK_PERIOD __BITS(17,8) /* sun8i */ 63 #define DA_FAT0_LRCP __BIT(7) 64 #define DA_LRCP_NORMAL 0 65 #define DA_LRCP_INVERTED 1 66 #define DA_FAT0_BCP __BIT(6) 67 #define DA_BCP_NORMAL 0 68 #define DA_BCP_INVERTED 1 69 #define DA_FAT0_SR __BITS(5,4) 70 #define DA_FAT0_WSS __BITS(3,2) 71 #define DA_FAT0_FMT __BITS(1,0) 72 #define DA_FMT_I2S 0 73 #define DA_FMT_LJ 1 74 #define DA_FMT_RJ 2 75 #define DA_FAT1 0x08 76 #define DA_ISTA 0x0c 77 #define DA_RXFIFO 0x10 78 #define DA_FCTL 0x14 79 #define DA_FCTL_HUB_EN __BIT(31) 80 #define DA_FCTL_FTX __BIT(25) 81 #define DA_FCTL_FRX __BIT(24) 82 #define DA_FCTL_TXIM __BIT(2) 83 #define DA_FCTL_RXIM __BITS(1,0) 84 #define DA_FSTA 0x18 85 #define DA_INT 0x1c 86 #define DA_INT_TX_DRQ __BIT(7) 87 #define DA_INT_RX_DRQ __BIT(3) 88 #define DA_TXFIFO 0x20 89 #define DA_CLKD 0x24 90 #define DA_CLKD_MCLKO_EN_SUN8I __BIT(8) 91 #define DA_CLKD_MCLKO_EN_SUN4I __BIT(7) 92 #define DA_CLKD_BCLKDIV_SUN8I __BITS(7,4) 93 #define DA_CLKD_BCLKDIV_SUN4I __BITS(6,4) 94 #define DA_CLKD_BCLKDIV_8 3 95 #define DA_CLKD_BCLKDIV_16 5 96 #define DA_CLKD_MCLKDIV __BITS(3,0) 97 #define DA_CLKD_MCLKDIV_1 0 98 #define DA_TXCNT 0x28 99 #define DA_RXCNT 0x2c 100 #define DA_CHCFG 0x30 /* sun8i */ 101 #define DA_CHCFG_TX_SLOT_HIZ __BIT(9) 102 #define DA_CHCFG_TXN_STATE __BIT(8) 103 #define DA_CHCFG_RX_SLOT_NUM __BITS(6,4) 104 #define DA_CHCFG_TX_SLOT_NUM __BITS(2,0) 105 106 #define DA_CHSEL_OFFSET __BITS(13,12) /* sun8i */ 107 #define DA_CHSEL_EN __BITS(11,4) 108 #define DA_CHSEL_SEL __BITS(2,0) 109 110 enum sunxi_i2s_type { 111 SUNXI_I2S_SUN4I, 112 SUNXI_I2S_SUN8I, 113 }; 114 115 struct sunxi_i2s_config { 116 const char *name; 117 enum sunxi_i2s_type type; 118 bus_size_t txchsel; 119 bus_size_t txchmap; 120 bus_size_t rxchsel; 121 bus_size_t rxchmap; 122 }; 123 124 static const struct sunxi_i2s_config sun50i_a64_codec_config = { 125 .name = "Audio Codec (digital part)", 126 .type = SUNXI_I2S_SUN4I, 127 .txchsel = 0x30, 128 .txchmap = 0x34, 129 .rxchsel = 0x38, 130 .rxchmap = 0x3c, 131 }; 132 133 static const struct sunxi_i2s_config sun8i_h3_config = { 134 .name = "I2S/PCM controller", 135 .type = SUNXI_I2S_SUN8I, 136 .txchsel = 0x34, 137 .txchmap = 0x44, 138 .rxchsel = 0x54, 139 .rxchmap = 0x58, 140 }; 141 142 static const struct of_compat_data compat_data[] = { 143 { "allwinner,sun50i-a64-codec-i2s", 144 (uintptr_t)&sun50i_a64_codec_config }, 145 { "allwinner,sun8i-h3-i2s", 146 (uintptr_t)&sun8i_h3_config }, 147 148 { NULL } 149 }; 150 151 struct sunxi_i2s_softc; 152 153 struct sunxi_i2s_chan { 154 struct sunxi_i2s_softc *ch_sc; 155 u_int ch_mode; 156 157 struct fdtbus_dma *ch_dma; 158 struct fdtbus_dma_req ch_req; 159 160 audio_params_t ch_params; 161 162 bus_addr_t ch_start_phys; 163 bus_addr_t ch_end_phys; 164 bus_addr_t ch_cur_phys; 165 int ch_blksize; 166 167 void (*ch_intr)(void *); 168 void *ch_intrarg; 169 }; 170 171 struct sunxi_i2s_dma { 172 LIST_ENTRY(sunxi_i2s_dma) dma_list; 173 bus_dmamap_t dma_map; 174 void *dma_addr; 175 size_t dma_size; 176 bus_dma_segment_t dma_segs[1]; 177 int dma_nsegs; 178 }; 179 180 struct sunxi_i2s_softc { 181 device_t sc_dev; 182 bus_space_tag_t sc_bst; 183 bus_space_handle_t sc_bsh; 184 bus_dma_tag_t sc_dmat; 185 int sc_phandle; 186 bus_addr_t sc_baseaddr; 187 struct clk *sc_clk; 188 189 struct sunxi_i2s_config *sc_cfg; 190 191 LIST_HEAD(, sunxi_i2s_dma) sc_dmalist; 192 193 kmutex_t sc_lock; 194 kmutex_t sc_intr_lock; 195 196 struct audio_format sc_format; 197 198 struct sunxi_i2s_chan sc_pchan; 199 struct sunxi_i2s_chan sc_rchan; 200 201 struct audio_dai_device sc_dai; 202 }; 203 204 #define I2S_TYPE(sc) ((sc)->sc_cfg->type) 205 206 #define I2S_READ(sc, reg) \ 207 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 208 #define I2S_WRITE(sc, reg, val) \ 209 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 210 211 static const u_int sun4i_i2s_bclk_divmap[] = { 212 [0] = 2, 213 [1] = 4, 214 [2] = 6, 215 [3] = 8, 216 [4] = 12, 217 [5] = 16, 218 }; 219 220 static const u_int sun4i_i2s_mclk_divmap[] = { 221 [0] = 1, 222 [1] = 2, 223 [2] = 4, 224 [3] = 6, 225 [4] = 8, 226 [5] = 12, 227 [6] = 16, 228 [7] = 24, 229 }; 230 231 static const u_int sun8i_i2s_divmap[] = { 232 [1] = 1, 233 [2] = 2, 234 [3] = 4, 235 [4] = 6, 236 [5] = 8, 237 [6] = 12, 238 [7] = 16, 239 [8] = 24, 240 [9] = 32, 241 [10] = 48, 242 [11] = 64, 243 [12] = 96, 244 [13] = 128, 245 [14] = 176, 246 [15] = 192, 247 }; 248 249 static u_int 250 sunxi_i2s_div_to_regval(const u_int *divmap, u_int divmaplen, u_int div) 251 { 252 u_int n; 253 254 for (n = 0; n < divmaplen; n++) 255 if (divmap[n] == div) 256 return n; 257 258 return -1; 259 } 260 261 static int 262 sunxi_i2s_allocdma(struct sunxi_i2s_softc *sc, size_t size, 263 size_t align, struct sunxi_i2s_dma *dma) 264 { 265 int error; 266 267 dma->dma_size = size; 268 error = bus_dmamem_alloc(sc->sc_dmat, dma->dma_size, align, 0, 269 dma->dma_segs, 1, &dma->dma_nsegs, BUS_DMA_WAITOK); 270 if (error) 271 return error; 272 273 error = bus_dmamem_map(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs, 274 dma->dma_size, &dma->dma_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT); 275 if (error) 276 goto free; 277 278 error = bus_dmamap_create(sc->sc_dmat, dma->dma_size, dma->dma_nsegs, 279 dma->dma_size, 0, BUS_DMA_WAITOK, &dma->dma_map); 280 if (error) 281 goto unmap; 282 283 error = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_addr, 284 dma->dma_size, NULL, BUS_DMA_WAITOK); 285 if (error) 286 goto destroy; 287 288 return 0; 289 290 destroy: 291 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 292 unmap: 293 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 294 free: 295 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 296 297 return error; 298 } 299 300 static void 301 sunxi_i2s_freedma(struct sunxi_i2s_softc *sc, struct sunxi_i2s_dma *dma) 302 { 303 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 304 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 305 bus_dmamem_unmap(sc->sc_dmat, dma->dma_addr, dma->dma_size); 306 bus_dmamem_free(sc->sc_dmat, dma->dma_segs, dma->dma_nsegs); 307 } 308 309 static int 310 sunxi_i2s_transfer(struct sunxi_i2s_chan *ch) 311 { 312 bus_dma_segment_t seg; 313 314 seg.ds_addr = ch->ch_cur_phys; 315 seg.ds_len = ch->ch_blksize; 316 ch->ch_req.dreq_segs = &seg; 317 ch->ch_req.dreq_nsegs = 1; 318 319 return fdtbus_dma_transfer(ch->ch_dma, &ch->ch_req); 320 } 321 322 static int 323 sunxi_i2s_query_format(void *priv, audio_format_query_t *afp) 324 { 325 struct sunxi_i2s_softc * const sc = priv; 326 327 return audio_query_format(&sc->sc_format, 1, afp); 328 } 329 330 static int 331 sunxi_i2s_set_format(void *priv, int setmode, 332 const audio_params_t *play, const audio_params_t *rec, 333 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 334 { 335 336 return 0; 337 } 338 339 static void * 340 sunxi_i2s_allocm(void *priv, int dir, size_t size) 341 { 342 struct sunxi_i2s_softc * const sc = priv; 343 struct sunxi_i2s_dma *dma; 344 int error; 345 346 dma = kmem_alloc(sizeof(*dma), KM_SLEEP); 347 348 error = sunxi_i2s_allocdma(sc, size, 16, dma); 349 if (error) { 350 kmem_free(dma, sizeof(*dma)); 351 device_printf(sc->sc_dev, "couldn't allocate DMA memory (%d)\n", 352 error); 353 return NULL; 354 } 355 356 LIST_INSERT_HEAD(&sc->sc_dmalist, dma, dma_list); 357 358 return dma->dma_addr; 359 } 360 361 static void 362 sunxi_i2s_freem(void *priv, void *addr, size_t size) 363 { 364 struct sunxi_i2s_softc * const sc = priv; 365 struct sunxi_i2s_dma *dma; 366 367 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 368 if (dma->dma_addr == addr) { 369 sunxi_i2s_freedma(sc, dma); 370 LIST_REMOVE(dma, dma_list); 371 kmem_free(dma, sizeof(*dma)); 372 break; 373 } 374 } 375 376 static int 377 sunxi_i2s_get_props(void *priv) 378 { 379 struct sunxi_i2s_softc * const sc = priv; 380 int props = 0; 381 382 if (sc->sc_pchan.ch_dma != NULL) 383 props |= AUDIO_PROP_PLAYBACK; 384 if (sc->sc_rchan.ch_dma != NULL) 385 props |= AUDIO_PROP_CAPTURE; 386 if (sc->sc_pchan.ch_dma != NULL && sc->sc_rchan.ch_dma != NULL) 387 props |= AUDIO_PROP_FULLDUPLEX; 388 389 return props; 390 } 391 392 static int 393 sunxi_i2s_round_blocksize(void *priv, int bs, int mode, 394 const audio_params_t *params) 395 { 396 bs &= ~3; 397 if (bs == 0) 398 bs = 4; 399 return bs; 400 } 401 402 static int 403 sunxi_i2s_trigger_output(void *priv, void *start, void *end, int blksize, 404 void (*intr)(void *), void *intrarg, const audio_params_t *params) 405 { 406 struct sunxi_i2s_softc * const sc = priv; 407 struct sunxi_i2s_chan *ch = &sc->sc_pchan; 408 struct sunxi_i2s_dma *dma; 409 bus_addr_t pstart; 410 bus_size_t psize; 411 uint32_t val; 412 int error; 413 414 if (ch->ch_dma == NULL) 415 return EIO; 416 417 pstart = 0; 418 psize = (uintptr_t)end - (uintptr_t)start; 419 420 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 421 if (dma->dma_addr == start) { 422 pstart = dma->dma_map->dm_segs[0].ds_addr; 423 break; 424 } 425 if (pstart == 0) { 426 device_printf(sc->sc_dev, "bad addr %p\n", start); 427 return EINVAL; 428 } 429 430 ch->ch_intr = intr; 431 ch->ch_intrarg = intrarg; 432 ch->ch_start_phys = ch->ch_cur_phys = pstart; 433 ch->ch_end_phys = pstart + psize; 434 ch->ch_blksize = blksize; 435 436 /* Flush FIFO */ 437 val = I2S_READ(sc, DA_FCTL); 438 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FTX); 439 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FTX); 440 441 /* Reset TX sample counter */ 442 I2S_WRITE(sc, DA_TXCNT, 0); 443 444 /* Enable transmitter block */ 445 val = I2S_READ(sc, DA_CTL); 446 I2S_WRITE(sc, DA_CTL, val | DA_CTL_TXEN); 447 448 /* Enable TX DRQ */ 449 val = I2S_READ(sc, DA_INT); 450 I2S_WRITE(sc, DA_INT, val | DA_INT_TX_DRQ); 451 452 /* Start DMA transfer */ 453 error = sunxi_i2s_transfer(ch); 454 if (error != 0) { 455 aprint_error_dev(sc->sc_dev, 456 "failed to start DMA transfer: %d\n", error); 457 return error; 458 } 459 460 return 0; 461 } 462 463 static int 464 sunxi_i2s_trigger_input(void *priv, void *start, void *end, int blksize, 465 void (*intr)(void *), void *intrarg, const audio_params_t *params) 466 { 467 struct sunxi_i2s_softc * const sc = priv; 468 struct sunxi_i2s_chan *ch = &sc->sc_rchan; 469 struct sunxi_i2s_dma *dma; 470 bus_addr_t pstart; 471 bus_size_t psize; 472 uint32_t val; 473 int error; 474 475 if (ch->ch_dma == NULL) 476 return EIO; 477 478 pstart = 0; 479 psize = (uintptr_t)end - (uintptr_t)start; 480 481 LIST_FOREACH(dma, &sc->sc_dmalist, dma_list) 482 if (dma->dma_addr == start) { 483 pstart = dma->dma_map->dm_segs[0].ds_addr; 484 break; 485 } 486 if (pstart == 0) { 487 device_printf(sc->sc_dev, "bad addr %p\n", start); 488 return EINVAL; 489 } 490 491 ch->ch_intr = intr; 492 ch->ch_intrarg = intrarg; 493 ch->ch_start_phys = ch->ch_cur_phys = pstart; 494 ch->ch_end_phys = pstart + psize; 495 ch->ch_blksize = blksize; 496 497 /* Flush FIFO */ 498 val = I2S_READ(sc, DA_FCTL); 499 I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FRX); 500 I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FRX); 501 502 /* Reset RX sample counter */ 503 I2S_WRITE(sc, DA_RXCNT, 0); 504 505 /* Enable receiver block */ 506 val = I2S_READ(sc, DA_CTL); 507 I2S_WRITE(sc, DA_CTL, val | DA_CTL_RXEN); 508 509 /* Enable RX DRQ */ 510 val = I2S_READ(sc, DA_INT); 511 I2S_WRITE(sc, DA_INT, val | DA_INT_RX_DRQ); 512 513 /* Start DMA transfer */ 514 error = sunxi_i2s_transfer(ch); 515 if (error != 0) { 516 aprint_error_dev(sc->sc_dev, 517 "failed to start DMA transfer: %d\n", error); 518 return error; 519 } 520 521 return 0; 522 } 523 524 static int 525 sunxi_i2s_halt_output(void *priv) 526 { 527 struct sunxi_i2s_softc * const sc = priv; 528 struct sunxi_i2s_chan *ch = &sc->sc_pchan; 529 uint32_t val; 530 531 if (ch->ch_dma == NULL) 532 return EIO; 533 534 /* Disable DMA channel */ 535 fdtbus_dma_halt(ch->ch_dma); 536 537 /* Disable transmitter block */ 538 val = I2S_READ(sc, DA_CTL); 539 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_TXEN); 540 541 /* Disable TX DRQ */ 542 val = I2S_READ(sc, DA_INT); 543 I2S_WRITE(sc, DA_INT, val & ~DA_INT_TX_DRQ); 544 545 ch->ch_intr = NULL; 546 ch->ch_intrarg = NULL; 547 548 return 0; 549 } 550 551 static int 552 sunxi_i2s_halt_input(void *priv) 553 { 554 struct sunxi_i2s_softc * const sc = priv; 555 struct sunxi_i2s_chan *ch = &sc->sc_rchan; 556 uint32_t val; 557 558 if (ch->ch_dma == NULL) 559 return EIO; 560 561 /* Disable DMA channel */ 562 fdtbus_dma_halt(ch->ch_dma); 563 564 /* Disable receiver block */ 565 val = I2S_READ(sc, DA_CTL); 566 I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_RXEN); 567 568 /* Disable RX DRQ */ 569 val = I2S_READ(sc, DA_INT); 570 I2S_WRITE(sc, DA_INT, val & ~DA_INT_RX_DRQ); 571 572 return 0; 573 } 574 575 static void 576 sunxi_i2s_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread) 577 { 578 struct sunxi_i2s_softc * const sc = priv; 579 580 *intr = &sc->sc_intr_lock; 581 *thread = &sc->sc_lock; 582 } 583 584 static const struct audio_hw_if sunxi_i2s_hw_if = { 585 .query_format = sunxi_i2s_query_format, 586 .set_format = sunxi_i2s_set_format, 587 .allocm = sunxi_i2s_allocm, 588 .freem = sunxi_i2s_freem, 589 .get_props = sunxi_i2s_get_props, 590 .round_blocksize = sunxi_i2s_round_blocksize, 591 .trigger_output = sunxi_i2s_trigger_output, 592 .trigger_input = sunxi_i2s_trigger_input, 593 .halt_output = sunxi_i2s_halt_output, 594 .halt_input = sunxi_i2s_halt_input, 595 .get_locks = sunxi_i2s_get_locks, 596 }; 597 598 static void 599 sunxi_i2s_dmaintr(void *priv) 600 { 601 struct sunxi_i2s_chan * const ch = priv; 602 struct sunxi_i2s_softc * const sc = ch->ch_sc; 603 604 mutex_enter(&sc->sc_intr_lock); 605 ch->ch_cur_phys += ch->ch_blksize; 606 if (ch->ch_cur_phys >= ch->ch_end_phys) 607 ch->ch_cur_phys = ch->ch_start_phys; 608 609 if (ch->ch_intr) { 610 ch->ch_intr(ch->ch_intrarg); 611 sunxi_i2s_transfer(ch); 612 } 613 mutex_exit(&sc->sc_intr_lock); 614 } 615 616 static int 617 sunxi_i2s_chan_init(struct sunxi_i2s_softc *sc, 618 struct sunxi_i2s_chan *ch, u_int mode, const char *dmaname) 619 { 620 ch->ch_sc = sc; 621 ch->ch_mode = mode; 622 ch->ch_dma = fdtbus_dma_get(sc->sc_phandle, dmaname, sunxi_i2s_dmaintr, ch); 623 if (ch->ch_dma == NULL) 624 return ENXIO; 625 626 if (mode == AUMODE_PLAY) { 627 ch->ch_req.dreq_dir = FDT_DMA_WRITE; 628 ch->ch_req.dreq_dev_phys = 629 sc->sc_baseaddr + DA_TXFIFO; 630 } else { 631 ch->ch_req.dreq_dir = FDT_DMA_READ; 632 ch->ch_req.dreq_dev_phys = 633 sc->sc_baseaddr + DA_RXFIFO; 634 } 635 ch->ch_req.dreq_mem_opt.opt_bus_width = 16; 636 ch->ch_req.dreq_mem_opt.opt_burst_len = 8; 637 ch->ch_req.dreq_dev_opt.opt_bus_width = 16; 638 ch->ch_req.dreq_dev_opt.opt_burst_len = 8; 639 640 return 0; 641 } 642 643 static int 644 sunxi_i2s_dai_set_sysclk(audio_dai_tag_t dai, u_int rate, int dir) 645 { 646 struct sunxi_i2s_softc * const sc = audio_dai_private(dai); 647 int bclk_val, mclk_val; 648 uint32_t val; 649 int error; 650 651 error = clk_set_rate(sc->sc_clk, SUNXI_I2S_CLK_RATE); 652 if (error != 0) { 653 aprint_error_dev(sc->sc_dev, 654 "couldn't set mod clock rate to %u Hz: %d\n", SUNXI_I2S_CLK_RATE, error); 655 return error; 656 } 657 error = clk_enable(sc->sc_clk); 658 if (error != 0) { 659 aprint_error_dev(sc->sc_dev, 660 "couldn't enable mod clock: %d\n", error); 661 return error; 662 } 663 664 const u_int bclk_prate = I2S_TYPE(sc) == SUNXI_I2S_SUN4I ? rate : SUNXI_I2S_CLK_RATE; 665 666 const u_int bclk_div = bclk_prate / (2 * 32 * SUNXI_I2S_SAMPLE_RATE); 667 const u_int mclk_div = SUNXI_I2S_CLK_RATE / rate; 668 669 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 670 bclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_bclk_divmap, 671 __arraycount(sun4i_i2s_bclk_divmap), bclk_div); 672 mclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_mclk_divmap, 673 __arraycount(sun4i_i2s_mclk_divmap), mclk_div); 674 } else { 675 bclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, 676 __arraycount(sun8i_i2s_divmap), bclk_div); 677 mclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap, 678 __arraycount(sun8i_i2s_divmap), mclk_div); 679 } 680 if (bclk_val == -1 || mclk_val == -1) { 681 aprint_error_dev(sc->sc_dev, "couldn't configure bclk/mclk dividers\n"); 682 return EIO; 683 } 684 685 val = I2S_READ(sc, DA_CLKD); 686 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 687 val |= DA_CLKD_MCLKO_EN_SUN4I; 688 val &= ~DA_CLKD_BCLKDIV_SUN4I; 689 val |= __SHIFTIN(bclk_val, DA_CLKD_BCLKDIV_SUN4I); 690 } else { 691 val |= DA_CLKD_MCLKO_EN_SUN8I; 692 val &= ~DA_CLKD_BCLKDIV_SUN8I; 693 val |= __SHIFTIN(bclk_val, DA_CLKD_BCLKDIV_SUN8I); 694 } 695 val &= ~DA_CLKD_MCLKDIV; 696 val |= __SHIFTIN(mclk_val, DA_CLKD_MCLKDIV); 697 I2S_WRITE(sc, DA_CLKD, val); 698 699 return 0; 700 } 701 702 static int 703 sunxi_i2s_dai_set_format(audio_dai_tag_t dai, u_int format) 704 { 705 struct sunxi_i2s_softc * const sc = audio_dai_private(dai); 706 uint32_t ctl, fat0, chsel; 707 u_int offset; 708 709 const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK); 710 const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK); 711 const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK); 712 713 ctl = I2S_READ(sc, DA_CTL); 714 fat0 = I2S_READ(sc, DA_FAT0); 715 716 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 717 fat0 &= ~DA_FAT0_FMT; 718 switch (fmt) { 719 case AUDIO_DAI_FORMAT_I2S: 720 fat0 |= __SHIFTIN(DA_FMT_I2S, DA_FAT0_FMT); 721 break; 722 case AUDIO_DAI_FORMAT_RJ: 723 fat0 |= __SHIFTIN(DA_FMT_RJ, DA_FAT0_FMT); 724 break; 725 case AUDIO_DAI_FORMAT_LJ: 726 fat0 |= __SHIFTIN(DA_FMT_LJ, DA_FAT0_FMT); 727 break; 728 default: 729 return EINVAL; 730 } 731 ctl &= ~DA_CTL_PCM; 732 } else { 733 ctl &= ~DA_CTL_MODE_SEL; 734 switch (fmt) { 735 case AUDIO_DAI_FORMAT_I2S: 736 ctl |= __SHIFTIN(DA_CTL_MODE_SEL_LJ, DA_CTL_MODE_SEL); 737 offset = 1; 738 break; 739 case AUDIO_DAI_FORMAT_LJ: 740 ctl |= __SHIFTIN(DA_CTL_MODE_SEL_LJ, DA_CTL_MODE_SEL); 741 offset = 0; 742 break; 743 case AUDIO_DAI_FORMAT_RJ: 744 ctl |= __SHIFTIN(DA_CTL_MODE_SEL_RJ, DA_CTL_MODE_SEL); 745 offset = 0; 746 break; 747 case AUDIO_DAI_FORMAT_DSPA: 748 ctl |= __SHIFTIN(DA_CTL_MODE_SEL_PCM, DA_CTL_MODE_SEL); 749 offset = 1; 750 break; 751 case AUDIO_DAI_FORMAT_DSPB: 752 ctl |= __SHIFTIN(DA_CTL_MODE_SEL_PCM, DA_CTL_MODE_SEL); 753 offset = 0; 754 break; 755 default: 756 return EINVAL; 757 } 758 759 chsel = I2S_READ(sc, sc->sc_cfg->txchsel); 760 chsel &= ~DA_CHSEL_OFFSET; 761 chsel |= __SHIFTIN(offset, DA_CHSEL_OFFSET); 762 I2S_WRITE(sc, sc->sc_cfg->txchsel, chsel); 763 764 chsel = I2S_READ(sc, sc->sc_cfg->rxchsel); 765 chsel &= ~DA_CHSEL_OFFSET; 766 chsel |= __SHIFTIN(offset, DA_CHSEL_OFFSET); 767 I2S_WRITE(sc, sc->sc_cfg->rxchsel, chsel); 768 } 769 770 fat0 &= ~(DA_FAT0_LRCP|DA_FAT0_BCP); 771 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 772 if (AUDIO_DAI_POLARITY_B(pol)) 773 fat0 |= __SHIFTIN(DA_BCP_INVERTED, DA_FAT0_BCP); 774 if (AUDIO_DAI_POLARITY_F(pol)) 775 fat0 |= __SHIFTIN(DA_LRCP_INVERTED, DA_FAT0_LRCP); 776 } else { 777 if (AUDIO_DAI_POLARITY_B(pol)) 778 fat0 |= __SHIFTIN(DA_BCP_INVERTED, DA_FAT0_BCP); 779 if (!AUDIO_DAI_POLARITY_F(pol)) 780 fat0 |= __SHIFTIN(DA_LRCP_INVERTED, DA_FAT0_LRCP); 781 782 fat0 &= ~DA_FAT0_LRCK_PERIOD; 783 fat0 |= __SHIFTIN(32 - 1, DA_FAT0_LRCK_PERIOD); 784 } 785 786 switch (clk) { 787 case AUDIO_DAI_CLOCK_CBM_CFM: 788 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 789 ctl |= DA_CTL_MS; /* codec is master */ 790 } else { 791 ctl &= ~DA_CTL_BCLK_OUT; 792 ctl &= ~DA_CLK_LRCK_OUT; 793 } 794 break; 795 case AUDIO_DAI_CLOCK_CBS_CFS: 796 if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) { 797 ctl &= ~DA_CTL_MS; /* codec is slave */ 798 } else { 799 ctl |= DA_CTL_BCLK_OUT; 800 ctl |= DA_CLK_LRCK_OUT; 801 } 802 break; 803 default: 804 return EINVAL; 805 } 806 807 I2S_WRITE(sc, DA_CTL, ctl); 808 I2S_WRITE(sc, DA_FAT0, fat0); 809 810 return 0; 811 } 812 813 static audio_dai_tag_t 814 sunxi_i2s_dai_get_tag(device_t dev, const void *data, size_t len) 815 { 816 struct sunxi_i2s_softc * const sc = device_private(dev); 817 818 if (len != 4) 819 return NULL; 820 821 return &sc->sc_dai; 822 } 823 824 static struct fdtbus_dai_controller_func sunxi_i2s_dai_funcs = { 825 .get_tag = sunxi_i2s_dai_get_tag 826 }; 827 828 static int 829 sunxi_i2s_clock_init(struct sunxi_i2s_softc *sc) 830 { 831 const int phandle = sc->sc_phandle; 832 struct fdtbus_reset *rst; 833 struct clk *clk; 834 int error; 835 836 sc->sc_clk = fdtbus_clock_get(phandle, "mod"); 837 if (sc->sc_clk == NULL) { 838 aprint_error(": couldn't find mod clock\n"); 839 return ENXIO; 840 } 841 842 /* Enable APB clock */ 843 clk = fdtbus_clock_get(phandle, "apb"); 844 if (clk == NULL) { 845 aprint_error(": couldn't find apb clock\n"); 846 return ENXIO; 847 } 848 error = clk_enable(clk); 849 if (error != 0) { 850 aprint_error(": couldn't enable apb clock: %d\n", error); 851 return error; 852 } 853 854 /* De-assert reset */ 855 rst = fdtbus_reset_get_index(phandle, 0); 856 if (rst == NULL) { 857 aprint_error(": couldn't find reset\n"); 858 return ENXIO; 859 } 860 error = fdtbus_reset_deassert(rst); 861 if (error != 0) { 862 aprint_error(": couldn't de-assert reset: %d\n", error); 863 return error; 864 } 865 866 return 0; 867 } 868 869 static int 870 sunxi_i2s_match(device_t parent, cfdata_t cf, void *aux) 871 { 872 struct fdt_attach_args * const faa = aux; 873 874 return of_match_compat_data(faa->faa_phandle, compat_data); 875 } 876 877 static void 878 sunxi_i2s_attach(device_t parent, device_t self, void *aux) 879 { 880 struct sunxi_i2s_softc * const sc = device_private(self); 881 struct fdt_attach_args * const faa = aux; 882 const int phandle = faa->faa_phandle; 883 bus_addr_t addr; 884 bus_size_t size; 885 uint32_t val; 886 887 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 888 aprint_error(": couldn't get registers\n"); 889 return; 890 } 891 892 sc->sc_dev = self; 893 sc->sc_phandle = phandle; 894 sc->sc_baseaddr = addr; 895 sc->sc_bst = faa->faa_bst; 896 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 897 aprint_error(": couldn't map registers\n"); 898 return; 899 } 900 sc->sc_dmat = faa->faa_dmat; 901 LIST_INIT(&sc->sc_dmalist); 902 sc->sc_cfg = (void *)of_search_compatible(phandle, compat_data)->data; 903 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 904 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 905 906 if (sunxi_i2s_clock_init(sc) != 0) 907 return; 908 909 /* At least one of these needs to succeed */ 910 sunxi_i2s_chan_init(sc, &sc->sc_pchan, AUMODE_PLAY, "tx"); 911 sunxi_i2s_chan_init(sc, &sc->sc_rchan, AUMODE_RECORD, "rx"); 912 if (sc->sc_pchan.ch_dma == NULL && sc->sc_rchan.ch_dma == NULL) { 913 aprint_error(": couldn't setup channels\n"); 914 return; 915 } 916 917 aprint_naive("\n"); 918 aprint_normal(": %s\n", sc->sc_cfg->name); 919 920 /* Reset */ 921 val = I2S_READ(sc, DA_CTL); 922 val &= ~(DA_CTL_TXEN|DA_CTL_RXEN|DA_CTL_GEN); 923 I2S_WRITE(sc, DA_CTL, val); 924 925 val = I2S_READ(sc, DA_FCTL); 926 val &= ~(DA_FCTL_FTX|DA_FCTL_FRX); 927 I2S_WRITE(sc, DA_FCTL, val); 928 929 I2S_WRITE(sc, DA_TXCNT, 0); 930 I2S_WRITE(sc, DA_RXCNT, 0); 931 932 /* Enable */ 933 val = I2S_READ(sc, DA_CTL); 934 val |= DA_CTL_GEN; 935 I2S_WRITE(sc, DA_CTL, val); 936 val |= DA_CTL_SDO_EN; 937 I2S_WRITE(sc, DA_CTL, val); 938 939 /* Setup channels */ 940 I2S_WRITE(sc, sc->sc_cfg->txchmap, 0x76543210); 941 val = I2S_READ(sc, sc->sc_cfg->txchsel); 942 val &= ~DA_CHSEL_EN; 943 val |= __SHIFTIN(3, DA_CHSEL_EN); 944 val &= ~DA_CHSEL_SEL; 945 val |= __SHIFTIN(1, DA_CHSEL_SEL); 946 I2S_WRITE(sc, sc->sc_cfg->txchsel, val); 947 I2S_WRITE(sc, sc->sc_cfg->rxchmap, 0x76543210); 948 val = I2S_READ(sc, sc->sc_cfg->rxchsel); 949 val &= ~DA_CHSEL_EN; 950 val |= __SHIFTIN(3, DA_CHSEL_EN); 951 val &= ~DA_CHSEL_SEL; 952 val |= __SHIFTIN(1, DA_CHSEL_SEL); 953 I2S_WRITE(sc, sc->sc_cfg->rxchsel, val); 954 955 if (I2S_TYPE(sc) == SUNXI_I2S_SUN8I) { 956 val = I2S_READ(sc, DA_CHCFG); 957 val &= ~DA_CHCFG_TX_SLOT_NUM; 958 val |= __SHIFTIN(1, DA_CHCFG_TX_SLOT_NUM); 959 val &= ~DA_CHCFG_RX_SLOT_NUM; 960 val |= __SHIFTIN(1, DA_CHCFG_RX_SLOT_NUM); 961 I2S_WRITE(sc, DA_CHCFG, val); 962 } 963 964 sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD; 965 sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE; 966 sc->sc_format.validbits = 16; 967 sc->sc_format.precision = 16; 968 sc->sc_format.channels = 2; 969 sc->sc_format.channel_mask = AUFMT_STEREO; 970 sc->sc_format.frequency_type = 1; 971 sc->sc_format.frequency[0] = SUNXI_I2S_SAMPLE_RATE; 972 973 sc->sc_dai.dai_set_sysclk = sunxi_i2s_dai_set_sysclk; 974 sc->sc_dai.dai_set_format = sunxi_i2s_dai_set_format; 975 sc->sc_dai.dai_hw_if = &sunxi_i2s_hw_if; 976 sc->sc_dai.dai_dev = self; 977 sc->sc_dai.dai_priv = sc; 978 fdtbus_register_dai_controller(self, phandle, &sunxi_i2s_dai_funcs); 979 } 980 981 CFATTACH_DECL_NEW(sunxi_i2s, sizeof(struct sunxi_i2s_softc), 982 sunxi_i2s_match, sunxi_i2s_attach, NULL, NULL); 983
Indexes created Sun Oct 12 09:09:55 GMT 2025