sunxi_intc.c revision 1.1.2.2
1 1.1.2.2 skrll /* $NetBSD: sunxi_intc.c,v 1.1.2.2 2017/08/28 17:51:32 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /*- 4 1.1.2.2 skrll * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 16 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1.2.2 skrll * SUCH DAMAGE. 27 1.1.2.2 skrll */ 28 1.1.2.2 skrll 29 1.1.2.2 skrll #define _INTR_PRIVATE 30 1.1.2.2 skrll 31 1.1.2.2 skrll #include <sys/cdefs.h> 32 1.1.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: sunxi_intc.c,v 1.1.2.2 2017/08/28 17:51:32 skrll Exp $"); 33 1.1.2.2 skrll 34 1.1.2.2 skrll #include <sys/param.h> 35 1.1.2.2 skrll #include <sys/kernel.h> 36 1.1.2.2 skrll #include <sys/bus.h> 37 1.1.2.2 skrll #include <sys/device.h> 38 1.1.2.2 skrll #include <sys/intr.h> 39 1.1.2.2 skrll #include <sys/systm.h> 40 1.1.2.2 skrll 41 1.1.2.2 skrll #include <dev/fdt/fdtvar.h> 42 1.1.2.2 skrll 43 1.1.2.2 skrll #include <arm/cpu.h> 44 1.1.2.2 skrll #include <arm/pic/picvar.h> 45 1.1.2.2 skrll #include <arm/fdt/arm_fdtvar.h> 46 1.1.2.2 skrll 47 1.1.2.2 skrll #define INTC_MAX_SOURCES 96 48 1.1.2.2 skrll #define INTC_MAX_GROUPS 3 49 1.1.2.2 skrll 50 1.1.2.2 skrll #define INTC_VECTOR_REG 0x00 51 1.1.2.2 skrll #define INTC_BASE_ADDR_REG 0x04 52 1.1.2.2 skrll #define INTC_PROTECT_REG 0x08 53 1.1.2.2 skrll #define INTC_PROTECT_EN __BIT(0) 54 1.1.2.2 skrll #define INTC_NMII_CTRL_REG 0x0c 55 1.1.2.2 skrll #define INTC_IRQ_PEND_REG(n) (0x10 + ((n) * 4)) 56 1.1.2.2 skrll #define INTC_FIQ_PEND_REG(n) (0x20 + ((n) * 4)) 57 1.1.2.2 skrll #define INTC_SEL_REG(n) (0x30 + ((n) * 4)) 58 1.1.2.2 skrll #define INTC_EN_REG(n) (0x40 + ((n) * 4)) 59 1.1.2.2 skrll #define INTC_MASK_REG(n) (0x50 + ((n) * 4)) 60 1.1.2.2 skrll #define INTC_RESP_REG(n) (0x60 + ((n) * 4)) 61 1.1.2.2 skrll #define INTC_FORCE_REG(n) (0x70 + ((n) * 4)) 62 1.1.2.2 skrll #define INTC_SRC_PRIO_REG(n) (0x80 + ((n) * 4)) 63 1.1.2.2 skrll 64 1.1.2.2 skrll static const char * const compatible[] = { 65 1.1.2.2 skrll "allwinner,sun4i-a10-ic", 66 1.1.2.2 skrll NULL 67 1.1.2.2 skrll }; 68 1.1.2.2 skrll 69 1.1.2.2 skrll struct sunxi_intc_softc { 70 1.1.2.2 skrll device_t sc_dev; 71 1.1.2.2 skrll bus_space_tag_t sc_bst; 72 1.1.2.2 skrll bus_space_handle_t sc_bsh; 73 1.1.2.2 skrll int sc_phandle; 74 1.1.2.2 skrll 75 1.1.2.2 skrll uint32_t sc_enabled_irqs[INTC_MAX_GROUPS]; 76 1.1.2.2 skrll 77 1.1.2.2 skrll struct pic_softc sc_pic; 78 1.1.2.2 skrll }; 79 1.1.2.2 skrll 80 1.1.2.2 skrll static struct sunxi_intc_softc *intc_softc; 81 1.1.2.2 skrll 82 1.1.2.2 skrll #define PICTOSOFTC(pic) \ 83 1.1.2.2 skrll ((void *)((uintptr_t)(pic) - offsetof(struct sunxi_intc_softc, sc_pic))) 84 1.1.2.2 skrll 85 1.1.2.2 skrll #define INTC_READ(sc, reg) \ 86 1.1.2.2 skrll bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 87 1.1.2.2 skrll #define INTC_WRITE(sc, reg, val) \ 88 1.1.2.2 skrll bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 89 1.1.2.2 skrll 90 1.1.2.2 skrll static void 91 1.1.2.2 skrll sunxi_intc_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 92 1.1.2.2 skrll { 93 1.1.2.2 skrll struct sunxi_intc_softc * const sc = PICTOSOFTC(pic); 94 1.1.2.2 skrll const u_int group = irqbase / 32; 95 1.1.2.2 skrll 96 1.1.2.2 skrll KASSERT((mask & sc->sc_enabled_irqs[group]) == 0); 97 1.1.2.2 skrll sc->sc_enabled_irqs[group] |= mask; 98 1.1.2.2 skrll INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]); 99 1.1.2.2 skrll } 100 1.1.2.2 skrll 101 1.1.2.2 skrll static void 102 1.1.2.2 skrll sunxi_intc_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 103 1.1.2.2 skrll { 104 1.1.2.2 skrll struct sunxi_intc_softc * const sc = PICTOSOFTC(pic); 105 1.1.2.2 skrll const u_int group = irqbase / 32; 106 1.1.2.2 skrll 107 1.1.2.2 skrll sc->sc_enabled_irqs[group] &= ~mask; 108 1.1.2.2 skrll INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]); 109 1.1.2.2 skrll } 110 1.1.2.2 skrll 111 1.1.2.2 skrll static void 112 1.1.2.2 skrll sunxi_intc_establish_irq(struct pic_softc *pic, struct intrsource *is) 113 1.1.2.2 skrll { 114 1.1.2.2 skrll KASSERT(is->is_irq < INTC_MAX_SOURCES); 115 1.1.2.2 skrll KASSERT(is->is_type == IST_LEVEL); 116 1.1.2.2 skrll } 117 1.1.2.2 skrll 118 1.1.2.2 skrll static void 119 1.1.2.2 skrll sunxi_intc_set_priority(struct pic_softc *pic, int ipl) 120 1.1.2.2 skrll { 121 1.1.2.2 skrll } 122 1.1.2.2 skrll 123 1.1.2.2 skrll static const struct pic_ops sunxi_intc_picops = { 124 1.1.2.2 skrll .pic_unblock_irqs = sunxi_intc_unblock_irqs, 125 1.1.2.2 skrll .pic_block_irqs = sunxi_intc_block_irqs, 126 1.1.2.2 skrll .pic_establish_irq = sunxi_intc_establish_irq, 127 1.1.2.2 skrll .pic_set_priority = sunxi_intc_set_priority, 128 1.1.2.2 skrll }; 129 1.1.2.2 skrll 130 1.1.2.2 skrll static void * 131 1.1.2.2 skrll sunxi_intc_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 132 1.1.2.2 skrll int (*func)(void *), void *arg) 133 1.1.2.2 skrll { 134 1.1.2.2 skrll /* 1st cell is the interrupt number */ 135 1.1.2.2 skrll const u_int irq = be32toh(specifier[0]); 136 1.1.2.2 skrll 137 1.1.2.2 skrll if (irq >= INTC_MAX_SOURCES) { 138 1.1.2.2 skrll #ifdef DIAGNOSTIC 139 1.1.2.2 skrll device_printf(dev, "IRQ %u is invalid\n", irq); 140 1.1.2.2 skrll #endif 141 1.1.2.2 skrll return NULL; 142 1.1.2.2 skrll } 143 1.1.2.2 skrll 144 1.1.2.2 skrll const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 145 1.1.2.2 skrll 146 1.1.2.2 skrll return intr_establish(irq, ipl, IST_LEVEL | mpsafe, func, arg); 147 1.1.2.2 skrll } 148 1.1.2.2 skrll 149 1.1.2.2 skrll static void 150 1.1.2.2 skrll sunxi_intc_fdt_disestablish(device_t dev, void *ih) 151 1.1.2.2 skrll { 152 1.1.2.2 skrll intr_disestablish(ih); 153 1.1.2.2 skrll } 154 1.1.2.2 skrll 155 1.1.2.2 skrll static bool 156 1.1.2.2 skrll sunxi_intc_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 157 1.1.2.2 skrll { 158 1.1.2.2 skrll /* 1st cell is the interrupt number */ 159 1.1.2.2 skrll if (!specifier) 160 1.1.2.2 skrll return false; 161 1.1.2.2 skrll const u_int irq = be32toh(specifier[0]); 162 1.1.2.2 skrll 163 1.1.2.2 skrll snprintf(buf, buflen, "INTC irq %d", irq); 164 1.1.2.2 skrll 165 1.1.2.2 skrll return true; 166 1.1.2.2 skrll } 167 1.1.2.2 skrll 168 1.1.2.2 skrll static const struct fdtbus_interrupt_controller_func sunxi_intc_fdt_funcs = { 169 1.1.2.2 skrll .establish = sunxi_intc_fdt_establish, 170 1.1.2.2 skrll .disestablish = sunxi_intc_fdt_disestablish, 171 1.1.2.2 skrll .intrstr = sunxi_intc_fdt_intrstr, 172 1.1.2.2 skrll }; 173 1.1.2.2 skrll 174 1.1.2.2 skrll static int 175 1.1.2.2 skrll sunxi_intc_find_pending_irqs(struct sunxi_intc_softc *sc, u_int group) 176 1.1.2.2 skrll { 177 1.1.2.2 skrll uint32_t pend; 178 1.1.2.2 skrll 179 1.1.2.2 skrll pend = INTC_READ(sc, INTC_IRQ_PEND_REG(group)); 180 1.1.2.2 skrll 181 1.1.2.2 skrll KASSERT((sc->sc_enabled_irqs[group] & pend) == pend); 182 1.1.2.2 skrll 183 1.1.2.2 skrll if (pend == 0) 184 1.1.2.2 skrll return 0; 185 1.1.2.2 skrll 186 1.1.2.2 skrll return pic_mark_pending_sources(&sc->sc_pic, group * 32, pend); 187 1.1.2.2 skrll } 188 1.1.2.2 skrll 189 1.1.2.2 skrll static void 190 1.1.2.2 skrll sunxi_intc_irq_handler(void *frame) 191 1.1.2.2 skrll { 192 1.1.2.2 skrll struct cpu_info * const ci = curcpu(); 193 1.1.2.2 skrll struct sunxi_intc_softc * const sc = intc_softc; 194 1.1.2.2 skrll const int oldipl = ci->ci_cpl; 195 1.1.2.2 skrll const uint32_t oldipl_mask = __BIT(oldipl); 196 1.1.2.2 skrll int ipl_mask = 0; 197 1.1.2.2 skrll 198 1.1.2.2 skrll ci->ci_data.cpu_nintr++; 199 1.1.2.2 skrll 200 1.1.2.2 skrll if (sc->sc_enabled_irqs[0]) 201 1.1.2.2 skrll ipl_mask |= sunxi_intc_find_pending_irqs(sc, 0); 202 1.1.2.2 skrll if (sc->sc_enabled_irqs[1]) 203 1.1.2.2 skrll ipl_mask |= sunxi_intc_find_pending_irqs(sc, 1); 204 1.1.2.2 skrll if (sc->sc_enabled_irqs[2]) 205 1.1.2.2 skrll ipl_mask |= sunxi_intc_find_pending_irqs(sc, 2); 206 1.1.2.2 skrll 207 1.1.2.2 skrll if ((ipl_mask & ~oldipl_mask) > oldipl_mask) 208 1.1.2.2 skrll pic_do_pending_ints(I32_bit, oldipl, frame); 209 1.1.2.2 skrll } 210 1.1.2.2 skrll 211 1.1.2.2 skrll static int 212 1.1.2.2 skrll sunxi_intc_match(device_t parent, cfdata_t cf, void *aux) 213 1.1.2.2 skrll { 214 1.1.2.2 skrll struct fdt_attach_args * const faa = aux; 215 1.1.2.2 skrll 216 1.1.2.2 skrll return of_match_compatible(faa->faa_phandle, compatible); 217 1.1.2.2 skrll } 218 1.1.2.2 skrll 219 1.1.2.2 skrll static void 220 1.1.2.2 skrll sunxi_intc_attach(device_t parent, device_t self, void *aux) 221 1.1.2.2 skrll { 222 1.1.2.2 skrll struct sunxi_intc_softc * const sc = device_private(self); 223 1.1.2.2 skrll struct fdt_attach_args * const faa = aux; 224 1.1.2.2 skrll const int phandle = faa->faa_phandle; 225 1.1.2.2 skrll bus_addr_t addr; 226 1.1.2.2 skrll bus_size_t size; 227 1.1.2.2 skrll int error, i; 228 1.1.2.2 skrll 229 1.1.2.2 skrll if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 230 1.1.2.2 skrll aprint_error(": couldn't get registers\n"); 231 1.1.2.2 skrll return; 232 1.1.2.2 skrll } 233 1.1.2.2 skrll 234 1.1.2.2 skrll sc->sc_dev = self; 235 1.1.2.2 skrll sc->sc_phandle = phandle; 236 1.1.2.2 skrll sc->sc_bst = faa->faa_bst; 237 1.1.2.2 skrll if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 238 1.1.2.2 skrll aprint_error(": couldn't map registers\n"); 239 1.1.2.2 skrll return; 240 1.1.2.2 skrll } 241 1.1.2.2 skrll 242 1.1.2.2 skrll aprint_naive("\n"); 243 1.1.2.2 skrll aprint_normal(": Interrupt Controller\n"); 244 1.1.2.2 skrll 245 1.1.2.2 skrll /* Disable IRQs */ 246 1.1.2.2 skrll for (i = 0; i < INTC_MAX_GROUPS; i++) { 247 1.1.2.2 skrll INTC_WRITE(sc, INTC_EN_REG(i), 0); 248 1.1.2.2 skrll INTC_WRITE(sc, INTC_MASK_REG(i), 0); 249 1.1.2.2 skrll } 250 1.1.2.2 skrll /* Disable user mode access to intc registers */ 251 1.1.2.2 skrll INTC_WRITE(sc, INTC_PROTECT_REG, INTC_PROTECT_EN); 252 1.1.2.2 skrll 253 1.1.2.2 skrll sc->sc_pic.pic_ops = &sunxi_intc_picops; 254 1.1.2.2 skrll sc->sc_pic.pic_maxsources = INTC_MAX_SOURCES; 255 1.1.2.2 skrll snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "intc"); 256 1.1.2.2 skrll pic_add(&sc->sc_pic, 0); 257 1.1.2.2 skrll 258 1.1.2.2 skrll error = fdtbus_register_interrupt_controller(self, phandle, 259 1.1.2.2 skrll &sunxi_intc_fdt_funcs); 260 1.1.2.2 skrll if (error) { 261 1.1.2.2 skrll aprint_error_dev(self, "couldn't register with fdtbus: %d\n", 262 1.1.2.2 skrll error); 263 1.1.2.2 skrll return; 264 1.1.2.2 skrll } 265 1.1.2.2 skrll 266 1.1.2.2 skrll KASSERT(intc_softc == NULL); 267 1.1.2.2 skrll intc_softc = sc; 268 1.1.2.2 skrll arm_fdt_irq_set_handler(sunxi_intc_irq_handler); 269 1.1.2.2 skrll } 270 1.1.2.2 skrll 271 1.1.2.2 skrll CFATTACH_DECL_NEW(sunxi_intc, sizeof(struct sunxi_intc_softc), 272 1.1.2.2 skrll sunxi_intc_match, sunxi_intc_attach, NULL, NULL); 273
Indexes created Tue Oct 28 02:10:10 GMT 2025