sunxi_intc.c revision 1.5.8.1
1 /* $NetBSD: sunxi_intc.c,v 1.5.8.1 2021/04/03 22:28:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #define _INTR_PRIVATE 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_intc.c,v 1.5.8.1 2021/04/03 22:28:19 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/kernel.h> 39 #include <sys/lwp.h> 40 #include <sys/systm.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #include <arm/cpu.h> 45 #include <arm/pic/picvar.h> 46 #include <arm/fdt/arm_fdtvar.h> 47 48 #define INTC_MAX_SOURCES 96 49 #define INTC_MAX_GROUPS 3 50 51 #define INTC_VECTOR_REG 0x00 52 #define INTC_BASE_ADDR_REG 0x04 53 #define INTC_PROTECT_REG 0x08 54 #define INTC_PROTECT_EN __BIT(0) 55 #define INTC_NMII_CTRL_REG 0x0c 56 #define INTC_IRQ_PEND_REG(n) (0x10 + ((n) * 4)) 57 #define INTC_FIQ_PEND_REG(n) (0x20 + ((n) * 4)) 58 #define INTC_SEL_REG(n) (0x30 + ((n) * 4)) 59 #define INTC_EN_REG(n) (0x40 + ((n) * 4)) 60 #define INTC_MASK_REG(n) (0x50 + ((n) * 4)) 61 #define INTC_RESP_REG(n) (0x60 + ((n) * 4)) 62 #define INTC_FORCE_REG(n) (0x70 + ((n) * 4)) 63 #define INTC_SRC_PRIO_REG(n) (0x80 + ((n) * 4)) 64 65 static const struct device_compatible_entry compat_data[] = { 66 { .compat = "allwinner,sun4i-a10-ic" }, 67 DEVICE_COMPAT_EOL 68 }; 69 70 struct sunxi_intc_softc { 71 device_t sc_dev; 72 bus_space_tag_t sc_bst; 73 bus_space_handle_t sc_bsh; 74 int sc_phandle; 75 76 uint32_t sc_enabled_irqs[INTC_MAX_GROUPS]; 77 78 struct pic_softc sc_pic; 79 }; 80 81 static struct sunxi_intc_softc *intc_softc; 82 83 #define PICTOSOFTC(pic) \ 84 ((void *)((uintptr_t)(pic) - offsetof(struct sunxi_intc_softc, sc_pic))) 85 86 #define INTC_READ(sc, reg) \ 87 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 88 #define INTC_WRITE(sc, reg, val) \ 89 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 90 91 static void 92 sunxi_intc_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 93 { 94 struct sunxi_intc_softc * const sc = PICTOSOFTC(pic); 95 const u_int group = irqbase / 32; 96 97 KASSERT((mask & sc->sc_enabled_irqs[group]) == 0); 98 sc->sc_enabled_irqs[group] |= mask; 99 INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]); 100 INTC_WRITE(sc, INTC_MASK_REG(group), ~sc->sc_enabled_irqs[group]); 101 } 102 103 static void 104 sunxi_intc_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t mask) 105 { 106 struct sunxi_intc_softc * const sc = PICTOSOFTC(pic); 107 const u_int group = irqbase / 32; 108 109 sc->sc_enabled_irqs[group] &= ~mask; 110 INTC_WRITE(sc, INTC_EN_REG(group), sc->sc_enabled_irqs[group]); 111 INTC_WRITE(sc, INTC_MASK_REG(group), ~sc->sc_enabled_irqs[group]); 112 } 113 114 static void 115 sunxi_intc_establish_irq(struct pic_softc *pic, struct intrsource *is) 116 { 117 KASSERT(is->is_irq < INTC_MAX_SOURCES); 118 KASSERT(is->is_type == IST_LEVEL); 119 } 120 121 static void 122 sunxi_intc_set_priority(struct pic_softc *pic, int ipl) 123 { 124 } 125 126 static const struct pic_ops sunxi_intc_picops = { 127 .pic_unblock_irqs = sunxi_intc_unblock_irqs, 128 .pic_block_irqs = sunxi_intc_block_irqs, 129 .pic_establish_irq = sunxi_intc_establish_irq, 130 .pic_set_priority = sunxi_intc_set_priority, 131 }; 132 133 static void * 134 sunxi_intc_fdt_establish(device_t dev, u_int *specifier, int ipl, int flags, 135 int (*func)(void *), void *arg, const char *xname) 136 { 137 /* 1st cell is the interrupt number */ 138 const u_int irq = be32toh(specifier[0]); 139 140 if (irq >= INTC_MAX_SOURCES) { 141 #ifdef DIAGNOSTIC 142 device_printf(dev, "IRQ %u is invalid\n", irq); 143 #endif 144 return NULL; 145 } 146 147 const u_int mpsafe = (flags & FDT_INTR_MPSAFE) ? IST_MPSAFE : 0; 148 149 return intr_establish_xname(irq, ipl, IST_LEVEL | mpsafe, func, arg, 150 xname); 151 } 152 153 static void 154 sunxi_intc_fdt_disestablish(device_t dev, void *ih) 155 { 156 intr_disestablish(ih); 157 } 158 159 static bool 160 sunxi_intc_fdt_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 161 { 162 /* 1st cell is the interrupt number */ 163 if (!specifier) 164 return false; 165 const u_int irq = be32toh(specifier[0]); 166 167 snprintf(buf, buflen, "INTC irq %d", irq); 168 169 return true; 170 } 171 172 static const struct fdtbus_interrupt_controller_func sunxi_intc_fdt_funcs = { 173 .establish = sunxi_intc_fdt_establish, 174 .disestablish = sunxi_intc_fdt_disestablish, 175 .intrstr = sunxi_intc_fdt_intrstr, 176 }; 177 178 static int 179 sunxi_intc_find_pending_irqs(struct sunxi_intc_softc *sc, u_int group) 180 { 181 uint32_t pend; 182 183 pend = INTC_READ(sc, INTC_IRQ_PEND_REG(group)); 184 pend &= sc->sc_enabled_irqs[group]; 185 186 if (pend == 0) 187 return 0; 188 189 INTC_WRITE(sc, INTC_IRQ_PEND_REG(group), pend); 190 191 return pic_mark_pending_sources(&sc->sc_pic, group * 32, pend); 192 } 193 194 static void 195 sunxi_intc_irq_handler(void *frame) 196 { 197 struct cpu_info * const ci = curcpu(); 198 struct sunxi_intc_softc * const sc = intc_softc; 199 const int oldipl = ci->ci_cpl; 200 const uint32_t oldipl_mask = __BIT(oldipl); 201 int ipl_mask = 0; 202 203 ci->ci_data.cpu_nintr++; 204 205 if (sc->sc_enabled_irqs[0]) 206 ipl_mask |= sunxi_intc_find_pending_irqs(sc, 0); 207 if (sc->sc_enabled_irqs[1]) 208 ipl_mask |= sunxi_intc_find_pending_irqs(sc, 1); 209 if (sc->sc_enabled_irqs[2]) 210 ipl_mask |= sunxi_intc_find_pending_irqs(sc, 2); 211 212 if ((ipl_mask & ~oldipl_mask) > oldipl_mask) 213 pic_do_pending_ints(I32_bit, oldipl, frame); 214 } 215 216 static int 217 sunxi_intc_match(device_t parent, cfdata_t cf, void *aux) 218 { 219 struct fdt_attach_args * const faa = aux; 220 221 return of_compatible_match(faa->faa_phandle, compat_data); 222 } 223 224 static void 225 sunxi_intc_attach(device_t parent, device_t self, void *aux) 226 { 227 struct sunxi_intc_softc * const sc = device_private(self); 228 struct fdt_attach_args * const faa = aux; 229 const int phandle = faa->faa_phandle; 230 bus_addr_t addr; 231 bus_size_t size; 232 int error, i; 233 234 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 235 aprint_error(": couldn't get registers\n"); 236 return; 237 } 238 239 sc->sc_dev = self; 240 sc->sc_phandle = phandle; 241 sc->sc_bst = faa->faa_bst; 242 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 243 aprint_error(": couldn't map registers\n"); 244 return; 245 } 246 247 aprint_naive("\n"); 248 aprint_normal(": Interrupt Controller\n"); 249 250 /* Disable IRQs */ 251 for (i = 0; i < INTC_MAX_GROUPS; i++) { 252 INTC_WRITE(sc, INTC_EN_REG(i), 0); 253 INTC_WRITE(sc, INTC_MASK_REG(i), ~0U); 254 INTC_WRITE(sc, INTC_IRQ_PEND_REG(i), 255 INTC_READ(sc, INTC_IRQ_PEND_REG(i))); 256 } 257 /* Disable user mode access to intc registers */ 258 INTC_WRITE(sc, INTC_PROTECT_REG, INTC_PROTECT_EN); 259 260 sc->sc_pic.pic_ops = &sunxi_intc_picops; 261 sc->sc_pic.pic_maxsources = INTC_MAX_SOURCES; 262 snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "intc"); 263 pic_add(&sc->sc_pic, 0); 264 265 error = fdtbus_register_interrupt_controller(self, phandle, 266 &sunxi_intc_fdt_funcs); 267 if (error) { 268 aprint_error_dev(self, "couldn't register with fdtbus: %d\n", 269 error); 270 return; 271 } 272 273 KASSERT(intc_softc == NULL); 274 intc_softc = sc; 275 arm_fdt_irq_set_handler(sunxi_intc_irq_handler); 276 } 277 278 CFATTACH_DECL_NEW(sunxi_intc, sizeof(struct sunxi_intc_softc), 279 sunxi_intc_match, sunxi_intc_attach, NULL, NULL); 280
Indexes created Mon Oct 20 20:10:13 GMT 2025