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sunxi_lcdc.c revision 1.1 
      1 /* $NetBSD: sunxi_lcdc.c,v 1.1 2019/01/30 01:24:00 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2019 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 __KERNEL_RCSID(0, "$NetBSD: sunxi_lcdc.c,v 1.1 2019/01/30 01:24:00 jmcneill Exp $");
     31 
     32 #include <sys/param.h>
     33 #include <sys/bus.h>
     34 #include <sys/device.h>
     35 #include <sys/intr.h>
     36 #include <sys/systm.h>
     37 #include <sys/kernel.h>
     38 #include <sys/conf.h>
     39 
     40 #include <drm/drmP.h>
     41 #include <drm/drm_crtc_helper.h>
     42 
     43 #include <dev/fdt/fdtvar.h>
     44 #include <dev/fdt/fdt_port.h>
     45 
     46 #define	TCON_GCTL_REG		0x000
     47 #define	 TCON_GCTL_TCON_EN			__BIT(31)
     48 #define	 TCON_GCTL_GAMMA_EN			__BIT(30)
     49 #define	 TCON_GCTL_IO_MAP_SEL			__BIT(0)
     50 
     51 #define	TCON_GINT0_REG		0x004
     52 #define	TCON_GINT1_REG		0x008
     53 #define	 TCON_GINT1_TCON1_LINE_INT_NUM		__BITS(11,0)
     54 
     55 #define	TCON1_CTL_REG		0x090
     56 #define	 TCON1_CTL_TCON1_EN			__BIT(31)
     57 #define	 TCON1_CTL_START_DELAY			__BITS(8,4)
     58 #define	 TCON1_CTL_TCON1_SRC_SEL		__BIT(1)
     59 #define	TCON1_BASIC0_REG	0x094
     60 #define	TCON1_BASIC1_REG	0x098
     61 #define	TCON1_BASIC2_REG	0x09c
     62 #define	TCON1_BASIC3_REG	0x0a0
     63 #define	TCON1_BASIC4_REG	0x0a4
     64 #define	TCON1_BASIC5_REG	0x0a8
     65 
     66 #define	TCON1_IO_POL_REG	0x0f0
     67 #define	 TCON1_IO_POL_IO3_INV			__BIT(27)
     68 #define	 TCON1_IO_POL_IO2_INV			__BIT(26)
     69 #define	 TCON1_IO_POL_IO1_INV			__BIT(25)
     70 #define	 TCON1_IO_POL_IO0_INV			__BIT(24)
     71 #define	 TCON1_IO_POL_DATA_INV			__BITS(23,0)
     72 #define	TCON1_IO_TRI_REG	0x0f4
     73 
     74 enum {
     75 	MIXER_PORT_INPUT = 0,
     76 	MIXER_PORT_OUTPUT = 1,
     77 };
     78 
     79 static const char * const compatible[] = {
     80 	"allwinner,sun50i-a64-tcon-lcd",
     81 	"allwinner,sun50i-a64-tcon-tv",
     82 	NULL
     83 };
     84 
     85 struct sunxi_lcdc_softc;
     86 
     87 struct sunxi_lcdc_encoder {
     88 	struct drm_encoder	base;
     89 	struct sunxi_lcdc_softc *sc;
     90 	struct drm_display_mode	curmode;
     91 };
     92 
     93 struct sunxi_lcdc_softc {
     94 	device_t		sc_dev;
     95 	bus_space_tag_t		sc_bst;
     96 	bus_space_handle_t	sc_bsh;
     97 	int			sc_phandle;
     98 
     99 	struct clk		*sc_clk_ch[2];
    100 
    101 	struct sunxi_lcdc_encoder sc_encoder;
    102 	struct drm_connector	sc_connector;
    103 
    104 	struct fdt_device_ports	sc_ports;
    105 };
    106 
    107 #define	to_sunxi_lcdc_encoder(x)	container_of(x, struct sunxi_lcdc_encoder, base)
    108 
    109 #define	TCON_READ(sc, reg)				\
    110 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
    111 #define	TCON_WRITE(sc, reg, val)			\
    112 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
    113 
    114 static void
    115 sunxi_lcdc_destroy(struct drm_encoder *encoder)
    116 {
    117 }
    118 
    119 static const struct drm_encoder_funcs sunxi_lcdc_funcs = {
    120 	.destroy = sunxi_lcdc_destroy,
    121 };
    122 
    123 static void
    124 sunxi_lcdc_tcon1_dpms(struct drm_encoder *encoder, int mode)
    125 {
    126 }
    127 
    128 static bool
    129 sunxi_lcdc_tcon1_mode_fixup(struct drm_encoder *encoder,
    130     const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode)
    131 {
    132 	return true;
    133 }
    134 
    135 static void
    136 sunxi_lcdc_tcon1_mode_set(struct drm_encoder *encoder,
    137     struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode)
    138 {
    139 	struct sunxi_lcdc_encoder *lcdc_encoder = to_sunxi_lcdc_encoder(encoder);
    140 
    141 	lcdc_encoder->curmode = *adjusted_mode;
    142 }
    143 
    144 static void
    145 sunxi_lcdc_tcon1_prepare(struct drm_encoder *encoder)
    146 {
    147 	struct sunxi_lcdc_encoder *lcdc_encoder = to_sunxi_lcdc_encoder(encoder);
    148 	struct sunxi_lcdc_softc * const sc = lcdc_encoder->sc;
    149 	uint32_t val;
    150 
    151 	val = TCON_READ(sc, TCON_GCTL_REG);
    152 	val |= TCON_GCTL_TCON_EN;
    153 	TCON_WRITE(sc, TCON_GCTL_REG, val);
    154 
    155 	TCON_WRITE(sc, TCON1_IO_POL_REG, 0);
    156 	TCON_WRITE(sc, TCON1_IO_TRI_REG, 0xffffffff);
    157 }
    158 
    159 static void
    160 sunxi_lcdc_tcon1_commit(struct drm_encoder *encoder)
    161 {
    162 	struct sunxi_lcdc_encoder *lcdc_encoder = to_sunxi_lcdc_encoder(encoder);
    163 	struct sunxi_lcdc_softc * const sc = lcdc_encoder->sc;
    164 	struct drm_display_mode *mode = &lcdc_encoder->curmode;
    165 	uint32_t val;
    166 	int error;
    167 
    168 	const u_int interlace_p = (mode->flags & DRM_MODE_FLAG_INTERLACE) != 0;
    169 	const u_int hspw = mode->hsync_end - mode->hsync_start;
    170 	const u_int hbp = mode->htotal - mode->hsync_start;
    171 	const u_int vspw = mode->vsync_end - mode->vsync_start;
    172 	const u_int vbp = mode->vtotal - mode->vsync_start;
    173 	const u_int vblank_len =
    174 	    ((mode->vtotal << interlace_p) >> 1) - mode->vdisplay - 2;
    175 	const u_int start_delay =
    176 	    vblank_len >= 32 ? 30 : vblank_len - 2;
    177 
    178 	val = TCON1_CTL_TCON1_EN |
    179 	      __SHIFTIN(start_delay, TCON1_CTL_START_DELAY);
    180 	TCON_WRITE(sc, TCON1_CTL_REG, val);
    181 
    182 	TCON_WRITE(sc, TCON1_BASIC0_REG, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
    183 	TCON_WRITE(sc, TCON1_BASIC1_REG, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
    184 	TCON_WRITE(sc, TCON1_BASIC2_REG, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
    185 	TCON_WRITE(sc, TCON1_BASIC3_REG, ((mode->htotal - 1) << 16) | (hbp - 1));
    186 	TCON_WRITE(sc, TCON1_BASIC4_REG, ((mode->vtotal * 2) << 16) | (vbp - 1));
    187 	TCON_WRITE(sc, TCON1_BASIC5_REG, ((hspw - 1) << 16) | (vspw - 1));
    188 
    189 	TCON_WRITE(sc, TCON_GINT1_REG,
    190 	    __SHIFTIN(start_delay + 2, TCON_GINT1_TCON1_LINE_INT_NUM));
    191 
    192 	if (sc->sc_clk_ch[1] != NULL) {
    193 		error = clk_set_rate(sc->sc_clk_ch[1], mode->crtc_clock * 1000);
    194 		if (error != 0) {
    195 			device_printf(sc->sc_dev, "failed to set CH1 PLL rate to %u Hz: %d\n",
    196 			    mode->crtc_clock * 1000, error);
    197 			return;
    198 		}
    199 		error = clk_enable(sc->sc_clk_ch[1]);
    200 		if (error != 0) {
    201 			device_printf(sc->sc_dev, "failed to enable CH1 PLL: %d\n", error);
    202 			return;
    203 		}
    204 	} else {
    205 		device_printf(sc->sc_dev, "no CH1 PLL configured\n");
    206 	}
    207 }
    208 
    209 static const struct drm_encoder_helper_funcs sunxi_lcdc_tcon1_helper_funcs = {
    210 	.dpms = sunxi_lcdc_tcon1_dpms,
    211 	.mode_fixup = sunxi_lcdc_tcon1_mode_fixup,
    212 	.prepare = sunxi_lcdc_tcon1_prepare,
    213 	.commit = sunxi_lcdc_tcon1_commit,
    214 	.mode_set = sunxi_lcdc_tcon1_mode_set,
    215 };
    216 
    217 static int
    218 sunxi_lcdc_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate)
    219 {
    220 	struct sunxi_lcdc_softc * const sc = device_private(dev);
    221 	struct fdt_endpoint *in_ep = fdt_endpoint_remote(ep);
    222 	struct fdt_endpoint *out_ep;
    223 	struct drm_crtc *crtc;
    224 	int error;
    225 
    226 	if (!activate)
    227 		return EINVAL;
    228 
    229 	if (fdt_endpoint_port_index(ep) != MIXER_PORT_INPUT)
    230 		return EINVAL;
    231 
    232 	if (fdt_endpoint_type(in_ep) != EP_DRM_CRTC)
    233 		return EINVAL;
    234 
    235 	crtc = fdt_endpoint_get_data(in_ep);
    236 
    237 	sc->sc_encoder.sc = sc;
    238 
    239 	out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, MIXER_PORT_OUTPUT, 1);
    240 	if (out_ep != NULL) {
    241 		drm_encoder_init(crtc->dev, &sc->sc_encoder.base, &sunxi_lcdc_funcs,
    242 		    DRM_MODE_ENCODER_TMDS);
    243 		drm_encoder_helper_add(&sc->sc_encoder.base, &sunxi_lcdc_tcon1_helper_funcs);
    244 
    245 		error = fdt_endpoint_activate(out_ep, activate);
    246 		if (error != 0)
    247 			return error;
    248 		sc->sc_encoder.base.possible_crtcs = 1 << drm_crtc_index(crtc);
    249 	}
    250 
    251 	return 0;
    252 }
    253 
    254 static void *
    255 sunxi_lcdc_ep_get_data(device_t dev, struct fdt_endpoint *ep)
    256 {
    257 	struct sunxi_lcdc_softc * const sc = device_private(dev);
    258 
    259 	return &sc->sc_encoder;
    260 }
    261 
    262 static int
    263 sunxi_lcdc_match(device_t parent, cfdata_t cf, void *aux)
    264 {
    265 	struct fdt_attach_args * const faa = aux;
    266 
    267 	return of_match_compatible(faa->faa_phandle, compatible);
    268 }
    269 
    270 static void
    271 sunxi_lcdc_attach(device_t parent, device_t self, void *aux)
    272 {
    273 	struct sunxi_lcdc_softc * const sc = device_private(self);
    274 	struct fdt_attach_args * const faa = aux;
    275 	const int phandle = faa->faa_phandle;
    276 	struct fdtbus_reset *rst;
    277 	struct clk *clk;
    278 	bus_addr_t addr;
    279 	bus_size_t size;
    280 
    281 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
    282 		aprint_error(": couldn't get registers\n");
    283 		return;
    284 	}
    285 
    286 	rst = fdtbus_reset_get(phandle, "lcd");
    287 	if (rst == NULL || fdtbus_reset_deassert(rst) != 0) {
    288 		aprint_error(": couldn't de-assert reset\n");
    289 		return;
    290 	}
    291 
    292 	clk = fdtbus_clock_get(phandle, "ahb");
    293 	if (clk == NULL || clk_enable(clk) != 0) {
    294 		aprint_error(": couldn't enable bus clock\n");
    295 		return;
    296 	}
    297 
    298 	sc->sc_dev = self;
    299 	sc->sc_bst = faa->faa_bst;
    300 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
    301 		aprint_error(": couldn't map registers\n");
    302 		return;
    303 	}
    304 	sc->sc_phandle = faa->faa_phandle;
    305 	sc->sc_clk_ch[0] = fdtbus_clock_get(phandle, "tcon-ch0");
    306 	sc->sc_clk_ch[1] = fdtbus_clock_get(phandle, "tcon-ch1");
    307 
    308 	aprint_naive("\n");
    309 	aprint_normal(": Timing Controller\n");
    310 
    311 	sc->sc_ports.dp_ep_activate = sunxi_lcdc_ep_activate;
    312 	sc->sc_ports.dp_ep_get_data = sunxi_lcdc_ep_get_data;
    313 	fdt_ports_register(&sc->sc_ports, self, phandle, EP_DRM_ENCODER);
    314 }
    315 
    316 CFATTACH_DECL_NEW(sunxi_lcdc, sizeof(struct sunxi_lcdc_softc),
    317 	sunxi_lcdc_match, sunxi_lcdc_attach, NULL, NULL);
    318