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      1  1.19     skrll /* $NetBSD: sunxi_mixer.c,v 1.19 2022/06/28 05:19:03 skrll Exp $ */
      2   1.1  jmcneill 
      3   1.1  jmcneill /*-
      4   1.1  jmcneill  * Copyright (c) 2019 Jared D. McNeill <jmcneill (at) invisible.ca>
      5   1.1  jmcneill  * All rights reserved.
      6   1.1  jmcneill  *
      7   1.1  jmcneill  * Redistribution and use in source and binary forms, with or without
      8   1.1  jmcneill  * modification, are permitted provided that the following conditions
      9   1.1  jmcneill  * are met:
     10   1.1  jmcneill  * 1. Redistributions of source code must retain the above copyright
     11   1.1  jmcneill  *    notice, this list of conditions and the following disclaimer.
     12   1.1  jmcneill  * 2. Redistributions in binary form must reproduce the above copyright
     13   1.1  jmcneill  *    notice, this list of conditions and the following disclaimer in the
     14   1.1  jmcneill  *    documentation and/or other materials provided with the distribution.
     15   1.1  jmcneill  *
     16   1.1  jmcneill  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17   1.1  jmcneill  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18   1.1  jmcneill  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19   1.1  jmcneill  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20   1.1  jmcneill  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21   1.1  jmcneill  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22   1.1  jmcneill  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23   1.1  jmcneill  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24   1.1  jmcneill  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25   1.1  jmcneill  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26   1.1  jmcneill  * SUCH DAMAGE.
     27   1.1  jmcneill  */
     28   1.1  jmcneill 
     29   1.1  jmcneill #include <sys/cdefs.h>
     30  1.19     skrll __KERNEL_RCSID(0, "$NetBSD: sunxi_mixer.c,v 1.19 2022/06/28 05:19:03 skrll Exp $");
     31   1.1  jmcneill 
     32   1.1  jmcneill #include <sys/param.h>
     33   1.1  jmcneill #include <sys/bus.h>
     34  1.18  riastrad #include <sys/conf.h>
     35   1.1  jmcneill #include <sys/device.h>
     36   1.1  jmcneill #include <sys/intr.h>
     37   1.1  jmcneill #include <sys/kernel.h>
     38   1.6  jmcneill #include <sys/sysctl.h>
     39  1.18  riastrad #include <sys/systm.h>
     40  1.18  riastrad 
     41  1.18  riastrad #include <dev/fdt/fdt_port.h>
     42  1.18  riastrad #include <dev/fdt/fdtvar.h>
     43  1.18  riastrad 
     44  1.18  riastrad #include <arm/sunxi/sunxi_drm.h>
     45   1.1  jmcneill 
     46   1.1  jmcneill #include <drm/drm_crtc.h>
     47   1.1  jmcneill #include <drm/drm_crtc_helper.h>
     48  1.18  riastrad #include <drm/drm_drv.h>
     49  1.17  riastrad #include <drm/drm_fourcc.h>
     50   1.1  jmcneill #include <drm/drm_plane_helper.h>
     51  1.17  riastrad #include <drm/drm_vblank.h>
     52   1.1  jmcneill 
     53   1.6  jmcneill #define	MIXER_CURSOR_MAXWIDTH	256
     54   1.6  jmcneill #define	MIXER_CURSOR_MAXHEIGHT	256
     55   1.6  jmcneill 
     56   1.1  jmcneill #define	SUNXI_MIXER_FREQ	432000000
     57   1.1  jmcneill 
     58   1.1  jmcneill #define	GLB_BASE		0x00000
     59   1.1  jmcneill #define	BLD_BASE		0x01000
     60   1.1  jmcneill #define	OVL_BASE(n)		(0x02000 + (n) * 0x1000)
     61   1.4  jmcneill #define	VSU_BASE		0x20000
     62   1.4  jmcneill #define	CSC_BASE(n)		((n) == 0 ? 0xaa050 : 0xa0000)
     63   1.1  jmcneill 
     64   1.1  jmcneill /* GLB registers */
     65   1.1  jmcneill #define	GLB_CTL			0x000
     66   1.1  jmcneill #define	 GLB_CTL_EN				__BIT(0)
     67   1.1  jmcneill #define	GLB_STS			0x004
     68   1.1  jmcneill #define	GLB_DBUFFER		0x008
     69   1.1  jmcneill #define	 GLB_DBUFFER_DOUBLE_BUFFER_RDY		__BIT(0)
     70   1.1  jmcneill #define	GLB_SIZE		0x00c
     71   1.1  jmcneill 
     72   1.1  jmcneill /* BLD registers */
     73   1.1  jmcneill #define	BLD_FILL_COLOR_CTL	0x000
     74   1.6  jmcneill #define	 BLD_FILL_COLOR_CTL_P3_EN		__BIT(11)
     75   1.6  jmcneill #define	 BLD_FILL_COLOR_CTL_P2_EN		__BIT(10)
     76   1.3  jmcneill #define	 BLD_FILL_COLOR_CTL_P1_EN		__BIT(9)
     77   1.1  jmcneill #define	 BLD_FILL_COLOR_CTL_P0_EN		__BIT(8)
     78   1.6  jmcneill #define	 BLD_FILL_COLOR_CTL_P3_FCEN		__BIT(3)
     79   1.6  jmcneill #define	 BLD_FILL_COLOR_CTL_P2_FCEN		__BIT(2)
     80   1.6  jmcneill #define	 BLD_FILL_COLOR_CTL_P1_FCEN		__BIT(1)
     81   1.6  jmcneill #define	 BLD_FILL_COLOR_CTL_P0_FCEN		__BIT(0)
     82   1.6  jmcneill #define	BLD_FILL_COLOR(n)	(0x004 + (n) * 0x10)
     83   1.1  jmcneill #define	BLD_CH_ISIZE(n)		(0x008 + (n) * 0x10)
     84   1.1  jmcneill #define	BLD_CH_OFFSET(n)	(0x00c + (n) * 0x10)
     85   1.1  jmcneill #define	BLD_CH_RTCTL		0x080
     86   1.6  jmcneill #define	 BLD_CH_RTCTL_P3			__BITS(15,12)
     87   1.6  jmcneill #define	 BLD_CH_RTCTL_P2			__BITS(11,8)
     88   1.3  jmcneill #define	 BLD_CH_RTCTL_P1			__BITS(7,4)
     89   1.1  jmcneill #define	 BLD_CH_RTCTL_P0			__BITS(3,0)
     90   1.1  jmcneill #define	BLD_SIZE		0x08c
     91   1.1  jmcneill #define	BLD_CTL(n)		(0x090 + (n) * 0x04)
     92   1.1  jmcneill 
     93   1.3  jmcneill /* OVL_V registers */
     94   1.3  jmcneill #define	OVL_V_ATTCTL(n)		(0x000 + (n) * 0x30)
     95   1.3  jmcneill #define	 OVL_V_ATTCTL_VIDEO_UI_SEL		__BIT(15)
     96   1.3  jmcneill #define	 OVL_V_ATTCTL_LAY_FBFMT			__BITS(12,8)
     97   1.3  jmcneill #define	  OVL_V_ATTCTL_LAY_FBFMT_VYUY		0x00
     98   1.3  jmcneill #define	  OVL_V_ATTCTL_LAY_FBFMT_YVYU		0x01
     99   1.3  jmcneill #define	  OVL_V_ATTCTL_LAY_FBFMT_UYVY		0x02
    100   1.3  jmcneill #define	  OVL_V_ATTCTL_LAY_FBFMT_YUYV		0x03
    101   1.3  jmcneill #define	  OVL_V_ATTCTL_LAY_FBFMT_YUV422		0x06
    102   1.3  jmcneill #define	  OVL_V_ATTCTL_LAY_FBFMT_YUV420		0x0a
    103   1.3  jmcneill #define	  OVL_V_ATTCTL_LAY_FBFMT_YUV411		0x0e
    104  1.12  jmcneill #if BYTE_ORDER == BIG_ENDIAN
    105  1.12  jmcneill #define	  OVL_V_ATTCTL_LAY_FBFMT_ARGB_8888	0x03
    106  1.12  jmcneill #define	  OVL_V_ATTCTL_LAY_FBFMT_XRGB_8888	0x07
    107  1.12  jmcneill #else
    108   1.6  jmcneill #define	  OVL_V_ATTCTL_LAY_FBFMT_ARGB_8888	0x00
    109   1.3  jmcneill #define	  OVL_V_ATTCTL_LAY_FBFMT_XRGB_8888	0x04
    110  1.12  jmcneill #endif
    111   1.3  jmcneill #define	 OVL_V_ATTCTL_LAY0_EN			__BIT(0)
    112   1.3  jmcneill #define	OVL_V_MBSIZE(n)		(0x004 + (n) * 0x30)
    113   1.3  jmcneill #define	OVL_V_COOR(n)		(0x008 + (n) * 0x30)
    114   1.3  jmcneill #define	OVL_V_PITCH0(n)		(0x00c + (n) * 0x30)
    115   1.3  jmcneill #define	OVL_V_PITCH1(n)		(0x010 + (n) * 0x30)
    116   1.3  jmcneill #define	OVL_V_PITCH2(n)		(0x014 + (n) * 0x30)
    117   1.3  jmcneill #define	OVL_V_TOP_LADD0(n)	(0x018 + (n) * 0x30)
    118   1.3  jmcneill #define	OVL_V_TOP_LADD1(n)	(0x01c + (n) * 0x30)
    119   1.3  jmcneill #define	OVL_V_TOP_LADD2(n)	(0x020 + (n) * 0x30)
    120   1.3  jmcneill #define	OVL_V_FILL_COLOR(n)	(0x0c0 + (n) * 0x4)
    121   1.3  jmcneill #define	OVL_V_TOP_HADD0		0x0d0
    122   1.3  jmcneill #define	OVL_V_TOP_HADD1		0x0d4
    123   1.3  jmcneill #define	OVL_V_TOP_HADD2		0x0d8
    124   1.3  jmcneill #define	 OVL_V_TOP_HADD_LAYER0	__BITS(7,0)
    125   1.3  jmcneill #define	OVL_V_SIZE		0x0e8
    126   1.3  jmcneill #define	OVL_V_HDS_CTL0		0x0f0
    127   1.3  jmcneill #define	OVL_V_HDS_CTL1		0x0f4
    128   1.3  jmcneill #define	OVL_V_VDS_CTL0		0x0f8
    129   1.3  jmcneill #define	OVL_V_VDS_CTL1		0x0fc
    130   1.3  jmcneill 
    131   1.1  jmcneill /* OVL_UI registers */
    132   1.1  jmcneill #define	OVL_UI_ATTR_CTL(n)	(0x000 + (n) * 0x20)
    133   1.1  jmcneill #define	 OVL_UI_ATTR_CTL_LAY_FBFMT		__BITS(12,8)
    134  1.12  jmcneill #if BYTE_ORDER == BIG_ENDIAN
    135  1.12  jmcneill #define	  OVL_UI_ATTR_CTL_LAY_FBFMT_ARGB_8888	0x03
    136  1.12  jmcneill #define	  OVL_UI_ATTR_CTL_LAY_FBFMT_XRGB_8888	0x07
    137  1.12  jmcneill #else
    138   1.6  jmcneill #define	  OVL_UI_ATTR_CTL_LAY_FBFMT_ARGB_8888	0x00
    139   1.1  jmcneill #define	  OVL_UI_ATTR_CTL_LAY_FBFMT_XRGB_8888	0x04
    140  1.12  jmcneill #endif
    141   1.1  jmcneill #define	 OVL_UI_ATTR_CTL_LAY_EN			__BIT(0)
    142   1.1  jmcneill #define	OVL_UI_MBSIZE(n)	(0x004 + (n) * 0x20)
    143   1.1  jmcneill #define	OVL_UI_COOR(n)		(0x008 + (n) * 0x20)
    144   1.1  jmcneill #define	OVL_UI_PITCH(n)		(0x00c + (n) * 0x20)
    145   1.1  jmcneill #define	OVL_UI_TOP_LADD(n)	(0x010 + (n) * 0x20)
    146   1.6  jmcneill #define	OVL_UI_FILL_COLOR(n)	(0x018 + (n) * 0x20)
    147   1.1  jmcneill #define	OVL_UI_TOP_HADD		0x080
    148   1.6  jmcneill #define	 OVL_UI_TOP_HADD_LAYER1	__BITS(15,8)
    149   1.1  jmcneill #define	 OVL_UI_TOP_HADD_LAYER0	__BITS(7,0)
    150   1.1  jmcneill #define	OVL_UI_SIZE		0x088
    151   1.1  jmcneill 
    152   1.4  jmcneill /* VSU registers */
    153   1.4  jmcneill #define	VS_CTRL_REG		0x000
    154   1.4  jmcneill #define	 VS_CTRL_COEF_SWITCH_EN			__BIT(4)
    155   1.4  jmcneill #define	 VS_CTRL_EN				__BIT(0)
    156   1.4  jmcneill #define	VS_STATUS_REG		0x008
    157   1.4  jmcneill #define	VS_FIELD_CTRL_REG	0x00c
    158   1.4  jmcneill #define	VS_OUT_SIZE_REG		0x040
    159   1.4  jmcneill #define	VS_Y_SIZE_REG		0x080
    160   1.4  jmcneill #define	VS_Y_HSTEP_REG		0x088
    161   1.4  jmcneill #define	VS_Y_VSTEP_REG		0x08c
    162   1.4  jmcneill #define	VS_Y_HPHASE_REG		0x090
    163   1.4  jmcneill #define	VS_Y_VPHASE0_REG	0x098
    164   1.4  jmcneill #define	VS_Y_VPHASE1_REG	0x09c
    165   1.4  jmcneill #define	VS_C_SIZE_REG		0x0c0
    166   1.4  jmcneill #define	VS_C_HSTEP_REG		0x0c8
    167   1.4  jmcneill #define	VS_C_VSTEP_REG		0x0cc
    168   1.4  jmcneill #define	VS_C_HPHASE_REG		0x0d0
    169   1.4  jmcneill #define	VS_C_VPHASE0_REG	0x0d8
    170   1.4  jmcneill #define	VS_C_VPHASE1_REG	0x0dc
    171   1.4  jmcneill #define	VS_Y_HCOEF0_REG(n)	(0x200 + (n) * 0x4)
    172   1.4  jmcneill #define	VS_Y_HCOEF1_REG(n)	(0x300 + (n) * 0x4)
    173   1.4  jmcneill #define	VS_Y_VCOEF_REG(n)	(0x400 + (n) * 0x4)
    174   1.4  jmcneill #define	VS_C_HCOEF0_REG(n)	(0x600 + (n) * 0x4)
    175   1.4  jmcneill #define	VS_C_HCOEF1_REG(n)	(0x700 + (n) * 0x4)
    176   1.4  jmcneill #define	VS_C_VCOEF_REG(n)	(0x800 + (n) * 0x4)
    177   1.4  jmcneill 
    178   1.4  jmcneill /* CSC registers */
    179   1.4  jmcneill #define	CSC_BYPASS_REG		0x000
    180   1.4  jmcneill #define	 CSC_BYPASS_DISABLE			__BIT(0)
    181   1.4  jmcneill #define	CSC_COEFF0_REG(n)	(0x10 + 0x10 * (n))
    182   1.4  jmcneill #define	GLB_ALPHA_REG		0x040
    183   1.4  jmcneill 
    184   1.1  jmcneill enum {
    185   1.1  jmcneill 	MIXER_PORT_OUTPUT = 1,
    186   1.1  jmcneill };
    187   1.1  jmcneill 
    188  1.11  jakllsch struct sunxi_mixer_compat_data {
    189  1.11  jakllsch 	uint8_t ovl_ui_count;
    190  1.11  jakllsch 	uint8_t mixer_index;
    191  1.11  jakllsch };
    192  1.11  jakllsch 
    193  1.11  jakllsch struct sunxi_mixer_compat_data mixer0_data = {
    194  1.11  jakllsch 	.ovl_ui_count = 3,
    195  1.11  jakllsch 	.mixer_index = 0,
    196  1.11  jakllsch };
    197  1.11  jakllsch 
    198  1.11  jakllsch struct sunxi_mixer_compat_data mixer1_data = {
    199  1.11  jakllsch 	.ovl_ui_count = 1,
    200  1.11  jakllsch 	.mixer_index = 1,
    201  1.11  jakllsch };
    202  1.11  jakllsch 
    203  1.13   thorpej static const struct device_compatible_entry compat_data[] = {
    204  1.13   thorpej 	{ .compat = "allwinner,sun8i-h3-de2-mixer-0",
    205  1.13   thorpej 	  .data = &mixer0_data },
    206  1.19     skrll 	{ .compat = "allwinner,sun8i-v3s-de2-mixer",
    207  1.19     skrll 	  .data = &mixer0_data },
    208  1.13   thorpej 	{ .compat = "allwinner,sun50i-a64-de2-mixer-0",
    209  1.13   thorpej 	  .data = &mixer0_data },
    210  1.13   thorpej 	{ .compat = "allwinner,sun50i-a64-de2-mixer-1",
    211  1.13   thorpej 	  .data = &mixer1_data },
    212  1.13   thorpej 
    213  1.15   thorpej 	DEVICE_COMPAT_EOL
    214   1.1  jmcneill };
    215   1.1  jmcneill 
    216   1.1  jmcneill struct sunxi_mixer_softc;
    217   1.1  jmcneill 
    218   1.1  jmcneill struct sunxi_mixer_crtc {
    219   1.1  jmcneill 	struct drm_crtc		base;
    220   1.1  jmcneill 	struct sunxi_mixer_softc *sc;
    221   1.1  jmcneill };
    222   1.1  jmcneill 
    223   1.6  jmcneill struct sunxi_mixer_plane {
    224   1.3  jmcneill 	struct drm_plane	base;
    225   1.3  jmcneill 	struct sunxi_mixer_softc *sc;
    226   1.3  jmcneill };
    227   1.3  jmcneill 
    228   1.1  jmcneill struct sunxi_mixer_softc {
    229   1.1  jmcneill 	device_t		sc_dev;
    230   1.1  jmcneill 	bus_space_tag_t		sc_bst;
    231   1.1  jmcneill 	bus_space_handle_t	sc_bsh;
    232   1.1  jmcneill 	int			sc_phandle;
    233   1.1  jmcneill 
    234   1.6  jmcneill 	u_int			sc_ovl_ui_count;
    235   1.6  jmcneill 
    236   1.1  jmcneill 	struct sunxi_mixer_crtc	sc_crtc;
    237   1.6  jmcneill 	struct sunxi_mixer_plane sc_overlay;
    238   1.1  jmcneill 
    239   1.1  jmcneill 	struct fdt_device_ports	sc_ports;
    240   1.1  jmcneill };
    241   1.1  jmcneill 
    242   1.1  jmcneill #define	GLB_READ(sc, reg)				\
    243   1.1  jmcneill 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, GLB_BASE + (reg))
    244   1.1  jmcneill #define	GLB_WRITE(sc, reg, val)				\
    245   1.1  jmcneill 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, GLB_BASE + (reg), (val))
    246   1.1  jmcneill 
    247   1.1  jmcneill #define	BLD_READ(sc, reg)				\
    248   1.1  jmcneill 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, BLD_BASE + (reg))
    249   1.1  jmcneill #define	BLD_WRITE(sc, reg, val)				\
    250   1.1  jmcneill 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, BLD_BASE + (reg), (val))
    251   1.1  jmcneill 
    252   1.3  jmcneill #define	OVL_V_READ(sc, reg)				\
    253   1.6  jmcneill 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, OVL_BASE(0) + (reg))
    254   1.3  jmcneill #define	OVL_V_WRITE(sc, reg, val)			\
    255   1.6  jmcneill 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, OVL_BASE(0) + (reg), (val))
    256   1.3  jmcneill 
    257   1.6  jmcneill #define	OVL_UI_READ(sc, n, reg)				\
    258   1.6  jmcneill 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, OVL_BASE((n) + 1) + (reg))
    259   1.6  jmcneill #define	OVL_UI_WRITE(sc, n, reg, val)			\
    260   1.6  jmcneill 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, OVL_BASE((n) + 1) + (reg), (val))
    261   1.1  jmcneill 
    262   1.4  jmcneill #define	VSU_READ(sc, reg)				\
    263   1.4  jmcneill 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, VSU_BASE + (reg))
    264   1.4  jmcneill #define	VSU_WRITE(sc, reg, val)			\
    265   1.4  jmcneill 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, VSU_BASE + (reg), (val))
    266   1.4  jmcneill 
    267   1.4  jmcneill #define	CSC_READ(sc, n, reg)				\
    268   1.4  jmcneill 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, CSC_BASE(n) + (reg))
    269   1.4  jmcneill #define	CSC_WRITE(sc, n, reg, val)			\
    270   1.4  jmcneill 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, CSC_BASE(n) + (reg), (val))
    271   1.4  jmcneill 
    272   1.3  jmcneill #define	to_sunxi_mixer_crtc(x)		container_of(x, struct sunxi_mixer_crtc, base)
    273   1.6  jmcneill #define	to_sunxi_mixer_plane(x)	container_of(x, struct sunxi_mixer_plane, base)
    274   1.1  jmcneill 
    275   1.5  jmcneill static int
    276   1.5  jmcneill sunxi_mixer_mode_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb,
    277   1.5  jmcneill     int x, int y, int atomic)
    278   1.5  jmcneill {
    279   1.5  jmcneill 	struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc);
    280   1.5  jmcneill 	struct sunxi_mixer_softc * const sc = mixer_crtc->sc;
    281   1.5  jmcneill 	struct sunxi_drm_framebuffer *sfb = atomic?
    282   1.5  jmcneill 	    to_sunxi_drm_framebuffer(fb) :
    283   1.5  jmcneill 	    to_sunxi_drm_framebuffer(crtc->primary->fb);
    284   1.6  jmcneill 	uint32_t val;
    285   1.5  jmcneill 
    286   1.5  jmcneill 	uint64_t paddr = (uint64_t)sfb->obj->dmamap->dm_segs[0].ds_addr;
    287   1.5  jmcneill 
    288   1.9  jmcneill 	paddr += y * sfb->base.pitches[0];
    289  1.17  riastrad 	paddr += x * sfb->base.format->cpp[0];
    290   1.9  jmcneill 
    291   1.5  jmcneill 	uint32_t haddr = (paddr >> 32) & OVL_UI_TOP_HADD_LAYER0;
    292   1.5  jmcneill 	uint32_t laddr = paddr & 0xffffffff;
    293   1.5  jmcneill 
    294   1.8  jmcneill 	/* Set UI overlay line size */
    295   1.8  jmcneill 	OVL_UI_WRITE(sc, 0, OVL_UI_PITCH(0), sfb->base.pitches[0]);
    296   1.8  jmcneill 
    297   1.5  jmcneill 	/* Framebuffer start address */
    298   1.6  jmcneill 	val = OVL_UI_READ(sc, 0, OVL_UI_TOP_HADD);
    299   1.6  jmcneill 	val &= ~OVL_UI_TOP_HADD_LAYER0;
    300   1.6  jmcneill 	val |= __SHIFTIN(haddr, OVL_UI_TOP_HADD_LAYER0);
    301   1.6  jmcneill 	OVL_UI_WRITE(sc, 0, OVL_UI_TOP_HADD, val);
    302   1.6  jmcneill 	OVL_UI_WRITE(sc, 0, OVL_UI_TOP_LADD(0), laddr);
    303   1.5  jmcneill 
    304   1.5  jmcneill 	return 0;
    305   1.5  jmcneill }
    306   1.5  jmcneill 
    307   1.1  jmcneill static void
    308   1.1  jmcneill sunxi_mixer_destroy(struct drm_crtc *crtc)
    309   1.1  jmcneill {
    310   1.1  jmcneill 	drm_crtc_cleanup(crtc);
    311   1.1  jmcneill }
    312   1.1  jmcneill 
    313   1.5  jmcneill static int
    314   1.5  jmcneill sunxi_mixer_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
    315  1.17  riastrad     struct drm_pending_vblank_event *event, uint32_t flags,
    316  1.17  riastrad     struct drm_modeset_acquire_ctx *ctx)
    317   1.5  jmcneill {
    318   1.5  jmcneill 	struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc);
    319   1.5  jmcneill 	struct sunxi_mixer_softc * const sc = mixer_crtc->sc;
    320   1.5  jmcneill 	unsigned long irqflags;
    321   1.5  jmcneill 
    322   1.5  jmcneill 	drm_crtc_wait_one_vblank(crtc);
    323   1.5  jmcneill 
    324   1.5  jmcneill 	sunxi_mixer_mode_do_set_base(crtc, fb, 0, 0, true);
    325   1.5  jmcneill 
    326   1.5  jmcneill 	/* Commit settings */
    327   1.5  jmcneill 	GLB_WRITE(sc, GLB_DBUFFER, GLB_DBUFFER_DOUBLE_BUFFER_RDY);
    328   1.5  jmcneill 
    329   1.5  jmcneill 	if (event) {
    330   1.5  jmcneill 		spin_lock_irqsave(&crtc->dev->event_lock, irqflags);
    331  1.17  riastrad 		drm_crtc_send_vblank_event(crtc, event);
    332   1.5  jmcneill 		spin_unlock_irqrestore(&crtc->dev->event_lock, irqflags);
    333   1.5  jmcneill 	}
    334   1.5  jmcneill 
    335   1.5  jmcneill 	return 0;
    336   1.5  jmcneill }
    337   1.5  jmcneill 
    338   1.6  jmcneill static int
    339   1.6  jmcneill sunxi_mixer_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
    340   1.6  jmcneill     uint32_t handle, uint32_t width, uint32_t height)
    341   1.6  jmcneill {
    342   1.6  jmcneill 	struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc);
    343   1.6  jmcneill 	struct sunxi_mixer_softc * const sc = mixer_crtc->sc;
    344   1.6  jmcneill 	struct drm_gem_object *gem_obj = NULL;
    345   1.6  jmcneill 	struct drm_gem_cma_object *obj;
    346   1.6  jmcneill 	uint32_t val;
    347   1.6  jmcneill 	int error;
    348   1.6  jmcneill 
    349   1.6  jmcneill 	/* Only mixers with more than one UI layer can support hardware cursors */
    350   1.6  jmcneill 	if (sc->sc_ovl_ui_count <= 1)
    351   1.6  jmcneill 		return -EINVAL;
    352   1.6  jmcneill 
    353   1.6  jmcneill 	if (handle == 0) {
    354   1.6  jmcneill 		val = BLD_READ(sc, BLD_FILL_COLOR_CTL);
    355   1.6  jmcneill 		val &= ~BLD_FILL_COLOR_CTL_P2_EN;
    356   1.6  jmcneill 		val |= BLD_FILL_COLOR_CTL_P2_FCEN;
    357   1.6  jmcneill 		BLD_WRITE(sc, BLD_FILL_COLOR_CTL, val);
    358   1.6  jmcneill 
    359   1.6  jmcneill 		error = 0;
    360   1.6  jmcneill 		goto done;
    361   1.6  jmcneill 	}
    362   1.6  jmcneill 
    363   1.6  jmcneill 	/* Arbitrary limits, the hardware layer can do 8192x8192 */
    364   1.6  jmcneill 	if (width > MIXER_CURSOR_MAXWIDTH || height > MIXER_CURSOR_MAXHEIGHT) {
    365   1.6  jmcneill 		DRM_ERROR("Cursor dimension %ux%u not supported\n", width, height);
    366   1.6  jmcneill 		error = -EINVAL;
    367   1.6  jmcneill 		goto done;
    368   1.6  jmcneill 	}
    369   1.6  jmcneill 
    370  1.17  riastrad 	gem_obj = drm_gem_object_lookup(file_priv, handle);
    371   1.6  jmcneill 	if (gem_obj == NULL) {
    372   1.6  jmcneill 		DRM_ERROR("Cannot find cursor object %#x for crtc %d\n",
    373   1.6  jmcneill 		    handle, drm_crtc_index(crtc));
    374   1.6  jmcneill 		error = -ENOENT;
    375   1.6  jmcneill 		goto done;
    376   1.6  jmcneill 	}
    377   1.6  jmcneill 	obj = to_drm_gem_cma_obj(gem_obj);
    378   1.6  jmcneill 
    379   1.6  jmcneill 	if (obj->base.size < width * height * 4) {
    380   1.6  jmcneill 		DRM_ERROR("Cursor buffer is too small\n");
    381   1.6  jmcneill 		error = -ENOMEM;
    382   1.6  jmcneill 		goto done;
    383   1.6  jmcneill 	}
    384   1.6  jmcneill 
    385   1.6  jmcneill 	uint64_t paddr = (uint64_t)obj->dmamap->dm_segs[0].ds_addr;
    386   1.6  jmcneill 	uint32_t haddr = (paddr >> 32) & OVL_UI_TOP_HADD_LAYER0;
    387   1.6  jmcneill 	uint32_t laddr = paddr & 0xffffffff;
    388   1.6  jmcneill 
    389   1.6  jmcneill 	/* Framebuffer start address */
    390   1.6  jmcneill 	val = OVL_UI_READ(sc, 1, OVL_UI_TOP_HADD);
    391   1.6  jmcneill 	val &= ~OVL_UI_TOP_HADD_LAYER0;
    392   1.6  jmcneill 	val |= __SHIFTIN(haddr, OVL_UI_TOP_HADD_LAYER0);
    393   1.6  jmcneill 	OVL_UI_WRITE(sc, 1, OVL_UI_TOP_HADD, val);
    394   1.6  jmcneill 	OVL_UI_WRITE(sc, 1, OVL_UI_TOP_LADD(0), laddr);
    395   1.6  jmcneill 
    396   1.6  jmcneill 	const uint32_t size = ((height - 1) << 16) | (width - 1);
    397   1.6  jmcneill 	const uint32_t offset = (crtc->cursor_y << 16) | crtc->cursor_x;
    398   1.6  jmcneill 	const uint32_t crtc_size = ((crtc->primary->fb->height - 1) << 16) |
    399   1.6  jmcneill 	    (crtc->primary->fb->width - 1);
    400   1.6  jmcneill 
    401   1.6  jmcneill 	/* Enable cursor in ARGB8888 mode */
    402   1.6  jmcneill 	val = OVL_UI_ATTR_CTL_LAY_EN |
    403   1.6  jmcneill 	      __SHIFTIN(OVL_UI_ATTR_CTL_LAY_FBFMT_ARGB_8888, OVL_UI_ATTR_CTL_LAY_FBFMT);
    404   1.6  jmcneill 	OVL_UI_WRITE(sc, 1, OVL_UI_ATTR_CTL(0), val);
    405   1.6  jmcneill 	/* Set UI overlay layer size */
    406   1.6  jmcneill 	OVL_UI_WRITE(sc, 1, OVL_UI_MBSIZE(0), size);
    407   1.6  jmcneill 	/* Set UI overlay offset */
    408   1.6  jmcneill 	OVL_UI_WRITE(sc, 1, OVL_UI_COOR(0), offset);
    409   1.6  jmcneill 	/* Set UI overlay line size */
    410  1.10  jmcneill 	OVL_UI_WRITE(sc, 1, OVL_UI_PITCH(0), width * 4);
    411   1.6  jmcneill 	/* Set UI overlay window size */
    412   1.6  jmcneill 	OVL_UI_WRITE(sc, 1, OVL_UI_SIZE, crtc_size);
    413   1.6  jmcneill 
    414   1.6  jmcneill 	/* Set blender 2 input size */
    415   1.6  jmcneill 	BLD_WRITE(sc, BLD_CH_ISIZE(2), crtc_size);
    416   1.6  jmcneill 	/* Set blender 2 offset */
    417   1.6  jmcneill 	BLD_WRITE(sc, BLD_CH_OFFSET(2), 0);
    418   1.6  jmcneill 	/* Route channel 2 to pipe 2 */
    419   1.6  jmcneill 	val = BLD_READ(sc, BLD_CH_RTCTL);
    420   1.6  jmcneill 	val &= ~BLD_CH_RTCTL_P2;
    421   1.6  jmcneill 	val |= __SHIFTIN(2, BLD_CH_RTCTL_P2);
    422   1.6  jmcneill 	BLD_WRITE(sc, BLD_CH_RTCTL, val);
    423   1.6  jmcneill 
    424   1.6  jmcneill 	/* Enable pipe 2 */
    425   1.6  jmcneill 	val = BLD_READ(sc, BLD_FILL_COLOR_CTL);
    426   1.6  jmcneill 	val |= BLD_FILL_COLOR_CTL_P2_EN;
    427   1.6  jmcneill 	val &= ~BLD_FILL_COLOR_CTL_P2_FCEN;
    428   1.6  jmcneill 	BLD_WRITE(sc, BLD_FILL_COLOR_CTL, val);
    429   1.6  jmcneill 
    430   1.6  jmcneill 	error = 0;
    431   1.6  jmcneill 
    432   1.6  jmcneill done:
    433   1.6  jmcneill 	if (error == 0) {
    434   1.6  jmcneill 		/* Commit settings */
    435   1.6  jmcneill 		GLB_WRITE(sc, GLB_DBUFFER, GLB_DBUFFER_DOUBLE_BUFFER_RDY);
    436   1.6  jmcneill 	}
    437   1.6  jmcneill 
    438   1.6  jmcneill 	if (gem_obj != NULL)
    439  1.17  riastrad 		drm_gem_object_put_unlocked(gem_obj);
    440   1.6  jmcneill 
    441   1.6  jmcneill 	return error;
    442   1.6  jmcneill }
    443   1.6  jmcneill 
    444   1.6  jmcneill static int
    445   1.6  jmcneill sunxi_mixer_cursor_move(struct drm_crtc *crtc, int x, int y)
    446   1.6  jmcneill {
    447   1.6  jmcneill 	struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc);
    448   1.6  jmcneill 	struct sunxi_mixer_softc * const sc = mixer_crtc->sc;
    449   1.6  jmcneill 
    450   1.6  jmcneill 	crtc->cursor_x = x & 0xffff;
    451   1.6  jmcneill 	crtc->cursor_y = y & 0xffff;
    452   1.6  jmcneill 
    453   1.6  jmcneill 	const uint32_t offset = (crtc->cursor_y << 16) | crtc->cursor_x;
    454   1.6  jmcneill 
    455   1.6  jmcneill 	OVL_UI_WRITE(sc, 1, OVL_UI_COOR(0), offset);
    456   1.6  jmcneill 
    457   1.6  jmcneill 	/* Commit settings */
    458   1.6  jmcneill 	GLB_WRITE(sc, GLB_DBUFFER, GLB_DBUFFER_DOUBLE_BUFFER_RDY);
    459   1.6  jmcneill 
    460   1.6  jmcneill 	return 0;
    461   1.6  jmcneill }
    462   1.6  jmcneill 
    463   1.7  jmcneill static const struct drm_crtc_funcs sunxi_mixer0_crtc_funcs = {
    464   1.1  jmcneill 	.set_config = drm_crtc_helper_set_config,
    465   1.6  jmcneill 	.destroy = sunxi_mixer_destroy,
    466   1.5  jmcneill 	.page_flip = sunxi_mixer_page_flip,
    467   1.6  jmcneill 	.cursor_set = sunxi_mixer_cursor_set,
    468   1.6  jmcneill 	.cursor_move = sunxi_mixer_cursor_move,
    469   1.1  jmcneill };
    470   1.1  jmcneill 
    471   1.7  jmcneill static const struct drm_crtc_funcs sunxi_mixer1_crtc_funcs = {
    472   1.7  jmcneill 	.set_config = drm_crtc_helper_set_config,
    473   1.7  jmcneill 	.destroy = sunxi_mixer_destroy,
    474   1.7  jmcneill 	.page_flip = sunxi_mixer_page_flip,
    475   1.7  jmcneill };
    476   1.7  jmcneill 
    477   1.1  jmcneill static void
    478   1.1  jmcneill sunxi_mixer_dpms(struct drm_crtc *crtc, int mode)
    479   1.1  jmcneill {
    480   1.1  jmcneill }
    481   1.1  jmcneill 
    482   1.1  jmcneill static bool
    483   1.1  jmcneill sunxi_mixer_mode_fixup(struct drm_crtc *crtc,
    484   1.1  jmcneill     const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode)
    485   1.1  jmcneill {
    486   1.1  jmcneill 	return true;
    487   1.1  jmcneill }
    488   1.1  jmcneill 
    489   1.1  jmcneill static int
    490   1.1  jmcneill sunxi_mixer_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
    491   1.1  jmcneill     struct drm_display_mode *adjusted_mode, int x, int y,
    492   1.1  jmcneill     struct drm_framebuffer *old_fb)
    493   1.1  jmcneill {
    494   1.1  jmcneill 	struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc);
    495   1.1  jmcneill 	struct sunxi_mixer_softc * const sc = mixer_crtc->sc;
    496   1.1  jmcneill 	uint32_t val;
    497   1.6  jmcneill 	u_int fbfmt;
    498   1.1  jmcneill 
    499   1.1  jmcneill 	const uint32_t size = ((adjusted_mode->vdisplay - 1) << 16) |
    500   1.1  jmcneill 			      (adjusted_mode->hdisplay - 1);
    501   1.1  jmcneill 
    502   1.1  jmcneill 	/* Set global size */
    503   1.1  jmcneill 	GLB_WRITE(sc, GLB_SIZE, size);
    504   1.1  jmcneill 
    505   1.1  jmcneill 	/* Enable pipe 0 */
    506   1.3  jmcneill 	val = BLD_READ(sc, BLD_FILL_COLOR_CTL);
    507   1.3  jmcneill 	val |= BLD_FILL_COLOR_CTL_P0_EN;
    508   1.3  jmcneill 	BLD_WRITE(sc, BLD_FILL_COLOR_CTL, val);
    509   1.1  jmcneill 
    510   1.1  jmcneill 	/* Set blender 0 input size */
    511   1.1  jmcneill 	BLD_WRITE(sc, BLD_CH_ISIZE(0), size);
    512   1.1  jmcneill 	/* Set blender 0 offset */
    513   1.9  jmcneill 	BLD_WRITE(sc, BLD_CH_OFFSET(0), 0);
    514   1.1  jmcneill 	/* Route channel 1 to pipe 0 */
    515   1.3  jmcneill 	val = BLD_READ(sc, BLD_CH_RTCTL);
    516   1.3  jmcneill 	val &= ~BLD_CH_RTCTL_P0;
    517   1.3  jmcneill 	val |= __SHIFTIN(1, BLD_CH_RTCTL_P0);
    518   1.3  jmcneill 	BLD_WRITE(sc, BLD_CH_RTCTL, val);
    519   1.1  jmcneill 	/* Set blender output size */
    520   1.1  jmcneill 	BLD_WRITE(sc, BLD_SIZE, size);
    521   1.1  jmcneill 
    522   1.6  jmcneill 	/* Enable UI overlay */
    523  1.17  riastrad 	if (crtc->primary->fb->format->format == DRM_FORMAT_XRGB8888)
    524   1.6  jmcneill 		fbfmt = OVL_UI_ATTR_CTL_LAY_FBFMT_XRGB_8888;
    525   1.6  jmcneill 	else
    526   1.6  jmcneill 		fbfmt = OVL_UI_ATTR_CTL_LAY_FBFMT_ARGB_8888;
    527   1.6  jmcneill 	val = OVL_UI_ATTR_CTL_LAY_EN | __SHIFTIN(fbfmt, OVL_UI_ATTR_CTL_LAY_FBFMT);
    528   1.6  jmcneill 	OVL_UI_WRITE(sc, 0, OVL_UI_ATTR_CTL(0), val);
    529   1.1  jmcneill 	/* Set UI overlay layer size */
    530   1.6  jmcneill 	OVL_UI_WRITE(sc, 0, OVL_UI_MBSIZE(0), size);
    531   1.1  jmcneill 	/* Set UI overlay offset */
    532   1.9  jmcneill 	OVL_UI_WRITE(sc, 0, OVL_UI_COOR(0), 0);
    533   1.1  jmcneill 	/* Set UI overlay window size */
    534   1.6  jmcneill 	OVL_UI_WRITE(sc, 0, OVL_UI_SIZE, size);
    535   1.1  jmcneill 
    536   1.1  jmcneill 	sunxi_mixer_mode_do_set_base(crtc, old_fb, x, y, 0);
    537   1.1  jmcneill 
    538   1.1  jmcneill 	return 0;
    539   1.1  jmcneill }
    540   1.1  jmcneill 
    541   1.1  jmcneill static int
    542   1.1  jmcneill sunxi_mixer_mode_set_base(struct drm_crtc *crtc, int x, int y,
    543   1.1  jmcneill     struct drm_framebuffer *old_fb)
    544   1.1  jmcneill {
    545   1.1  jmcneill 	struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc);
    546   1.1  jmcneill 	struct sunxi_mixer_softc * const sc = mixer_crtc->sc;
    547   1.1  jmcneill 
    548   1.1  jmcneill 	sunxi_mixer_mode_do_set_base(crtc, old_fb, x, y, 0);
    549   1.1  jmcneill 
    550   1.1  jmcneill 	/* Commit settings */
    551   1.1  jmcneill 	GLB_WRITE(sc, GLB_DBUFFER, GLB_DBUFFER_DOUBLE_BUFFER_RDY);
    552   1.1  jmcneill 
    553   1.1  jmcneill 	return 0;
    554   1.1  jmcneill }
    555   1.1  jmcneill 
    556   1.1  jmcneill static int
    557   1.1  jmcneill sunxi_mixer_mode_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
    558   1.1  jmcneill     int x, int y, enum mode_set_atomic state)
    559   1.1  jmcneill {
    560   1.1  jmcneill 	struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc);
    561   1.1  jmcneill 	struct sunxi_mixer_softc * const sc = mixer_crtc->sc;
    562   1.1  jmcneill 
    563   1.1  jmcneill 	sunxi_mixer_mode_do_set_base(crtc, fb, x, y, 1);
    564   1.1  jmcneill 
    565   1.1  jmcneill 	/* Commit settings */
    566   1.1  jmcneill 	GLB_WRITE(sc, GLB_DBUFFER, GLB_DBUFFER_DOUBLE_BUFFER_RDY);
    567   1.1  jmcneill 
    568   1.1  jmcneill 	return 0;
    569   1.1  jmcneill }
    570   1.1  jmcneill 
    571   1.1  jmcneill static void
    572   1.1  jmcneill sunxi_mixer_disable(struct drm_crtc *crtc)
    573   1.1  jmcneill {
    574   1.1  jmcneill }
    575   1.1  jmcneill 
    576   1.1  jmcneill static void
    577   1.1  jmcneill sunxi_mixer_prepare(struct drm_crtc *crtc)
    578   1.1  jmcneill {
    579   1.1  jmcneill 	struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc);
    580   1.1  jmcneill 	struct sunxi_mixer_softc * const sc = mixer_crtc->sc;
    581   1.1  jmcneill 
    582   1.1  jmcneill 	/* RT enable */
    583   1.1  jmcneill 	GLB_WRITE(sc, GLB_CTL, GLB_CTL_EN);
    584   1.1  jmcneill }
    585   1.1  jmcneill 
    586   1.1  jmcneill static void
    587   1.1  jmcneill sunxi_mixer_commit(struct drm_crtc *crtc)
    588   1.1  jmcneill {
    589   1.1  jmcneill 	struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc);
    590   1.1  jmcneill 	struct sunxi_mixer_softc * const sc = mixer_crtc->sc;
    591   1.1  jmcneill 
    592   1.1  jmcneill 	/* Commit settings */
    593   1.1  jmcneill 	GLB_WRITE(sc, GLB_DBUFFER, GLB_DBUFFER_DOUBLE_BUFFER_RDY);
    594   1.1  jmcneill }
    595   1.1  jmcneill 
    596   1.1  jmcneill static const struct drm_crtc_helper_funcs sunxi_mixer_crtc_helper_funcs = {
    597   1.1  jmcneill 	.dpms = sunxi_mixer_dpms,
    598   1.1  jmcneill 	.mode_fixup = sunxi_mixer_mode_fixup,
    599   1.1  jmcneill 	.mode_set = sunxi_mixer_mode_set,
    600   1.1  jmcneill 	.mode_set_base = sunxi_mixer_mode_set_base,
    601   1.1  jmcneill 	.mode_set_base_atomic = sunxi_mixer_mode_set_base_atomic,
    602   1.1  jmcneill 	.disable = sunxi_mixer_disable,
    603   1.1  jmcneill 	.prepare = sunxi_mixer_prepare,
    604   1.1  jmcneill 	.commit = sunxi_mixer_commit,
    605   1.1  jmcneill };
    606   1.1  jmcneill 
    607   1.3  jmcneill static void
    608   1.3  jmcneill sunxi_mixer_overlay_destroy(struct drm_plane *plane)
    609   1.3  jmcneill {
    610   1.3  jmcneill }
    611   1.3  jmcneill 
    612   1.3  jmcneill static bool
    613   1.4  jmcneill sunxi_mixer_overlay_rgb(uint32_t drm_format)
    614   1.3  jmcneill {
    615   1.3  jmcneill 	switch (drm_format) {
    616   1.6  jmcneill 	case DRM_FORMAT_ARGB8888:
    617   1.3  jmcneill 	case DRM_FORMAT_XRGB8888:
    618   1.3  jmcneill 		return true;
    619   1.3  jmcneill 	default:
    620   1.3  jmcneill 		return false;
    621   1.3  jmcneill 	}
    622   1.3  jmcneill }
    623   1.3  jmcneill 
    624   1.3  jmcneill static u_int
    625   1.3  jmcneill sunxi_mixer_overlay_format(uint32_t drm_format)
    626   1.3  jmcneill {
    627   1.3  jmcneill 	switch (drm_format) {
    628   1.6  jmcneill 	case DRM_FORMAT_ARGB8888:	return OVL_V_ATTCTL_LAY_FBFMT_ARGB_8888;
    629   1.3  jmcneill 	case DRM_FORMAT_XRGB8888:	return OVL_V_ATTCTL_LAY_FBFMT_XRGB_8888;
    630   1.3  jmcneill 	case DRM_FORMAT_VYUY:		return OVL_V_ATTCTL_LAY_FBFMT_VYUY;
    631   1.3  jmcneill 	case DRM_FORMAT_YVYU:		return OVL_V_ATTCTL_LAY_FBFMT_YVYU;
    632   1.3  jmcneill 	case DRM_FORMAT_UYVY:		return OVL_V_ATTCTL_LAY_FBFMT_UYVY;
    633   1.3  jmcneill 	case DRM_FORMAT_YUYV:		return OVL_V_ATTCTL_LAY_FBFMT_YUYV;
    634   1.3  jmcneill 	case DRM_FORMAT_YUV422:		return OVL_V_ATTCTL_LAY_FBFMT_YUV422;
    635   1.3  jmcneill 	case DRM_FORMAT_YUV420:		return OVL_V_ATTCTL_LAY_FBFMT_YUV420;
    636   1.3  jmcneill 	case DRM_FORMAT_YUV411:		return OVL_V_ATTCTL_LAY_FBFMT_YUV411;
    637   1.3  jmcneill 	default:			return 0;	/* shouldn't happen */
    638   1.3  jmcneill 	}
    639   1.3  jmcneill }
    640   1.3  jmcneill 
    641   1.4  jmcneill static const uint32_t lan3coefftab32_left[512] = {
    642   1.4  jmcneill 	0x40000000, 0x40fe0000, 0x3ffd0100, 0x3efc0100,
    643   1.4  jmcneill 	0x3efb0100, 0x3dfa0200, 0x3cf90200, 0x3bf80200,
    644   1.4  jmcneill 	0x39f70200, 0x37f70200, 0x35f70200, 0x33f70200,
    645   1.4  jmcneill 	0x31f70200, 0x2ef70200, 0x2cf70200, 0x2af70200,
    646   1.4  jmcneill 	0x27f70200, 0x24f80100, 0x22f80100, 0x1ef90100,
    647   1.4  jmcneill 	0x1cf90100, 0x19fa0100, 0x17fa0100, 0x14fb0100,
    648   1.4  jmcneill 	0x11fc0000, 0x0ffc0000, 0x0cfd0000, 0x0afd0000,
    649   1.4  jmcneill 	0x08fe0000, 0x05ff0000, 0x03ff0000, 0x02000000,
    650   1.4  jmcneill 
    651   1.4  jmcneill 	0x40000000, 0x40fe0000, 0x3ffd0100, 0x3efc0100,
    652   1.4  jmcneill 	0x3efb0100, 0x3dfa0200, 0x3cf90200, 0x3bf80200,
    653   1.4  jmcneill 	0x39f70200, 0x37f70200, 0x35f70200, 0x33f70200,
    654   1.4  jmcneill 	0x31f70200, 0x2ef70200, 0x2cf70200, 0x2af70200,
    655   1.4  jmcneill 	0x27f70200, 0x24f80100, 0x22f80100, 0x1ef90100,
    656   1.4  jmcneill 	0x1cf90100, 0x19fa0100, 0x17fa0100, 0x14fb0100,
    657   1.4  jmcneill 	0x11fc0000, 0x0ffc0000, 0x0cfd0000, 0x0afd0000,
    658   1.4  jmcneill 	0x08fe0000, 0x05ff0000, 0x03ff0000, 0x02000000,
    659   1.4  jmcneill 
    660   1.4  jmcneill 	0x3806fc02, 0x3805fc02, 0x3803fd01, 0x3801fe01,
    661   1.4  jmcneill 	0x3700fe01, 0x35ffff01, 0x35fdff01, 0x34fc0001,
    662   1.4  jmcneill 	0x34fb0000, 0x33fa0000, 0x31fa0100, 0x2ff90100,
    663   1.4  jmcneill 	0x2df80200, 0x2bf80200, 0x2af70200, 0x28f70200,
    664   1.4  jmcneill 	0x27f70200, 0x24f70300, 0x22f70300, 0x1ff70300,
    665   1.4  jmcneill 	0x1ef70300, 0x1cf70300, 0x1af70300, 0x18f70300,
    666   1.4  jmcneill 	0x16f80300, 0x13f80300, 0x11f90300, 0x0ef90300,
    667   1.4  jmcneill 	0x0efa0200, 0x0cfa0200, 0x0afb0200, 0x08fb0200,
    668   1.4  jmcneill 
    669   1.4  jmcneill 	0x320bfa02, 0x3309fa02, 0x3208fb02, 0x3206fb02,
    670   1.4  jmcneill 	0x3205fb02, 0x3104fc02, 0x3102fc01, 0x3001fd01,
    671   1.4  jmcneill 	0x3000fd01, 0x2ffffd01, 0x2efefe01, 0x2dfdfe01,
    672   1.4  jmcneill 	0x2bfcff01, 0x29fcff01, 0x28fbff01, 0x27fa0001,
    673   1.4  jmcneill 	0x26fa0000, 0x24f90000, 0x22f90100, 0x20f90100,
    674   1.4  jmcneill 	0x1ff80100, 0x1ef80100, 0x1cf80100, 0x1af80200,
    675   1.4  jmcneill 	0x18f80200, 0x17f80200, 0x15f80200, 0x12f80200,
    676   1.4  jmcneill 	0x11f90200, 0x0ff90200, 0x0df90200, 0x0cfa0200,
    677   1.4  jmcneill 
    678   1.4  jmcneill 	0x2e0efa01, 0x2f0dfa01, 0x2f0bfa01, 0x2e0afa01,
    679   1.4  jmcneill 	0x2e09fa01, 0x2e07fb01, 0x2d06fb01, 0x2d05fb01,
    680   1.4  jmcneill 	0x2c04fb01, 0x2b03fc01, 0x2a02fc01, 0x2a01fc01,
    681   1.4  jmcneill 	0x2800fd01, 0x28fffd01, 0x26fefd01, 0x25fefe01,
    682   1.4  jmcneill 	0x24fdfe01, 0x23fcfe01, 0x21fcff01, 0x20fbff01,
    683   1.4  jmcneill 	0x1efbff01, 0x1efbff00, 0x1cfa0000, 0x1bfa0000,
    684   1.4  jmcneill 	0x19fa0000, 0x18fa0000, 0x17f90000, 0x15f90100,
    685   1.4  jmcneill 	0x14f90100, 0x12f90100, 0x11f90100, 0x0ff90100,
    686   1.4  jmcneill 
    687   1.4  jmcneill 	0x2b10fa00, 0x2b0ffa00, 0x2b0efa00, 0x2b0cfa00,
    688   1.4  jmcneill 	0x2b0bfa00, 0x2a0afb01, 0x2a09fb01, 0x2908fb01,
    689   1.4  jmcneill 	0x2807fb01, 0x2806fb01, 0x2805fb01, 0x2604fc01,
    690   1.4  jmcneill 	0x2503fc01, 0x2502fc01, 0x2401fc01, 0x2301fc01,
    691   1.4  jmcneill 	0x2100fd01, 0x21fffd01, 0x21fffd01, 0x20fefd01,
    692   1.4  jmcneill 	0x1dfefe01, 0x1cfdfe01, 0x1cfdfe00, 0x1bfcfe00,
    693   1.4  jmcneill 	0x19fcff00, 0x19fbff00, 0x17fbff00, 0x16fbff00,
    694   1.4  jmcneill 	0x15fbff00, 0x14fb0000, 0x13fa0000, 0x11fa0000,
    695   1.4  jmcneill 
    696   1.4  jmcneill 	0x2811fcff, 0x2810fcff, 0x280ffbff, 0x280efbff,
    697   1.4  jmcneill 	0x270dfb00, 0x270cfb00, 0x270bfb00, 0x260afb00,
    698   1.4  jmcneill 	0x2609fb00, 0x2508fb00, 0x2507fb00, 0x2407fb00,
    699   1.4  jmcneill 	0x2406fc00, 0x2305fc00, 0x2204fc00, 0x2203fc00,
    700   1.4  jmcneill 	0x2103fc00, 0x2002fc00, 0x1f01fd00, 0x1e01fd00,
    701   1.4  jmcneill 	0x1d00fd00, 0x1dfffd00, 0x1cfffd00, 0x1bfefd00,
    702   1.4  jmcneill 	0x1afefe00, 0x19fefe00, 0x18fdfe00, 0x17fdfe00,
    703   1.4  jmcneill 	0x16fdfe00, 0x15fcff00, 0x13fcff00, 0x12fcff00,
    704   1.4  jmcneill 
    705   1.4  jmcneill 	0x2512fdfe, 0x2511fdff, 0x2410fdff, 0x240ffdff,
    706   1.4  jmcneill 	0x240efcff, 0x240dfcff, 0x240dfcff, 0x240cfcff,
    707   1.4  jmcneill 	0x230bfcff, 0x230afc00, 0x2209fc00, 0x2108fc00,
    708   1.4  jmcneill 	0x2108fc00, 0x2007fc00, 0x2006fc00, 0x2005fc00,
    709   1.4  jmcneill 	0x1f05fc00, 0x1e04fc00, 0x1e03fc00, 0x1c03fd00,
    710   1.4  jmcneill 	0x1c02fd00, 0x1b02fd00, 0x1b01fd00, 0x1a00fd00,
    711   1.4  jmcneill 	0x1900fd00, 0x1800fd00, 0x17fffe00, 0x16fffe00,
    712   1.4  jmcneill 	0x16fefe00, 0x14fefe00, 0x13fefe00, 0x13fdfe00,
    713   1.4  jmcneill 
    714   1.4  jmcneill 	0x2212fffe, 0x2211fefe, 0x2211fefe, 0x2110fefe,
    715   1.4  jmcneill 	0x210ffeff, 0x220efdff, 0x210dfdff, 0x210dfdff,
    716   1.4  jmcneill 	0x210cfdff, 0x210bfdff, 0x200afdff, 0x200afdff,
    717   1.4  jmcneill 	0x1f09fdff, 0x1f08fdff, 0x1d08fd00, 0x1c07fd00,
    718   1.4  jmcneill 	0x1d06fd00, 0x1b06fd00, 0x1b05fd00, 0x1c04fd00,
    719   1.4  jmcneill 	0x1b04fd00, 0x1a03fd00, 0x1a03fd00, 0x1902fd00,
    720   1.4  jmcneill 	0x1802fd00, 0x1801fd00, 0x1701fd00, 0x1600fd00,
    721   1.4  jmcneill 	0x1400fe00, 0x1400fe00, 0x14fffe00, 0x13fffe00,
    722   1.4  jmcneill 
    723   1.4  jmcneill 	0x201200fe, 0x201100fe, 0x1f11fffe, 0x2010fffe,
    724   1.4  jmcneill 	0x1f0ffffe, 0x1e0ffffe, 0x1f0efeff, 0x1f0dfeff,
    725   1.4  jmcneill 	0x1f0dfeff, 0x1e0cfeff, 0x1e0bfeff, 0x1d0bfeff,
    726   1.4  jmcneill 	0x1d0afeff, 0x1d09fdff, 0x1d09fdff, 0x1c08fdff,
    727   1.4  jmcneill 	0x1c07fdff, 0x1b07fd00, 0x1b06fd00, 0x1a06fd00,
    728   1.4  jmcneill 	0x1a05fd00, 0x1805fd00, 0x1904fd00, 0x1804fd00,
    729   1.4  jmcneill 	0x1703fd00, 0x1703fd00, 0x1602fe00, 0x1502fe00,
    730   1.4  jmcneill 	0x1501fe00, 0x1401fe00, 0x1301fe00, 0x1300fe00,
    731   1.4  jmcneill 
    732   1.4  jmcneill 	0x1c1202fe, 0x1c1102fe, 0x1b1102fe, 0x1c1001fe,
    733   1.4  jmcneill 	0x1b1001fe, 0x1b0f01ff, 0x1b0e00ff, 0x1b0e00ff,
    734   1.4  jmcneill 	0x1b0d00ff, 0x1a0d00ff, 0x1a0c00ff, 0x1a0cffff,
    735   1.4  jmcneill 	0x1a0bffff, 0x1a0bffff, 0x1a0affff, 0x180affff,
    736   1.4  jmcneill 	0x1909ffff, 0x1809ffff, 0x1808ffff, 0x1808feff,
    737   1.4  jmcneill 	0x1807feff, 0x1707fe00, 0x1606fe00, 0x1506fe00,
    738   1.4  jmcneill 	0x1605fe00, 0x1505fe00, 0x1504fe00, 0x1304fe00,
    739   1.4  jmcneill 	0x1304fe00, 0x1303fe00, 0x1203fe00, 0x1203fe00,
    740   1.4  jmcneill 
    741   1.4  jmcneill 	0x181104ff, 0x191103ff, 0x191003ff, 0x181003ff,
    742   1.4  jmcneill 	0x180f03ff, 0x190f02ff, 0x190e02ff, 0x180e02ff,
    743   1.4  jmcneill 	0x180d02ff, 0x180d01ff, 0x180d01ff, 0x180c01ff,
    744   1.4  jmcneill 	0x180c01ff, 0x180b00ff, 0x170b00ff, 0x170a00ff,
    745   1.4  jmcneill 	0x170a00ff, 0x170900ff, 0x160900ff, 0x160900ff,
    746   1.4  jmcneill 	0x1608ffff, 0x1508ffff, 0x1507ff00, 0x1507ff00,
    747   1.4  jmcneill 	0x1407ff00, 0x1306ff00, 0x1306ff00, 0x1305ff00,
    748   1.4  jmcneill 	0x1205ff00, 0x1105ff00, 0x1204ff00, 0x1104ff00,
    749   1.4  jmcneill 
    750   1.4  jmcneill 	0x171005ff, 0x171005ff, 0x171004ff, 0x170f04ff,
    751   1.4  jmcneill 	0x160f04ff, 0x170f03ff, 0x170e03ff, 0x160e03ff,
    752   1.4  jmcneill 	0x160d03ff, 0x160d02ff, 0x160d02ff, 0x160c02ff,
    753   1.4  jmcneill 	0x160c02ff, 0x160c02ff, 0x160b01ff, 0x150b01ff,
    754   1.4  jmcneill 	0x150a01ff, 0x150a01ff, 0x150a01ff, 0x140901ff,
    755   1.4  jmcneill 	0x14090000, 0x14090000, 0x14080000, 0x13080000,
    756   1.4  jmcneill 	0x13070000, 0x12070000, 0x12070000, 0x12060000,
    757   1.4  jmcneill 	0x11060000, 0x11060000, 0x11050000, 0x1105ff00,
    758   1.4  jmcneill 
    759   1.4  jmcneill 	0x14100600, 0x15100500, 0x150f0500, 0x150f0500,
    760   1.4  jmcneill 	0x140f0500, 0x150e0400, 0x140e0400, 0x130e0400,
    761   1.4  jmcneill 	0x140d0400, 0x150d0300, 0x130d0300, 0x140c0300,
    762   1.4  jmcneill 	0x140c0300, 0x140c0200, 0x140b0200, 0x130b0200,
    763   1.4  jmcneill 	0x120b0200, 0x130a0200, 0x130a0200, 0x130a0100,
    764   1.4  jmcneill 	0x13090100, 0x12090100, 0x11090100, 0x12080100,
    765   1.4  jmcneill 	0x11080100, 0x10080100, 0x11070100, 0x11070000,
    766   1.4  jmcneill 	0x10070000, 0x11060000, 0x10060000, 0x10060000,
    767   1.4  jmcneill 
    768   1.4  jmcneill 	0x140f0600, 0x140f0600, 0x130f0600, 0x140f0500,
    769   1.4  jmcneill 	0x140e0500, 0x130e0500, 0x130e0500, 0x140d0400,
    770   1.4  jmcneill 	0x140d0400, 0x130d0400, 0x120d0400, 0x130c0400,
    771   1.4  jmcneill 	0x130c0300, 0x130c0300, 0x130b0300, 0x130b0300,
    772   1.4  jmcneill 	0x110b0300, 0x130a0200, 0x120a0200, 0x120a0200,
    773   1.4  jmcneill 	0x120a0200, 0x12090200, 0x10090200, 0x11090100,
    774   1.4  jmcneill 	0x11080100, 0x11080100, 0x10080100, 0x10080100,
    775   1.4  jmcneill 	0x10070100, 0x10070100, 0x0f070100, 0x10060100,
    776   1.4  jmcneill 
    777   1.4  jmcneill 	0x120f0701, 0x130f0601, 0x130e0601, 0x130e0601,
    778   1.4  jmcneill 	0x120e0601, 0x130e0501, 0x130e0500, 0x130d0500,
    779   1.4  jmcneill 	0x120d0500, 0x120d0500, 0x130c0400, 0x130c0400,
    780   1.4  jmcneill 	0x120c0400, 0x110c0400, 0x120b0400, 0x120b0300,
    781   1.4  jmcneill 	0x120b0300, 0x120b0300, 0x120a0300, 0x110a0300,
    782   1.4  jmcneill 	0x110a0200, 0x11090200, 0x11090200, 0x10090200,
    783   1.4  jmcneill 	0x10090200, 0x10080200, 0x10080200, 0x10080100,
    784   1.4  jmcneill 	0x0f080100, 0x10070100, 0x0f070100, 0x0f070100
    785   1.4  jmcneill };
    786   1.4  jmcneill 
    787   1.4  jmcneill static const uint32_t lan3coefftab32_right[512] = {
    788   1.4  jmcneill 	0x00000000, 0x00000002, 0x0000ff04, 0x0000ff06,
    789   1.4  jmcneill 	0x0000fe08, 0x0000fd0a, 0x0000fd0c, 0x0000fc0f,
    790   1.4  jmcneill 	0x0000fc12, 0x0001fb14, 0x0001fa17, 0x0001fa19,
    791   1.4  jmcneill 	0x0001f91c, 0x0001f91f, 0x0001f822, 0x0001f824,
    792   1.4  jmcneill 	0x0002f727, 0x0002f72a, 0x0002f72c, 0x0002f72f,
    793   1.4  jmcneill 	0x0002f731, 0x0002f733, 0x0002f735, 0x0002f737,
    794   1.4  jmcneill 	0x0002f73a, 0x0002f83b, 0x0002f93c, 0x0002fa3d,
    795   1.4  jmcneill 	0x0001fb3e, 0x0001fc3f, 0x0001fd40, 0x0000fe40,
    796   1.4  jmcneill 
    797   1.4  jmcneill 	0x00000000, 0x00000002, 0x0000ff04, 0x0000ff06,
    798   1.4  jmcneill 	0x0000fe08, 0x0000fd0a, 0x0000fd0c, 0x0000fc0f,
    799   1.4  jmcneill 	0x0000fc12, 0x0001fb14, 0x0001fa17, 0x0001fa19,
    800   1.4  jmcneill 	0x0001f91c, 0x0001f91f, 0x0001f822, 0x0001f824,
    801   1.4  jmcneill 	0x0002f727, 0x0002f72a, 0x0002f72c, 0x0002f72f,
    802   1.4  jmcneill 	0x0002f731, 0x0002f733, 0x0002f735, 0x0002f737,
    803   1.4  jmcneill 	0x0002f73a, 0x0002f83b, 0x0002f93c, 0x0002fa3d,
    804   1.4  jmcneill 	0x0001fb3e, 0x0001fc3f, 0x0001fd40, 0x0000fe40,
    805   1.4  jmcneill 
    806   1.4  jmcneill 	0x0002fc06, 0x0002fb08, 0x0002fb0a, 0x0002fa0c,
    807   1.4  jmcneill 	0x0002fa0e, 0x0003f910, 0x0003f912, 0x0003f814,
    808   1.4  jmcneill 	0x0003f816, 0x0003f719, 0x0003f71a, 0x0003f71d,
    809   1.4  jmcneill 	0x0003f71f, 0x0003f721, 0x0003f723, 0x0003f725,
    810   1.4  jmcneill 	0x0002f727, 0x0002f729, 0x0002f72b, 0x0002f82d,
    811   1.4  jmcneill 	0x0002f82e, 0x0001f930, 0x0001fa31, 0x0000fa34,
    812   1.4  jmcneill 	0x0000fb34, 0x0100fc35, 0x01fffd36, 0x01ffff37,
    813   1.4  jmcneill 	0x01fe0037, 0x01fe0138, 0x01fd0338, 0x02fc0538,
    814   1.4  jmcneill 
    815   1.4  jmcneill 	0x0002fa0b, 0x0002fa0c, 0x0002f90e, 0x0002f910,
    816   1.4  jmcneill 	0x0002f911, 0x0002f813, 0x0002f816, 0x0002f817,
    817   1.4  jmcneill 	0x0002f818, 0x0002f81a, 0x0001f81c, 0x0001f81e,
    818   1.4  jmcneill 	0x0001f820, 0x0001f921, 0x0001f923, 0x0000f925,
    819   1.4  jmcneill 	0x0000fa26, 0x0100fa28, 0x01fffb29, 0x01fffc2a,
    820   1.4  jmcneill 	0x01fffc2c, 0x01fefd2d, 0x01fefe2e, 0x01fdff2f,
    821   1.4  jmcneill 	0x01fd0030, 0x01fd0130, 0x01fc0232, 0x02fc0432,
    822   1.4  jmcneill 	0x02fb0532, 0x02fb0633, 0x02fb0833, 0x02fa0933,
    823   1.4  jmcneill 
    824   1.4  jmcneill 	0x0001fa0e, 0x0001f90f, 0x0001f911, 0x0001f913,
    825   1.4  jmcneill 	0x0001f914, 0x0001f915, 0x0000f918, 0x0000fa18,
    826   1.4  jmcneill 	0x0000fa1a, 0x0000fa1b, 0x0000fa1d, 0x00fffb1e,
    827   1.4  jmcneill 	0x01fffb1f, 0x01fffb20, 0x01fffc22, 0x01fefc23,
    828   1.4  jmcneill 	0x01fefd24, 0x01fefe25, 0x01fdfe27, 0x01fdff28,
    829   1.4  jmcneill 	0x01fd0029, 0x01fc012a, 0x01fc022b, 0x01fc032b,
    830   1.4  jmcneill 	0x01fb042d, 0x01fb052d, 0x01fb062e, 0x01fb072e,
    831   1.4  jmcneill 	0x01fa092e, 0x01fa0a2f, 0x01fa0b2f, 0x01fa0d2f,
    832   1.4  jmcneill 
    833   1.4  jmcneill 	0x0000fa11, 0x0000fa12, 0x0000fa13, 0x0000fb14,
    834   1.4  jmcneill 	0x00fffb16, 0x00fffb16, 0x00fffb17, 0x00fffb19,
    835   1.4  jmcneill 	0x00fffc1a, 0x00fefc1c, 0x00fefd1c, 0x01fefd1d,
    836   1.4  jmcneill 	0x01fefe1e, 0x01fdfe20, 0x01fdff21, 0x01fdff22,
    837   1.4  jmcneill 	0x01fd0023, 0x01fc0124, 0x01fc0124, 0x01fc0225,
    838   1.4  jmcneill 	0x01fc0326, 0x01fc0427, 0x01fb0528, 0x01fb0629,
    839   1.4  jmcneill 	0x01fb0729, 0x01fb0829, 0x01fb092a, 0x01fb0a2a,
    840   1.4  jmcneill 	0x00fa0b2c, 0x00fa0c2b, 0x00fa0e2b, 0x00fa0f2c,
    841   1.4  jmcneill 
    842   1.4  jmcneill 	0x00fffc11, 0x00fffc12, 0x00fffc14, 0x00fffc15,
    843   1.4  jmcneill 	0x00fefd16, 0x00fefd17, 0x00fefd18, 0x00fefe19,
    844   1.4  jmcneill 	0x00fefe1a, 0x00fdfe1d, 0x00fdff1d, 0x00fdff1e,
    845   1.4  jmcneill 	0x00fd001d, 0x00fd011e, 0x00fd0120, 0x00fc0221,
    846   1.4  jmcneill 	0x00fc0321, 0x00fc0323, 0x00fc0423, 0x00fc0523,
    847   1.4  jmcneill 	0x00fc0624, 0x00fb0725, 0x00fb0726, 0x00fb0827,
    848   1.4  jmcneill 	0x00fb0926, 0x00fb0a26, 0x00fb0b27, 0x00fb0c27,
    849   1.4  jmcneill 	0x00fb0d27, 0xfffb0e28, 0xfffb0f29, 0xfffc1028,
    850   1.4  jmcneill 
    851   1.4  jmcneill 	0x00fefd13, 0x00fefd13, 0x00fefe14, 0x00fefe15,
    852   1.4  jmcneill 	0x00fefe17, 0x00feff17, 0x00feff17, 0x00fd0018,
    853   1.4  jmcneill 	0x00fd001a, 0x00fd001a, 0x00fd011b, 0x00fd021c,
    854   1.4  jmcneill 	0x00fd021c, 0x00fd031d, 0x00fc031f, 0x00fc041f,
    855   1.4  jmcneill 	0x00fc051f, 0x00fc0521, 0x00fc0621, 0x00fc0721,
    856   1.4  jmcneill 	0x00fc0821, 0x00fc0822, 0x00fc0922, 0x00fc0a23,
    857   1.4  jmcneill 	0xfffc0b24, 0xfffc0c24, 0xfffc0d24, 0xfffc0d25,
    858   1.4  jmcneill 	0xfffc0e25, 0xfffd0f25, 0xfffd1025, 0xfffd1125,
    859   1.4  jmcneill 
    860   1.4  jmcneill 	0x00feff12, 0x00feff14, 0x00feff14, 0x00fe0015,
    861   1.4  jmcneill 	0x00fe0015, 0x00fd0017, 0x00fd0118, 0x00fd0118,
    862   1.4  jmcneill 	0x00fd0218, 0x00fd0219, 0x00fd031a, 0x00fd031a,
    863   1.4  jmcneill 	0x00fd041b, 0x00fd041c, 0x00fd051c, 0x00fd061d,
    864   1.4  jmcneill 	0x00fd061d, 0x00fd071e, 0x00fd081e, 0xfffd081f,
    865   1.4  jmcneill 	0xfffd091f, 0xfffd0a20, 0xfffd0a20, 0xfffd0b21,
    866   1.4  jmcneill 	0xfffd0c21, 0xfffd0d21, 0xfffd0d22, 0xfffd0e23,
    867   1.4  jmcneill 	0xfffe0f22, 0xfefe1022, 0xfefe1122, 0xfefe1123,
    868   1.4  jmcneill 
    869   1.4  jmcneill 	0x00fe0012, 0x00fe0013, 0x00fe0114, 0x00fe0114,
    870   1.4  jmcneill 	0x00fe0116, 0x00fe0216, 0x00fe0216, 0x00fd0317,
    871   1.4  jmcneill 	0x00fd0317, 0x00fd0418, 0x00fd0419, 0x00fd0519,
    872   1.4  jmcneill 	0x00fd051a, 0x00fd061b, 0x00fd061b, 0x00fd071c,
    873   1.4  jmcneill 	0xfffd071e, 0xfffd081d, 0xfffd091d, 0xfffd091e,
    874   1.4  jmcneill 	0xfffe0a1d, 0xfffe0b1e, 0xfffe0b1e, 0xfffe0c1e,
    875   1.4  jmcneill 	0xfffe0d1f, 0xfffe0d1f, 0xfffe0e1f, 0xfeff0f1f,
    876   1.4  jmcneill 	0xfeff0f20, 0xfeff1020, 0xfeff1120, 0xfe001120,
    877   1.4  jmcneill 
    878   1.4  jmcneill 	0x00fe0212, 0x00fe0312, 0x00fe0313, 0x00fe0314,
    879   1.4  jmcneill 	0x00fe0414, 0x00fe0414, 0x00fe0416, 0x00fe0515,
    880   1.4  jmcneill 	0x00fe0516, 0x00fe0616, 0x00fe0617, 0x00fe0717,
    881   1.4  jmcneill 	0xfffe0719, 0xfffe0818, 0xffff0818, 0xffff0919,
    882   1.4  jmcneill 	0xffff0919, 0xffff0a19, 0xffff0a1a, 0xffff0b1a,
    883   1.4  jmcneill 	0xffff0b1b, 0xffff0c1a, 0xff000c1b, 0xff000d1b,
    884   1.4  jmcneill 	0xff000d1b, 0xff000e1b, 0xff000e1c, 0xff010f1c,
    885   1.4  jmcneill 	0xfe01101c, 0xfe01101d, 0xfe02111c, 0xfe02111c,
    886   1.4  jmcneill 
    887   1.4  jmcneill 	0x00ff0411, 0x00ff0411, 0x00ff0412, 0x00ff0512,
    888   1.4  jmcneill 	0x00ff0513, 0x00ff0513, 0x00ff0613, 0x00ff0614,
    889   1.4  jmcneill 	0x00ff0714, 0x00ff0715, 0x00ff0715, 0xffff0816,
    890   1.4  jmcneill 	0xffff0816, 0xff000916, 0xff000917, 0xff000918,
    891   1.4  jmcneill 	0xff000a17, 0xff000a18, 0xff000b18, 0xff000b18,
    892   1.4  jmcneill 	0xff010c18, 0xff010c19, 0xff010d18, 0xff010d18,
    893   1.4  jmcneill 	0xff020d18, 0xff020e19, 0xff020e19, 0xff020f19,
    894   1.4  jmcneill 	0xff030f19, 0xff031019, 0xff031019, 0xff031119,
    895   1.4  jmcneill 
    896   1.4  jmcneill 	0x00ff0511, 0x00ff0511, 0x00000511, 0x00000611,
    897   1.4  jmcneill 	0x00000612, 0x00000612, 0x00000712, 0x00000713,
    898   1.4  jmcneill 	0x00000714, 0x00000814, 0x00000814, 0x00000914,
    899   1.4  jmcneill 	0x00000914, 0xff010914, 0xff010a15, 0xff010a16,
    900   1.4  jmcneill 	0xff010a17, 0xff010b16, 0xff010b16, 0xff020c16,
    901   1.4  jmcneill 	0xff020c16, 0xff020c16, 0xff020d16, 0xff020d17,
    902   1.4  jmcneill 	0xff030d17, 0xff030e17, 0xff030e17, 0xff030f17,
    903   1.4  jmcneill 	0xff040f17, 0xff040f17, 0xff041017, 0xff051017,
    904   1.4  jmcneill 
    905   1.4  jmcneill 	0x00000610, 0x00000610, 0x00000611, 0x00000611,
    906   1.4  jmcneill 	0x00000711, 0x00000712, 0x00010712, 0x00010812,
    907   1.4  jmcneill 	0x00010812, 0x00010812, 0x00010913, 0x00010913,
    908   1.4  jmcneill 	0x00010913, 0x00010a13, 0x00020a13, 0x00020a14,
    909   1.4  jmcneill 	0x00020b14, 0x00020b14, 0x00020b14, 0x00020c14,
    910   1.4  jmcneill 	0x00030c14, 0x00030c15, 0x00030d15, 0x00030d15,
    911   1.4  jmcneill 	0x00040d15, 0x00040e15, 0x00040e15, 0x00040e16,
    912   1.4  jmcneill 	0x00050f15, 0x00050f15, 0x00050f16, 0x00051015,
    913   1.4  jmcneill 
    914   1.4  jmcneill 	0x00000611, 0x00010610, 0x00010710, 0x00010710,
    915   1.4  jmcneill 	0x00010711, 0x00010811, 0x00010811, 0x00010812,
    916   1.4  jmcneill 	0x00010812, 0x00010912, 0x00020912, 0x00020912,
    917   1.4  jmcneill 	0x00020a12, 0x00020a12, 0x00020a13, 0x00020a13,
    918   1.4  jmcneill 	0x00030b13, 0x00030b13, 0x00030b14, 0x00030c13,
    919   1.4  jmcneill 	0x00030c13, 0x00040c13, 0x00040d14, 0x00040d14,
    920   1.4  jmcneill 	0x00040d15, 0x00040d15, 0x00050e14, 0x00050e14,
    921   1.4  jmcneill 	0x00050e15, 0x00050f14, 0x00060f14, 0x00060f14,
    922   1.4  jmcneill 
    923   1.4  jmcneill 	0x0001070f, 0x0001070f, 0x00010710, 0x00010710,
    924   1.4  jmcneill 	0x00010810, 0x00010810, 0x00020810, 0x00020811,
    925   1.4  jmcneill 	0x00020911, 0x00020911, 0x00020912, 0x00020912,
    926   1.4  jmcneill 	0x00020a12, 0x00030a12, 0x00030a12, 0x00030b12,
    927   1.4  jmcneill 	0x00030b12, 0x00030b12, 0x00040b12, 0x00040c12,
    928   1.4  jmcneill 	0x00040c13, 0x00040c14, 0x00040c14, 0x00050d13,
    929   1.4  jmcneill 	0x00050d13, 0x00050d14, 0x00050e13, 0x01050e13,
    930   1.4  jmcneill 	0x01060e13, 0x01060e13, 0x01060e14, 0x01060f13
    931   1.4  jmcneill };
    932   1.4  jmcneill 
    933   1.4  jmcneill static const uint32_t lan2coefftab32[512] = {
    934   1.4  jmcneill 	0x00004000, 0x000140ff, 0x00033ffe, 0x00043ffd, 0x00063efc, 0xff083dfc, 0x000a3bfb, 0xff0d39fb,
    935   1.4  jmcneill 	0xff0f37fb, 0xff1136fa, 0xfe1433fb, 0xfe1631fb, 0xfd192ffb, 0xfd1c2cfb, 0xfd1f29fb, 0xfc2127fc,
    936   1.4  jmcneill 	0xfc2424fc, 0xfc2721fc, 0xfb291ffd, 0xfb2c1cfd, 0xfb2f19fd, 0xfb3116fe, 0xfb3314fe, 0xfa3611ff,
    937   1.4  jmcneill 	0xfb370fff, 0xfb390dff, 0xfb3b0a00, 0xfc3d08ff, 0xfc3e0600, 0xfd3f0400, 0xfe3f0300, 0xff400100,
    938   1.4  jmcneill 
    939   1.4  jmcneill 	0x00004000, 0x000140ff, 0x00033ffe, 0x00043ffd, 0x00063efc, 0xff083dfc, 0x000a3bfb, 0xff0d39fb,
    940   1.4  jmcneill 	0xff0f37fb, 0xff1136fa, 0xfe1433fb, 0xfe1631fb, 0xfd192ffb, 0xfd1c2cfb, 0xfd1f29fb, 0xfc2127fc,
    941   1.4  jmcneill 	0xfc2424fc, 0xfc2721fc, 0xfb291ffd, 0xfb2c1cfd, 0xfb2f19fd, 0xfb3116fe, 0xfb3314fe, 0xfa3611ff,
    942   1.4  jmcneill 	0xfb370fff, 0xfb390dff, 0xfb3b0a00, 0xfc3d08ff, 0xfc3e0600, 0xfd3f0400, 0xfe3f0300, 0xff400100,
    943   1.4  jmcneill 
    944   1.4  jmcneill 	0xff053804, 0xff063803, 0xff083801, 0xff093701, 0xff0a3700, 0xff0c3500, 0xff0e34ff, 0xff1033fe,
    945   1.4  jmcneill 	0xff1232fd, 0xfe1431fd, 0xfe162ffd, 0xfe182dfd, 0xfd1b2cfc, 0xfd1d2afc, 0xfd1f28fc, 0xfd2126fc,
    946   1.4  jmcneill 	0xfd2323fd, 0xfc2621fd, 0xfc281ffd, 0xfc2a1dfd, 0xfc2c1bfd, 0xfd2d18fe, 0xfd2f16fe, 0xfd3114fe,
    947   1.4  jmcneill 	0xfd3212ff, 0xfe3310ff, 0xff340eff, 0x00350cff, 0x00360a00, 0x01360900, 0x02370700, 0x03370600,
    948   1.4  jmcneill 
    949   1.4  jmcneill 	0xff083207, 0xff093206, 0xff0a3205, 0xff0c3203, 0xff0d3103, 0xff0e3102, 0xfe113001, 0xfe132f00,
    950   1.4  jmcneill 	0xfe142e00, 0xfe162dff, 0xfe182bff, 0xfe192aff, 0xfe1b29fe, 0xfe1d27fe, 0xfe1f25fe, 0xfd2124fe,
    951   1.4  jmcneill 	0xfe2222fe, 0xfe2421fd, 0xfe251ffe, 0xfe271dfe, 0xfe291bfe, 0xff2a19fe, 0xff2b18fe, 0xff2d16fe,
    952   1.4  jmcneill 	0x002e14fe, 0x002f12ff, 0x013010ff, 0x02300fff, 0x03310dff, 0x04310cff, 0x05310a00, 0x06310900,
    953   1.4  jmcneill 
    954   1.4  jmcneill 	0xff0a2e09, 0xff0b2e08, 0xff0c2e07, 0xff0e2d06, 0xff0f2d05, 0xff102d04, 0xff122c03, 0xfe142c02,
    955   1.4  jmcneill 	0xfe152b02, 0xfe172a01, 0xfe182901, 0xfe1a2800, 0xfe1b2700, 0xfe1d2500, 0xff1e24ff, 0xfe2023ff,
    956   1.4  jmcneill 	0xff2121ff, 0xff2320fe, 0xff241eff, 0x00251dfe, 0x00261bff, 0x00281afe, 0x012818ff, 0x012a16ff,
    957   1.4  jmcneill 	0x022a15ff, 0x032b13ff, 0x032c12ff, 0x052c10ff, 0x052d0fff, 0x062d0d00, 0x072d0c00, 0x082d0b00,
    958   1.4  jmcneill 
    959   1.4  jmcneill 	0xff0c2a0b, 0xff0d2a0a, 0xff0e2a09, 0xff0f2a08, 0xff102a07, 0xff112a06, 0xff132905, 0xff142904,
    960   1.4  jmcneill 	0xff162803, 0xff172703, 0xff182702, 0xff1a2601, 0xff1b2501, 0xff1c2401, 0xff1e2300, 0xff1f2200,
    961   1.4  jmcneill 	0x00202000, 0x00211f00, 0x01221d00, 0x01231c00, 0x01251bff, 0x02251aff, 0x032618ff, 0x032717ff,
    962   1.4  jmcneill 	0x042815ff, 0x052814ff, 0x052913ff, 0x06291100, 0x072a10ff, 0x082a0e00, 0x092a0d00, 0x0a2a0c00,
    963   1.4  jmcneill 
    964   1.4  jmcneill 	0xff0d280c, 0xff0e280b, 0xff0f280a, 0xff102809, 0xff112808, 0xff122708, 0xff142706, 0xff152705,
    965   1.4  jmcneill 	0xff162605, 0xff172604, 0xff192503, 0xff1a2403, 0x001b2302, 0x001c2202, 0x001d2201, 0x001e2101,
    966   1.4  jmcneill 	0x011f1f01, 0x01211e00, 0x01221d00, 0x02221c00, 0x02231b00, 0x03241900, 0x04241800, 0x04251700,
    967   1.4  jmcneill 	0x052616ff, 0x06261400, 0x072713ff, 0x08271100, 0x08271100, 0x09271000, 0x0a280e00, 0x0b280d00,
    968   1.4  jmcneill 
    969   1.4  jmcneill 	0xff0e260d, 0xff0f260c, 0xff10260b, 0xff11260a, 0xff122609, 0xff132608, 0xff142508, 0xff152507,
    970   1.4  jmcneill 	0x00152506, 0x00172405, 0x00182305, 0x00192304, 0x001b2203, 0x001c2103, 0x011d2002, 0x011d2002,
    971   1.4  jmcneill 	0x011f1f01, 0x021f1e01, 0x02201d01, 0x03211c00, 0x03221b00, 0x04221a00, 0x04231801, 0x05241700,
    972   1.4  jmcneill 	0x06241600, 0x07241500, 0x08251300, 0x09251200, 0x09261100, 0x0a261000, 0x0b260f00, 0x0c260e00,
    973   1.4  jmcneill 
    974   1.4  jmcneill 	0xff0e250e, 0xff0f250d, 0xff10250c, 0xff11250b, 0x0011250a, 0x00132409, 0x00142408, 0x00152407,
    975   1.4  jmcneill 	0x00162307, 0x00172306, 0x00182206, 0x00192205, 0x011a2104, 0x011b2004, 0x011c2003, 0x021c1f03,
    976   1.4  jmcneill 	0x021e1e02, 0x031e1d02, 0x03201c01, 0x04201b01, 0x04211a01, 0x05221900, 0x05221801, 0x06231700,
    977   1.4  jmcneill 	0x07231600, 0x07241500, 0x08241400, 0x09241300, 0x0a241200, 0x0b241100, 0x0c241000, 0x0d240f00,
    978   1.4  jmcneill 
    979   1.4  jmcneill 	0x000e240e, 0x000f240d, 0x0010240c, 0x0011240b, 0x0013230a, 0x0013230a, 0x00142309, 0x00152308,
    980   1.4  jmcneill 	0x00162208, 0x00172207, 0x01182106, 0x01192105, 0x011a2005, 0x021b1f04, 0x021b1f04, 0x021d1e03,
    981   1.4  jmcneill 	0x031d1d03, 0x031e1d02, 0x041e1c02, 0x041f1b02, 0x05201a01, 0x05211901, 0x06211801, 0x07221700,
    982   1.4  jmcneill 	0x07221601, 0x08231500, 0x09231400, 0x0a231300, 0x0a231300, 0x0b231200, 0x0c231100, 0x0d231000,
    983   1.4  jmcneill 
    984   1.4  jmcneill 	0x000f220f, 0x0010220e, 0x0011220d, 0x0012220c, 0x0013220b, 0x0013220b, 0x0015210a, 0x0015210a,
    985   1.4  jmcneill 	0x01162108, 0x01172008, 0x01182007, 0x02191f06, 0x02191f06, 0x021a1e06, 0x031a1e05, 0x031c1d04,
    986   1.4  jmcneill 	0x041c1c04, 0x041d1c03, 0x051d1b03, 0x051e1a03, 0x061f1902, 0x061f1902, 0x07201801, 0x08201701,
    987   1.4  jmcneill 	0x08211601, 0x09211501, 0x0a211500, 0x0b211400, 0x0b221300, 0x0c221200, 0x0d221100, 0x0e221000,
    988   1.4  jmcneill 
    989   1.4  jmcneill 	0x0010210f, 0x0011210e, 0x0011210e, 0x0012210d, 0x0013210c, 0x0014200c, 0x0114200b, 0x0115200a,
    990   1.4  jmcneill 	0x01161f0a, 0x01171f09, 0x02171f08, 0x02181e08, 0x03181e07, 0x031a1d06, 0x031a1d06, 0x041b1c05,
    991   1.4  jmcneill 	0x041c1c04, 0x051c1b04, 0x051d1a04, 0x061d1a03, 0x071d1903, 0x071e1803, 0x081e1802, 0x081f1702,
    992   1.4  jmcneill 	0x091f1602, 0x0a201501, 0x0b1f1501, 0x0b201401, 0x0c211300, 0x0d211200, 0x0e201200, 0x0e211100,
    993   1.4  jmcneill 
    994   1.4  jmcneill 	0x00102010, 0x0011200f, 0x0012200e, 0x0013200d, 0x0013200d, 0x01141f0c, 0x01151f0b, 0x01151f0b,
    995   1.4  jmcneill 	0x01161f0a, 0x02171e09, 0x02171e09, 0x03181d08, 0x03191d07, 0x03191d07, 0x041a1c06, 0x041b1c05,
    996   1.4  jmcneill 	0x051b1b05, 0x051c1b04, 0x061c1a04, 0x071d1903, 0x071d1903, 0x081d1803, 0x081e1703, 0x091e1702,
    997   1.4  jmcneill 	0x0a1f1601, 0x0a1f1502, 0x0b1f1501, 0x0c1f1401, 0x0d201300, 0x0d201300, 0x0e201200, 0x0f201100,
    998   1.4  jmcneill 
    999   1.4  jmcneill 	0x00102010, 0x0011200f, 0x00121f0f, 0x00131f0e, 0x00141f0d, 0x01141f0c, 0x01141f0c, 0x01151e0c,
   1000   1.4  jmcneill 	0x02161e0a, 0x02171e09, 0x03171d09, 0x03181d08, 0x03181d08, 0x04191c07, 0x041a1c06, 0x051a1b06,
   1001   1.4  jmcneill 	0x051b1b05, 0x061b1a05, 0x061c1a04, 0x071c1904, 0x081c1903, 0x081d1803, 0x091d1703, 0x091e1702,
   1002   1.4  jmcneill 	0x0a1e1602, 0x0b1e1502, 0x0c1e1501, 0x0c1f1401, 0x0d1f1400, 0x0e1f1300, 0x0e1f1201, 0x0f1f1200,
   1003   1.4  jmcneill 
   1004   1.4  jmcneill 	0x00111e11, 0x00121e10, 0x00131e0f, 0x00131e0f, 0x01131e0e, 0x01141d0e, 0x02151d0c, 0x02151d0c,
   1005   1.4  jmcneill 	0x02161d0b, 0x03161c0b, 0x03171c0a, 0x04171c09, 0x04181b09, 0x05181b08, 0x05191b07, 0x06191a07,
   1006   1.4  jmcneill 	0x061a1a06, 0x071a1906, 0x071b1905, 0x081b1805, 0x091b1804, 0x091c1704, 0x0a1c1703, 0x0a1c1604,
   1007   1.4  jmcneill 	0x0b1d1602, 0x0c1d1502, 0x0c1d1502, 0x0d1d1402, 0x0e1d1401, 0x0e1e1301, 0x0f1e1300, 0x101e1200,
   1008   1.4  jmcneill 
   1009   1.4  jmcneill 	0x00111e11, 0x00121e10, 0x00131d10, 0x01131d0f, 0x01141d0e, 0x01141d0e, 0x02151c0d, 0x02151c0d,
   1010   1.4  jmcneill 	0x03161c0b, 0x03161c0b, 0x04171b0a, 0x04171b0a, 0x05171b09, 0x05181a09, 0x06181a08, 0x06191a07,
   1011   1.4  jmcneill 	0x07191907, 0x071a1906, 0x081a1806, 0x081a1806, 0x091a1805, 0x0a1b1704, 0x0a1b1704, 0x0b1c1603,
   1012   1.4  jmcneill 	0x0b1c1603, 0x0c1c1503, 0x0d1c1502, 0x0d1d1402, 0x0e1d1401, 0x0f1d1301, 0x0f1d1301, 0x101e1200,
   1013   1.4  jmcneill };
   1014   1.4  jmcneill 
   1015   1.4  jmcneill static void
   1016   1.4  jmcneill sunxi_mixer_vsu_init(struct sunxi_mixer_softc *sc, u_int src_w, u_int src_h,
   1017  1.17  riastrad     u_int crtc_w, u_int crtc_h, const struct drm_format_info *format)
   1018   1.4  jmcneill {
   1019   1.4  jmcneill 	const u_int hstep = (src_w << 16) / crtc_w;
   1020   1.4  jmcneill 	const u_int vstep = (src_h << 16) / crtc_h;
   1021   1.4  jmcneill 
   1022  1.17  riastrad 	const int hsub = format->hsub;
   1023  1.17  riastrad 	const int vsub = format->vsub;
   1024   1.4  jmcneill 
   1025   1.4  jmcneill 	const u_int src_cw = src_w / hsub;
   1026   1.4  jmcneill 	const u_int src_ch = src_h / vsub;
   1027   1.4  jmcneill 
   1028   1.4  jmcneill 	VSU_WRITE(sc, VS_OUT_SIZE_REG, ((crtc_h - 1) << 16) | (crtc_w - 1));
   1029   1.4  jmcneill 	VSU_WRITE(sc, VS_Y_SIZE_REG, ((src_h - 1) << 16) | (src_w - 1));
   1030   1.4  jmcneill 	VSU_WRITE(sc, VS_Y_HSTEP_REG, hstep << 4);
   1031   1.4  jmcneill 	VSU_WRITE(sc, VS_Y_VSTEP_REG, vstep << 4);
   1032   1.4  jmcneill 	VSU_WRITE(sc, VS_Y_HPHASE_REG, 0);
   1033   1.4  jmcneill 	VSU_WRITE(sc, VS_Y_VPHASE0_REG, 0);
   1034   1.4  jmcneill 	VSU_WRITE(sc, VS_Y_VPHASE1_REG, 0);
   1035   1.4  jmcneill 	VSU_WRITE(sc, VS_C_SIZE_REG, ((src_ch - 1) << 16) | (src_cw - 1));
   1036   1.4  jmcneill 	VSU_WRITE(sc, VS_C_HSTEP_REG, (hstep / hsub) << 4);
   1037   1.4  jmcneill 	VSU_WRITE(sc, VS_C_VSTEP_REG, (vstep / vsub) << 4);
   1038   1.4  jmcneill 	VSU_WRITE(sc, VS_C_HPHASE_REG, 0);
   1039   1.4  jmcneill 	VSU_WRITE(sc, VS_C_VPHASE0_REG, 0);
   1040   1.4  jmcneill 	VSU_WRITE(sc, VS_C_VPHASE1_REG, 0);
   1041   1.4  jmcneill 
   1042   1.4  jmcneill 	/* XXX */
   1043   1.4  jmcneill 	const u_int coef_base = 0;
   1044   1.4  jmcneill 
   1045   1.4  jmcneill 	for (int i = 0; i < 32; i++) {
   1046   1.4  jmcneill 		VSU_WRITE(sc, VS_Y_HCOEF0_REG(i), lan3coefftab32_left[coef_base + i]);
   1047   1.4  jmcneill 		VSU_WRITE(sc, VS_Y_HCOEF1_REG(i), lan3coefftab32_right[coef_base + i]);
   1048   1.4  jmcneill 		VSU_WRITE(sc, VS_Y_VCOEF_REG(i), lan2coefftab32[coef_base + i]);
   1049   1.4  jmcneill 		VSU_WRITE(sc, VS_C_HCOEF0_REG(i), lan3coefftab32_left[coef_base + i]);
   1050   1.4  jmcneill 		VSU_WRITE(sc, VS_C_HCOEF1_REG(i), lan3coefftab32_right[coef_base + i]);
   1051   1.4  jmcneill 		VSU_WRITE(sc, VS_C_VCOEF_REG(i), lan2coefftab32[coef_base + i]);
   1052   1.4  jmcneill 	}
   1053   1.4  jmcneill 
   1054   1.4  jmcneill 	/* Commit settings and enable scaler */
   1055   1.4  jmcneill 	VSU_WRITE(sc, VS_CTRL_REG, VS_CTRL_COEF_SWITCH_EN | VS_CTRL_EN);
   1056   1.4  jmcneill }
   1057   1.4  jmcneill 
   1058   1.4  jmcneill static const u32 yuv2rgb[] = {
   1059   1.4  jmcneill 	0x000004A8, 0x00000000, 0x00000662, 0xFFFC865A,
   1060   1.4  jmcneill 	0x000004A8, 0xFFFFFE6F, 0xFFFFFCBF, 0x00021FF4,
   1061   1.4  jmcneill 	0x000004A8, 0x00000813, 0x00000000, 0xFFFBAE4A,
   1062   1.4  jmcneill };
   1063   1.4  jmcneill 
   1064   1.4  jmcneill static void
   1065   1.4  jmcneill sunxi_mixer_csc_init(struct sunxi_mixer_softc *sc, uint32_t pixel_format)
   1066   1.4  jmcneill {
   1067   1.4  jmcneill 	const u_int crtc_index = drm_crtc_index(&sc->sc_crtc.base);
   1068   1.4  jmcneill 
   1069   1.4  jmcneill 	for (int i = 0; i < __arraycount(yuv2rgb); i++)
   1070   1.4  jmcneill 		CSC_WRITE(sc, crtc_index, CSC_COEFF0_REG(0) + i * 4, yuv2rgb[i]);
   1071   1.4  jmcneill 
   1072   1.4  jmcneill 	CSC_WRITE(sc, crtc_index, CSC_BYPASS_REG, CSC_BYPASS_DISABLE);
   1073   1.4  jmcneill }
   1074   1.4  jmcneill 
   1075   1.4  jmcneill static void
   1076   1.4  jmcneill sunxi_mixer_csc_disable(struct sunxi_mixer_softc *sc)
   1077   1.4  jmcneill {
   1078   1.4  jmcneill 	const u_int crtc_index = drm_crtc_index(&sc->sc_crtc.base);
   1079   1.4  jmcneill 
   1080   1.4  jmcneill 	CSC_WRITE(sc, crtc_index, CSC_BYPASS_REG, 0);
   1081   1.4  jmcneill }
   1082   1.4  jmcneill 
   1083   1.3  jmcneill static int
   1084   1.3  jmcneill sunxi_mixer_overlay_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
   1085   1.3  jmcneill     struct drm_framebuffer *fb, int crtc_x, int crtc_y, u_int crtc_w, u_int crtc_h,
   1086  1.17  riastrad     uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
   1087  1.17  riastrad     struct drm_modeset_acquire_ctx *ctx)
   1088   1.3  jmcneill {
   1089   1.6  jmcneill 	struct sunxi_mixer_plane *overlay = to_sunxi_mixer_plane(plane);
   1090   1.3  jmcneill 	struct sunxi_mixer_softc * const sc = overlay->sc;
   1091   1.3  jmcneill 	struct sunxi_drm_framebuffer *sfb = to_sunxi_drm_framebuffer(fb);
   1092   1.3  jmcneill 	uint32_t val;
   1093   1.3  jmcneill 
   1094  1.17  riastrad 	const u_int fbfmt = sunxi_mixer_overlay_format(fb->format->format);
   1095   1.3  jmcneill 	const uint64_t paddr = (uint64_t)sfb->obj->dmamap->dm_segs[0].ds_addr;
   1096   1.3  jmcneill 
   1097   1.3  jmcneill 	const uint32_t input_size = (((src_h >> 16) - 1) << 16) | ((src_w >> 16) - 1);
   1098   1.3  jmcneill 	const uint32_t input_pos = ((src_y >> 16) << 16) | (src_x >> 16);
   1099   1.3  jmcneill 
   1100   1.3  jmcneill 	OVL_V_WRITE(sc, OVL_V_MBSIZE(0), input_size);
   1101   1.3  jmcneill 	OVL_V_WRITE(sc, OVL_V_COOR(0), input_pos);
   1102   1.3  jmcneill 
   1103   1.4  jmcneill 	/* Note: DRM and hardware's ideas of pitch 1 and 2 are swapped */
   1104   1.4  jmcneill 
   1105   1.3  jmcneill 	OVL_V_WRITE(sc, OVL_V_PITCH0(0), fb->pitches[0]);
   1106   1.4  jmcneill 	OVL_V_WRITE(sc, OVL_V_PITCH1(0), fb->pitches[2]);
   1107   1.4  jmcneill 	OVL_V_WRITE(sc, OVL_V_PITCH2(0), fb->pitches[1]);
   1108   1.3  jmcneill 
   1109   1.3  jmcneill 	const uint64_t paddr0 = paddr + fb->offsets[0] +
   1110  1.17  riastrad 	    (src_x >> 16) * fb->format->cpp[0] +
   1111   1.3  jmcneill 	    (src_y >> 16) * fb->pitches[0];
   1112   1.4  jmcneill 	const uint64_t paddr1 = paddr + fb->offsets[2] +
   1113  1.17  riastrad 	    (src_x >> 16) * fb->format->cpp[2] +
   1114   1.4  jmcneill 	    (src_y >> 16) * fb->pitches[2];
   1115   1.4  jmcneill 	const uint64_t paddr2 = paddr + fb->offsets[1] +
   1116  1.17  riastrad 	    (src_x >> 16) * fb->format->cpp[1] +
   1117   1.3  jmcneill 	    (src_y >> 16) * fb->pitches[1];
   1118   1.3  jmcneill 
   1119   1.3  jmcneill 	OVL_V_WRITE(sc, OVL_V_TOP_HADD0, (paddr0 >> 32) & OVL_V_TOP_HADD_LAYER0);
   1120   1.3  jmcneill 	OVL_V_WRITE(sc, OVL_V_TOP_HADD1, (paddr1 >> 32) & OVL_V_TOP_HADD_LAYER0);
   1121   1.3  jmcneill 	OVL_V_WRITE(sc, OVL_V_TOP_HADD2, (paddr2 >> 32) & OVL_V_TOP_HADD_LAYER0);
   1122   1.3  jmcneill 
   1123   1.3  jmcneill 	OVL_V_WRITE(sc, OVL_V_TOP_LADD0(0), paddr0 & 0xffffffff);
   1124   1.3  jmcneill 	OVL_V_WRITE(sc, OVL_V_TOP_LADD1(0), paddr1 & 0xffffffff);
   1125   1.3  jmcneill 	OVL_V_WRITE(sc, OVL_V_TOP_LADD2(0), paddr2 & 0xffffffff);
   1126   1.3  jmcneill 
   1127   1.3  jmcneill 	OVL_V_WRITE(sc, OVL_V_SIZE, input_size);
   1128   1.3  jmcneill 
   1129   1.3  jmcneill 	val = OVL_V_ATTCTL_LAY0_EN;
   1130   1.3  jmcneill 	val |= __SHIFTIN(fbfmt, OVL_V_ATTCTL_LAY_FBFMT);
   1131  1.17  riastrad 	if (sunxi_mixer_overlay_rgb(fb->format->format) == true)
   1132   1.3  jmcneill 		val |= OVL_V_ATTCTL_VIDEO_UI_SEL;
   1133   1.3  jmcneill 	OVL_V_WRITE(sc, OVL_V_ATTCTL(0), val);
   1134   1.3  jmcneill 
   1135   1.4  jmcneill 	/* Enable video scaler */
   1136  1.17  riastrad 	sunxi_mixer_vsu_init(sc, src_w >> 16, src_h >> 16, crtc_w, crtc_h, fb->format);
   1137   1.4  jmcneill 
   1138   1.4  jmcneill 	/* Enable colour space conversion for non-RGB formats */
   1139  1.17  riastrad 	if (sunxi_mixer_overlay_rgb(fb->format->format) == false)
   1140  1.17  riastrad 		sunxi_mixer_csc_init(sc, fb->format->format);
   1141   1.4  jmcneill 	else
   1142   1.4  jmcneill 		sunxi_mixer_csc_disable(sc);
   1143   1.4  jmcneill 
   1144   1.3  jmcneill 	/* Set blender 1 input size */
   1145   1.4  jmcneill 	BLD_WRITE(sc, BLD_CH_ISIZE(1), ((crtc_h - 1) << 16) | (crtc_w - 1));
   1146   1.3  jmcneill 	/* Set blender 1 offset */
   1147   1.3  jmcneill 	BLD_WRITE(sc, BLD_CH_OFFSET(1), (crtc_y << 16) | crtc_x);
   1148   1.3  jmcneill 	/* Route channel 0 to pipe 1 */
   1149   1.3  jmcneill 	val = BLD_READ(sc, BLD_CH_RTCTL);
   1150   1.3  jmcneill 	val &= ~BLD_CH_RTCTL_P1;
   1151   1.3  jmcneill 	val |= __SHIFTIN(0, BLD_CH_RTCTL_P1);
   1152   1.3  jmcneill 	BLD_WRITE(sc, BLD_CH_RTCTL, val);
   1153   1.3  jmcneill 
   1154   1.3  jmcneill         /* Enable pipe 1 */
   1155   1.3  jmcneill 	val = BLD_READ(sc, BLD_FILL_COLOR_CTL);
   1156   1.3  jmcneill 	val |= BLD_FILL_COLOR_CTL_P1_EN;
   1157   1.3  jmcneill 	BLD_WRITE(sc, BLD_FILL_COLOR_CTL, val);
   1158   1.3  jmcneill 
   1159   1.3  jmcneill 	/* Commit settings */
   1160   1.3  jmcneill 	GLB_WRITE(sc, GLB_DBUFFER, GLB_DBUFFER_DOUBLE_BUFFER_RDY);
   1161   1.3  jmcneill 
   1162   1.3  jmcneill 	return 0;
   1163   1.3  jmcneill }
   1164   1.3  jmcneill 
   1165   1.3  jmcneill static int
   1166  1.17  riastrad sunxi_mixer_overlay_disable_plane(struct drm_plane *plane,
   1167  1.17  riastrad     struct drm_modeset_acquire_ctx *ctx)
   1168   1.3  jmcneill {
   1169   1.6  jmcneill 	struct sunxi_mixer_plane *overlay = to_sunxi_mixer_plane(plane);
   1170   1.3  jmcneill 	struct sunxi_mixer_softc * const sc = overlay->sc;
   1171   1.3  jmcneill 	uint32_t val;
   1172   1.3  jmcneill 
   1173   1.4  jmcneill 	sunxi_mixer_csc_disable(sc);
   1174   1.4  jmcneill 
   1175   1.3  jmcneill 	val = BLD_READ(sc, BLD_FILL_COLOR_CTL);
   1176   1.3  jmcneill 	val &= ~BLD_FILL_COLOR_CTL_P1_EN;
   1177   1.3  jmcneill 	BLD_WRITE(sc, BLD_FILL_COLOR_CTL, val);
   1178   1.3  jmcneill 
   1179   1.3  jmcneill 	/* Commit settings */
   1180   1.3  jmcneill 	GLB_WRITE(sc, GLB_DBUFFER, GLB_DBUFFER_DOUBLE_BUFFER_RDY);
   1181   1.3  jmcneill 
   1182   1.3  jmcneill 	return 0;
   1183   1.3  jmcneill }
   1184   1.3  jmcneill 
   1185   1.3  jmcneill static const struct drm_plane_funcs sunxi_mixer_overlay_funcs = {
   1186   1.3  jmcneill 	.update_plane = sunxi_mixer_overlay_update_plane,
   1187   1.3  jmcneill 	.disable_plane = sunxi_mixer_overlay_disable_plane,
   1188   1.3  jmcneill 	.destroy = sunxi_mixer_overlay_destroy,
   1189   1.3  jmcneill };
   1190   1.3  jmcneill 
   1191   1.3  jmcneill static uint32_t sunxi_mixer_overlay_formats[] = {
   1192   1.6  jmcneill 	DRM_FORMAT_ARGB8888,
   1193   1.3  jmcneill 	DRM_FORMAT_XRGB8888,
   1194   1.3  jmcneill #if notyet
   1195   1.3  jmcneill 	DRM_FORMAT_VYUY,
   1196   1.3  jmcneill 	DRM_FORMAT_YVYU,
   1197   1.3  jmcneill 	DRM_FORMAT_UYVY,
   1198   1.3  jmcneill 	DRM_FORMAT_YUYV,
   1199   1.4  jmcneill #endif
   1200   1.3  jmcneill 	DRM_FORMAT_YUV422,
   1201   1.3  jmcneill 	DRM_FORMAT_YUV420,
   1202   1.3  jmcneill 	DRM_FORMAT_YUV411,
   1203   1.3  jmcneill };
   1204   1.3  jmcneill 
   1205   1.1  jmcneill static int
   1206   1.1  jmcneill sunxi_mixer_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate)
   1207   1.1  jmcneill {
   1208   1.1  jmcneill 	struct sunxi_mixer_softc * const sc = device_private(dev);
   1209   1.1  jmcneill 	struct drm_device *ddev;
   1210   1.6  jmcneill 	bus_size_t reg;
   1211   1.1  jmcneill 
   1212   1.1  jmcneill 	if (!activate)
   1213   1.1  jmcneill 		return EINVAL;
   1214   1.1  jmcneill 
   1215   1.1  jmcneill 	ddev = sunxi_drm_endpoint_device(ep);
   1216   1.1  jmcneill 	if (ddev == NULL) {
   1217   1.1  jmcneill 		DRM_ERROR("couldn't find DRM device\n");
   1218   1.1  jmcneill 		return ENXIO;
   1219   1.1  jmcneill 	}
   1220   1.1  jmcneill 
   1221   1.1  jmcneill 	sc->sc_crtc.sc = sc;
   1222   1.3  jmcneill 	sc->sc_overlay.sc = sc;
   1223   1.1  jmcneill 
   1224   1.6  jmcneill 	/* Initialize registers */
   1225   1.6  jmcneill 	for (reg = 0; reg < 0xc000; reg += 4)
   1226   1.6  jmcneill 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, 0);
   1227   1.6  jmcneill 	BLD_WRITE(sc, BLD_CTL(0), 0x03010301);
   1228   1.6  jmcneill 	BLD_WRITE(sc, BLD_CTL(1), 0x03010301);
   1229   1.6  jmcneill 	BLD_WRITE(sc, BLD_CTL(2), 0x03010301);
   1230   1.6  jmcneill 	BLD_WRITE(sc, BLD_CTL(3), 0x03010301);
   1231   1.6  jmcneill 
   1232   1.7  jmcneill 	if (sc->sc_ovl_ui_count > 1)
   1233   1.7  jmcneill 		drm_crtc_init(ddev, &sc->sc_crtc.base, &sunxi_mixer0_crtc_funcs);
   1234   1.7  jmcneill 	else
   1235   1.7  jmcneill 		drm_crtc_init(ddev, &sc->sc_crtc.base, &sunxi_mixer1_crtc_funcs);
   1236   1.1  jmcneill 	drm_crtc_helper_add(&sc->sc_crtc.base, &sunxi_mixer_crtc_helper_funcs);
   1237   1.1  jmcneill 
   1238   1.3  jmcneill 	drm_universal_plane_init(ddev, &sc->sc_overlay.base,
   1239   1.3  jmcneill 	    1 << drm_crtc_index(&sc->sc_crtc.base), &sunxi_mixer_overlay_funcs,
   1240   1.3  jmcneill 	    sunxi_mixer_overlay_formats, __arraycount(sunxi_mixer_overlay_formats),
   1241  1.17  riastrad 	    NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
   1242   1.3  jmcneill 
   1243   1.1  jmcneill 	return fdt_endpoint_activate(ep, activate);
   1244   1.1  jmcneill }
   1245   1.1  jmcneill 
   1246   1.1  jmcneill static void *
   1247   1.1  jmcneill sunxi_mixer_ep_get_data(device_t dev, struct fdt_endpoint *ep)
   1248   1.1  jmcneill {
   1249   1.1  jmcneill 	struct sunxi_mixer_softc * const sc = device_private(dev);
   1250   1.1  jmcneill 
   1251   1.1  jmcneill 	return &sc->sc_crtc;
   1252   1.1  jmcneill }
   1253   1.1  jmcneill 
   1254   1.1  jmcneill static int
   1255   1.1  jmcneill sunxi_mixer_match(device_t parent, cfdata_t cf, void *aux)
   1256   1.1  jmcneill {
   1257   1.1  jmcneill 	struct fdt_attach_args * const faa = aux;
   1258   1.1  jmcneill 
   1259  1.16   thorpej 	return of_compatible_match(faa->faa_phandle, compat_data);
   1260   1.1  jmcneill }
   1261   1.1  jmcneill 
   1262   1.1  jmcneill static void
   1263   1.1  jmcneill sunxi_mixer_attach(device_t parent, device_t self, void *aux)
   1264   1.1  jmcneill {
   1265   1.1  jmcneill 	struct sunxi_mixer_softc * const sc = device_private(self);
   1266   1.1  jmcneill 	struct fdt_attach_args * const faa = aux;
   1267   1.1  jmcneill 	struct fdt_endpoint *out_ep;
   1268   1.1  jmcneill 	const int phandle = faa->faa_phandle;
   1269  1.11  jakllsch 	const struct sunxi_mixer_compat_data * const cd =
   1270  1.16   thorpej 	    of_compatible_lookup(phandle, compat_data)->data;
   1271   1.1  jmcneill 	struct clk *clk_bus, *clk_mod;
   1272   1.1  jmcneill 	struct fdtbus_reset *rst;
   1273   1.1  jmcneill 	bus_addr_t addr;
   1274   1.1  jmcneill 	bus_size_t size;
   1275   1.1  jmcneill 
   1276   1.1  jmcneill 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
   1277   1.1  jmcneill 		aprint_error(": couldn't get registers\n");
   1278   1.1  jmcneill 		return;
   1279   1.1  jmcneill 	}
   1280   1.1  jmcneill 
   1281   1.1  jmcneill 	rst = fdtbus_reset_get_index(phandle, 0);
   1282   1.1  jmcneill 	if (rst == NULL || fdtbus_reset_deassert(rst) != 0) {
   1283   1.1  jmcneill 		aprint_error(": couldn't de-assert reset\n");
   1284   1.1  jmcneill 		return;
   1285   1.1  jmcneill 	}
   1286   1.1  jmcneill 
   1287   1.1  jmcneill 	clk_bus = fdtbus_clock_get(phandle, "bus");
   1288   1.1  jmcneill 	if (clk_bus == NULL || clk_enable(clk_bus) != 0) {
   1289   1.1  jmcneill 		aprint_error(": couldn't enable bus clock\n");
   1290   1.1  jmcneill 		return;
   1291   1.1  jmcneill 	}
   1292   1.1  jmcneill 
   1293   1.1  jmcneill 	clk_mod = fdtbus_clock_get(phandle, "mod");
   1294   1.1  jmcneill 	if (clk_mod == NULL ||
   1295   1.1  jmcneill 	    clk_set_rate(clk_mod, SUNXI_MIXER_FREQ) != 0 ||
   1296   1.1  jmcneill 	    clk_enable(clk_mod) != 0) {
   1297   1.1  jmcneill 		aprint_error(": couldn't enable mod clock\n");
   1298   1.1  jmcneill 		return;
   1299   1.1  jmcneill 	}
   1300   1.1  jmcneill 
   1301   1.1  jmcneill 	sc->sc_dev = self;
   1302   1.1  jmcneill 	sc->sc_bst = faa->faa_bst;
   1303   1.1  jmcneill 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
   1304   1.1  jmcneill 		aprint_error(": couldn't map registers\n");
   1305   1.1  jmcneill 		return;
   1306   1.1  jmcneill 	}
   1307   1.1  jmcneill 	sc->sc_phandle = faa->faa_phandle;
   1308  1.11  jakllsch 	sc->sc_ovl_ui_count = cd->ovl_ui_count;
   1309   1.1  jmcneill 
   1310   1.1  jmcneill 	aprint_naive("\n");
   1311   1.1  jmcneill 	aprint_normal(": Display Engine Mixer\n");
   1312   1.1  jmcneill 
   1313   1.1  jmcneill 	sc->sc_ports.dp_ep_activate = sunxi_mixer_ep_activate;
   1314   1.1  jmcneill 	sc->sc_ports.dp_ep_get_data = sunxi_mixer_ep_get_data;
   1315   1.1  jmcneill 	fdt_ports_register(&sc->sc_ports, self, phandle, EP_DRM_CRTC);
   1316   1.1  jmcneill 
   1317  1.11  jakllsch 	out_ep = fdt_endpoint_get_from_index(&sc->sc_ports,
   1318  1.11  jakllsch 	    MIXER_PORT_OUTPUT, cd->mixer_index);
   1319  1.11  jakllsch 	if (out_ep == NULL) {
   1320  1.11  jakllsch 		/* Couldn't find new-style DE2 endpoint, try old style. */
   1321  1.11  jakllsch 		out_ep = fdt_endpoint_get_from_index(&sc->sc_ports,
   1322  1.11  jakllsch 		    MIXER_PORT_OUTPUT, 0);
   1323  1.11  jakllsch 	}
   1324  1.11  jakllsch 
   1325   1.1  jmcneill 	if (out_ep != NULL)
   1326   1.1  jmcneill 		sunxi_drm_register_endpoint(phandle, out_ep);
   1327   1.1  jmcneill }
   1328   1.1  jmcneill 
   1329   1.1  jmcneill CFATTACH_DECL_NEW(sunxi_mixer, sizeof(struct sunxi_mixer_softc),
   1330   1.1  jmcneill 	sunxi_mixer_match, sunxi_mixer_attach, NULL, NULL);
   1331