sunxi_mixer.c revision 1.2
1 /* $NetBSD: sunxi_mixer.c,v 1.2 2019/01/31 01:49:28 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_mixer.c,v 1.2 2019/01/31 01:49:28 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/conf.h> 39 40 #include <drm/drmP.h> 41 #include <drm/drm_crtc.h> 42 #include <drm/drm_crtc_helper.h> 43 #include <drm/drm_plane_helper.h> 44 45 #include <dev/fdt/fdtvar.h> 46 #include <dev/fdt/fdt_port.h> 47 48 #include <arm/sunxi/sunxi_drm.h> 49 50 #define SUNXI_MIXER_FREQ 432000000 51 52 #define GLB_BASE 0x00000 53 #define BLD_BASE 0x01000 54 #define OVL_BASE(n) (0x02000 + (n) * 0x1000) 55 #define OVL_UI_BASE OVL_BASE(1) 56 57 /* GLB registers */ 58 #define GLB_CTL 0x000 59 #define GLB_CTL_EN __BIT(0) 60 #define GLB_STS 0x004 61 #define GLB_DBUFFER 0x008 62 #define GLB_DBUFFER_DOUBLE_BUFFER_RDY __BIT(0) 63 #define GLB_SIZE 0x00c 64 65 /* BLD registers */ 66 #define BLD_FILL_COLOR_CTL 0x000 67 #define BLD_FILL_COLOR_CTL_P0_EN __BIT(8) 68 #define BLD_CH_ISIZE(n) (0x008 + (n) * 0x10) 69 #define BLD_CH_OFFSET(n) (0x00c + (n) * 0x10) 70 #define BLD_CH_RTCTL 0x080 71 #define BLD_CH_RTCTL_P0 __BITS(3,0) 72 #define BLD_SIZE 0x08c 73 #define BLD_CTL(n) (0x090 + (n) * 0x04) 74 75 /* OVL_UI registers */ 76 #define OVL_UI_ATTR_CTL(n) (0x000 + (n) * 0x20) 77 #define OVL_UI_ATTR_CTL_LAY_FBFMT __BITS(12,8) 78 #define OVL_UI_ATTR_CTL_LAY_FBFMT_XRGB_8888 0x04 79 #define OVL_UI_ATTR_CTL_LAY_EN __BIT(0) 80 #define OVL_UI_MBSIZE(n) (0x004 + (n) * 0x20) 81 #define OVL_UI_COOR(n) (0x008 + (n) * 0x20) 82 #define OVL_UI_PITCH(n) (0x00c + (n) * 0x20) 83 #define OVL_UI_TOP_LADD(n) (0x010 + (n) * 0x20) 84 #define OVL_UI_TOP_HADD 0x080 85 #define OVL_UI_TOP_HADD_LAYER0 __BITS(7,0) 86 #define OVL_UI_SIZE 0x088 87 88 enum { 89 MIXER_PORT_OUTPUT = 1, 90 }; 91 92 static const char * const compatible[] = { 93 "allwinner,sun8i-h3-de2-mixer-0", 94 "allwinner,sun50i-a64-de2-mixer-0", 95 "allwinner,sun50i-a64-de2-mixer-1", 96 NULL 97 }; 98 99 struct sunxi_mixer_softc; 100 101 struct sunxi_mixer_crtc { 102 struct drm_crtc base; 103 struct sunxi_mixer_softc *sc; 104 }; 105 106 struct sunxi_mixer_softc { 107 device_t sc_dev; 108 bus_space_tag_t sc_bst; 109 bus_space_handle_t sc_bsh; 110 int sc_phandle; 111 112 struct sunxi_mixer_crtc sc_crtc; 113 114 struct fdt_device_ports sc_ports; 115 }; 116 117 #define GLB_READ(sc, reg) \ 118 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, GLB_BASE + (reg)) 119 #define GLB_WRITE(sc, reg, val) \ 120 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, GLB_BASE + (reg), (val)) 121 122 #define BLD_READ(sc, reg) \ 123 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, BLD_BASE + (reg)) 124 #define BLD_WRITE(sc, reg, val) \ 125 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, BLD_BASE + (reg), (val)) 126 127 #define OVL_UI_READ(sc, reg) \ 128 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, OVL_UI_BASE + (reg)) 129 #define OVL_UI_WRITE(sc, reg, val) \ 130 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, OVL_UI_BASE + (reg), (val)) 131 132 #define to_sunxi_mixer_crtc(x) container_of(x, struct sunxi_mixer_crtc, base) 133 134 static void 135 sunxi_mixer_destroy(struct drm_crtc *crtc) 136 { 137 drm_crtc_cleanup(crtc); 138 } 139 140 static const struct drm_crtc_funcs sunxi_mixer_crtc_funcs = { 141 .set_config = drm_crtc_helper_set_config, 142 .destroy = sunxi_mixer_destroy, 143 }; 144 145 static void 146 sunxi_mixer_dpms(struct drm_crtc *crtc, int mode) 147 { 148 } 149 150 static bool 151 sunxi_mixer_mode_fixup(struct drm_crtc *crtc, 152 const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) 153 { 154 return true; 155 } 156 157 static int 158 sunxi_mixer_mode_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, 159 int x, int y, int atomic) 160 { 161 struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc); 162 struct sunxi_mixer_softc * const sc = mixer_crtc->sc; 163 struct sunxi_drm_framebuffer *sfb = atomic? 164 to_sunxi_drm_framebuffer(fb) : 165 to_sunxi_drm_framebuffer(crtc->primary->fb); 166 167 uint64_t paddr = (uint64_t)sfb->obj->dmamap->dm_segs[0].ds_addr; 168 169 uint32_t haddr = (paddr >> 32) & OVL_UI_TOP_HADD_LAYER0; 170 uint32_t laddr = paddr & 0xffffffff; 171 172 /* Framebuffer start address */ 173 OVL_UI_WRITE(sc, OVL_UI_TOP_HADD, haddr); 174 OVL_UI_WRITE(sc, OVL_UI_TOP_LADD(0), laddr); 175 176 return 0; 177 } 178 179 static int 180 sunxi_mixer_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 181 struct drm_display_mode *adjusted_mode, int x, int y, 182 struct drm_framebuffer *old_fb) 183 { 184 struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc); 185 struct sunxi_mixer_softc * const sc = mixer_crtc->sc; 186 uint32_t val; 187 188 const uint32_t size = ((adjusted_mode->vdisplay - 1) << 16) | 189 (adjusted_mode->hdisplay - 1); 190 const uint32_t offset = (y << 16) | x; 191 192 /* Set global size */ 193 GLB_WRITE(sc, GLB_SIZE, size); 194 195 /* Enable pipe 0 */ 196 BLD_WRITE(sc, BLD_FILL_COLOR_CTL, BLD_FILL_COLOR_CTL_P0_EN); 197 198 /* Set blender 0 input size */ 199 BLD_WRITE(sc, BLD_CH_ISIZE(0), size); 200 /* Set blender 0 offset */ 201 BLD_WRITE(sc, BLD_CH_OFFSET(0), offset); 202 /* Route channel 1 to pipe 0 */ 203 BLD_WRITE(sc, BLD_CH_RTCTL, __SHIFTIN(1, BLD_CH_RTCTL_P0)); 204 /* Set blender output size */ 205 BLD_WRITE(sc, BLD_SIZE, size); 206 207 /* Enable UI overlay in XRGB8888 mode */ 208 val = OVL_UI_ATTR_CTL_LAY_EN | 209 __SHIFTIN(OVL_UI_ATTR_CTL_LAY_FBFMT_XRGB_8888, OVL_UI_ATTR_CTL_LAY_FBFMT); 210 OVL_UI_WRITE(sc, OVL_UI_ATTR_CTL(0), val); 211 /* Set UI overlay layer size */ 212 OVL_UI_WRITE(sc, OVL_UI_MBSIZE(0), size); 213 /* Set UI overlay offset */ 214 OVL_UI_WRITE(sc, OVL_UI_COOR(0), offset); 215 /* Set UI overlay line size */ 216 OVL_UI_WRITE(sc, OVL_UI_PITCH(0), adjusted_mode->hdisplay * 4); 217 /* Set UI overlay window size */ 218 OVL_UI_WRITE(sc, OVL_UI_SIZE, size); 219 220 sunxi_mixer_mode_do_set_base(crtc, old_fb, x, y, 0); 221 222 return 0; 223 } 224 225 static int 226 sunxi_mixer_mode_set_base(struct drm_crtc *crtc, int x, int y, 227 struct drm_framebuffer *old_fb) 228 { 229 struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc); 230 struct sunxi_mixer_softc * const sc = mixer_crtc->sc; 231 232 sunxi_mixer_mode_do_set_base(crtc, old_fb, x, y, 0); 233 234 /* Commit settings */ 235 GLB_WRITE(sc, GLB_DBUFFER, GLB_DBUFFER_DOUBLE_BUFFER_RDY); 236 237 return 0; 238 } 239 240 static int 241 sunxi_mixer_mode_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 242 int x, int y, enum mode_set_atomic state) 243 { 244 struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc); 245 struct sunxi_mixer_softc * const sc = mixer_crtc->sc; 246 247 sunxi_mixer_mode_do_set_base(crtc, fb, x, y, 1); 248 249 /* Commit settings */ 250 GLB_WRITE(sc, GLB_DBUFFER, GLB_DBUFFER_DOUBLE_BUFFER_RDY); 251 252 return 0; 253 } 254 255 static void 256 sunxi_mixer_disable(struct drm_crtc *crtc) 257 { 258 } 259 260 static void 261 sunxi_mixer_prepare(struct drm_crtc *crtc) 262 { 263 struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc); 264 struct sunxi_mixer_softc * const sc = mixer_crtc->sc; 265 266 /* RT enable */ 267 GLB_WRITE(sc, GLB_CTL, GLB_CTL_EN); 268 } 269 270 static void 271 sunxi_mixer_commit(struct drm_crtc *crtc) 272 { 273 struct sunxi_mixer_crtc *mixer_crtc = to_sunxi_mixer_crtc(crtc); 274 struct sunxi_mixer_softc * const sc = mixer_crtc->sc; 275 276 /* Commit settings */ 277 GLB_WRITE(sc, GLB_DBUFFER, GLB_DBUFFER_DOUBLE_BUFFER_RDY); 278 } 279 280 static const struct drm_crtc_helper_funcs sunxi_mixer_crtc_helper_funcs = { 281 .dpms = sunxi_mixer_dpms, 282 .mode_fixup = sunxi_mixer_mode_fixup, 283 .mode_set = sunxi_mixer_mode_set, 284 .mode_set_base = sunxi_mixer_mode_set_base, 285 .mode_set_base_atomic = sunxi_mixer_mode_set_base_atomic, 286 .disable = sunxi_mixer_disable, 287 .prepare = sunxi_mixer_prepare, 288 .commit = sunxi_mixer_commit, 289 }; 290 291 static int 292 sunxi_mixer_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 293 { 294 struct sunxi_mixer_softc * const sc = device_private(dev); 295 struct drm_device *ddev; 296 297 if (!activate) 298 return EINVAL; 299 300 ddev = sunxi_drm_endpoint_device(ep); 301 if (ddev == NULL) { 302 DRM_ERROR("couldn't find DRM device\n"); 303 return ENXIO; 304 } 305 306 sc->sc_crtc.sc = sc; 307 308 drm_crtc_init(ddev, &sc->sc_crtc.base, &sunxi_mixer_crtc_funcs); 309 drm_crtc_helper_add(&sc->sc_crtc.base, &sunxi_mixer_crtc_helper_funcs); 310 311 return fdt_endpoint_activate(ep, activate); 312 } 313 314 static void * 315 sunxi_mixer_ep_get_data(device_t dev, struct fdt_endpoint *ep) 316 { 317 struct sunxi_mixer_softc * const sc = device_private(dev); 318 319 return &sc->sc_crtc; 320 } 321 322 static int 323 sunxi_mixer_match(device_t parent, cfdata_t cf, void *aux) 324 { 325 struct fdt_attach_args * const faa = aux; 326 327 return of_match_compatible(faa->faa_phandle, compatible); 328 } 329 330 static void 331 sunxi_mixer_attach(device_t parent, device_t self, void *aux) 332 { 333 struct sunxi_mixer_softc * const sc = device_private(self); 334 struct fdt_attach_args * const faa = aux; 335 struct fdt_endpoint *out_ep; 336 const int phandle = faa->faa_phandle; 337 struct clk *clk_bus, *clk_mod; 338 struct fdtbus_reset *rst; 339 bus_addr_t addr; 340 bus_size_t size; 341 342 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 343 aprint_error(": couldn't get registers\n"); 344 return; 345 } 346 347 rst = fdtbus_reset_get_index(phandle, 0); 348 if (rst == NULL || fdtbus_reset_deassert(rst) != 0) { 349 aprint_error(": couldn't de-assert reset\n"); 350 return; 351 } 352 353 clk_bus = fdtbus_clock_get(phandle, "bus"); 354 if (clk_bus == NULL || clk_enable(clk_bus) != 0) { 355 aprint_error(": couldn't enable bus clock\n"); 356 return; 357 } 358 359 clk_mod = fdtbus_clock_get(phandle, "mod"); 360 if (clk_mod == NULL || 361 clk_set_rate(clk_mod, SUNXI_MIXER_FREQ) != 0 || 362 clk_enable(clk_mod) != 0) { 363 aprint_error(": couldn't enable mod clock\n"); 364 return; 365 } 366 367 sc->sc_dev = self; 368 sc->sc_bst = faa->faa_bst; 369 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 370 aprint_error(": couldn't map registers\n"); 371 return; 372 } 373 sc->sc_phandle = faa->faa_phandle; 374 375 aprint_naive("\n"); 376 aprint_normal(": Display Engine Mixer\n"); 377 378 sc->sc_ports.dp_ep_activate = sunxi_mixer_ep_activate; 379 sc->sc_ports.dp_ep_get_data = sunxi_mixer_ep_get_data; 380 fdt_ports_register(&sc->sc_ports, self, phandle, EP_DRM_CRTC); 381 382 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, MIXER_PORT_OUTPUT, 0); 383 if (out_ep != NULL) 384 sunxi_drm_register_endpoint(phandle, out_ep); 385 } 386 387 CFATTACH_DECL_NEW(sunxi_mixer, sizeof(struct sunxi_mixer_softc), 388 sunxi_mixer_match, sunxi_mixer_attach, NULL, NULL); 389
Indexes created Fri Sep 26 20:09:58 GMT 2025