sunxi_mmc.c revision 1.5.2.2
1 1.5.2.2 skrll /* $NetBSD: sunxi_mmc.c,v 1.5.2.2 2017/08/28 17:51:32 skrll Exp $ */ 2 1.5.2.2 skrll 3 1.5.2.2 skrll /*- 4 1.5.2.2 skrll * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 1.5.2.2 skrll * All rights reserved. 6 1.5.2.2 skrll * 7 1.5.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.5.2.2 skrll * modification, are permitted provided that the following conditions 9 1.5.2.2 skrll * are met: 10 1.5.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.5.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.5.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.5.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.5.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.5.2.2 skrll * 16 1.5.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.5.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.5.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.5.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.5.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.5.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.5.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.5.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.5.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.5.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.5.2.2 skrll * SUCH DAMAGE. 27 1.5.2.2 skrll */ 28 1.5.2.2 skrll 29 1.5.2.2 skrll #include <sys/cdefs.h> 30 1.5.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.5.2.2 2017/08/28 17:51:32 skrll Exp $"); 31 1.5.2.2 skrll 32 1.5.2.2 skrll #include <sys/param.h> 33 1.5.2.2 skrll #include <sys/bus.h> 34 1.5.2.2 skrll #include <sys/device.h> 35 1.5.2.2 skrll #include <sys/intr.h> 36 1.5.2.2 skrll #include <sys/systm.h> 37 1.5.2.2 skrll #include <sys/kernel.h> 38 1.5.2.2 skrll #include <sys/gpio.h> 39 1.5.2.2 skrll 40 1.5.2.2 skrll #include <dev/sdmmc/sdmmcvar.h> 41 1.5.2.2 skrll #include <dev/sdmmc/sdmmcchip.h> 42 1.5.2.2 skrll #include <dev/sdmmc/sdmmc_ioreg.h> 43 1.5.2.2 skrll 44 1.5.2.2 skrll #include <dev/fdt/fdtvar.h> 45 1.5.2.2 skrll 46 1.5.2.2 skrll #include <arm/sunxi/sunxi_mmc.h> 47 1.5.2.2 skrll 48 1.5.2.2 skrll enum sunxi_mmc_timing { 49 1.5.2.2 skrll SUNXI_MMC_TIMING_400K, 50 1.5.2.2 skrll SUNXI_MMC_TIMING_25M, 51 1.5.2.2 skrll SUNXI_MMC_TIMING_50M, 52 1.5.2.2 skrll SUNXI_MMC_TIMING_50M_DDR, 53 1.5.2.2 skrll SUNXI_MMC_TIMING_50M_DDR_8BIT, 54 1.5.2.2 skrll }; 55 1.5.2.2 skrll 56 1.5.2.2 skrll struct sunxi_mmc_delay { 57 1.5.2.2 skrll u_int output_phase; 58 1.5.2.2 skrll u_int sample_phase; 59 1.5.2.2 skrll }; 60 1.5.2.2 skrll 61 1.5.2.2 skrll static const struct sunxi_mmc_delay sunxi_mmc_delays[] = { 62 1.5.2.2 skrll [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 63 1.5.2.2 skrll [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 64 1.5.2.2 skrll [SUNXI_MMC_TIMING_50M] = { 90, 120 }, 65 1.5.2.2 skrll [SUNXI_MMC_TIMING_50M_DDR] = { 60, 120 }, 66 1.5.2.2 skrll [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 90, 180 }, 67 1.5.2.2 skrll }; 68 1.5.2.2 skrll 69 1.5.2.2 skrll #define SUNXI_MMC_NDESC 16 70 1.5.2.2 skrll #define SUNXI_MMC_DMA_XFERLEN 0x10000 71 1.5.2.2 skrll #define SUNXI_MMC_DMA_FTRGLEVEL 0x20070008 72 1.5.2.2 skrll 73 1.5.2.2 skrll struct sunxi_mmc_softc; 74 1.5.2.2 skrll 75 1.5.2.2 skrll static int sunxi_mmc_match(device_t, cfdata_t, void *); 76 1.5.2.2 skrll static void sunxi_mmc_attach(device_t, device_t, void *); 77 1.5.2.2 skrll static void sunxi_mmc_attach_i(device_t); 78 1.5.2.2 skrll 79 1.5.2.2 skrll static int sunxi_mmc_intr(void *); 80 1.5.2.2 skrll static int sunxi_mmc_idma_setup(struct sunxi_mmc_softc *); 81 1.5.2.2 skrll 82 1.5.2.2 skrll static int sunxi_mmc_host_reset(sdmmc_chipset_handle_t); 83 1.5.2.2 skrll static uint32_t sunxi_mmc_host_ocr(sdmmc_chipset_handle_t); 84 1.5.2.2 skrll static int sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t); 85 1.5.2.2 skrll static int sunxi_mmc_card_detect(sdmmc_chipset_handle_t); 86 1.5.2.2 skrll static int sunxi_mmc_write_protect(sdmmc_chipset_handle_t); 87 1.5.2.2 skrll static int sunxi_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 88 1.5.2.2 skrll static int sunxi_mmc_bus_clock(sdmmc_chipset_handle_t, int, bool); 89 1.5.2.2 skrll static int sunxi_mmc_bus_width(sdmmc_chipset_handle_t, int); 90 1.5.2.2 skrll static int sunxi_mmc_bus_rod(sdmmc_chipset_handle_t, int); 91 1.5.2.2 skrll static int sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 92 1.5.2.2 skrll static void sunxi_mmc_exec_command(sdmmc_chipset_handle_t, 93 1.5.2.2 skrll struct sdmmc_command *); 94 1.5.2.2 skrll static void sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 95 1.5.2.2 skrll static void sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t); 96 1.5.2.2 skrll 97 1.5.2.2 skrll static struct sdmmc_chip_functions sunxi_mmc_chip_functions = { 98 1.5.2.2 skrll .host_reset = sunxi_mmc_host_reset, 99 1.5.2.2 skrll .host_ocr = sunxi_mmc_host_ocr, 100 1.5.2.2 skrll .host_maxblklen = sunxi_mmc_host_maxblklen, 101 1.5.2.2 skrll .card_detect = sunxi_mmc_card_detect, 102 1.5.2.2 skrll .write_protect = sunxi_mmc_write_protect, 103 1.5.2.2 skrll .bus_power = sunxi_mmc_bus_power, 104 1.5.2.2 skrll .bus_clock_ddr = sunxi_mmc_bus_clock, 105 1.5.2.2 skrll .bus_width = sunxi_mmc_bus_width, 106 1.5.2.2 skrll .bus_rod = sunxi_mmc_bus_rod, 107 1.5.2.2 skrll .signal_voltage = sunxi_mmc_signal_voltage, 108 1.5.2.2 skrll .exec_command = sunxi_mmc_exec_command, 109 1.5.2.2 skrll .card_enable_intr = sunxi_mmc_card_enable_intr, 110 1.5.2.2 skrll .card_intr_ack = sunxi_mmc_card_intr_ack, 111 1.5.2.2 skrll }; 112 1.5.2.2 skrll 113 1.5.2.2 skrll struct sunxi_mmc_softc { 114 1.5.2.2 skrll device_t sc_dev; 115 1.5.2.2 skrll bus_space_tag_t sc_bst; 116 1.5.2.2 skrll bus_space_handle_t sc_bsh; 117 1.5.2.2 skrll bus_dma_tag_t sc_dmat; 118 1.5.2.2 skrll int sc_phandle; 119 1.5.2.2 skrll 120 1.5.2.2 skrll void *sc_ih; 121 1.5.2.2 skrll kmutex_t sc_intr_lock; 122 1.5.2.2 skrll kcondvar_t sc_intr_cv; 123 1.5.2.2 skrll kcondvar_t sc_idst_cv; 124 1.5.2.2 skrll 125 1.5.2.2 skrll int sc_mmc_width; 126 1.5.2.2 skrll int sc_mmc_present; 127 1.5.2.2 skrll 128 1.5.2.2 skrll device_t sc_sdmmc_dev; 129 1.5.2.2 skrll 130 1.5.2.2 skrll uint32_t sc_dma_ftrglevel; 131 1.5.2.2 skrll 132 1.5.2.2 skrll uint32_t sc_idma_xferlen; 133 1.5.2.2 skrll bus_dma_segment_t sc_idma_segs[1]; 134 1.5.2.2 skrll int sc_idma_nsegs; 135 1.5.2.2 skrll bus_size_t sc_idma_size; 136 1.5.2.2 skrll bus_dmamap_t sc_idma_map; 137 1.5.2.2 skrll int sc_idma_ndesc; 138 1.5.2.2 skrll void *sc_idma_desc; 139 1.5.2.2 skrll 140 1.5.2.2 skrll uint32_t sc_intr_rint; 141 1.5.2.2 skrll uint32_t sc_intr_mint; 142 1.5.2.2 skrll uint32_t sc_idma_idst; 143 1.5.2.2 skrll 144 1.5.2.2 skrll struct clk *sc_clk_ahb; 145 1.5.2.2 skrll struct clk *sc_clk_mmc; 146 1.5.2.2 skrll struct clk *sc_clk_output; 147 1.5.2.2 skrll struct clk *sc_clk_sample; 148 1.5.2.2 skrll 149 1.5.2.2 skrll struct fdtbus_reset *sc_rst_ahb; 150 1.5.2.2 skrll 151 1.5.2.2 skrll struct fdtbus_gpio_pin *sc_gpio_cd; 152 1.5.2.2 skrll int sc_gpio_cd_inverted; 153 1.5.2.2 skrll struct fdtbus_gpio_pin *sc_gpio_wp; 154 1.5.2.2 skrll int sc_gpio_wp_inverted; 155 1.5.2.2 skrll 156 1.5.2.2 skrll struct fdtbus_regulator *sc_reg_vqmmc; 157 1.5.2.2 skrll }; 158 1.5.2.2 skrll 159 1.5.2.2 skrll CFATTACH_DECL_NEW(sunxi_mmc, sizeof(struct sunxi_mmc_softc), 160 1.5.2.2 skrll sunxi_mmc_match, sunxi_mmc_attach, NULL, NULL); 161 1.5.2.2 skrll 162 1.5.2.2 skrll #define MMC_WRITE(sc, reg, val) \ 163 1.5.2.2 skrll bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 164 1.5.2.2 skrll #define MMC_READ(sc, reg) \ 165 1.5.2.2 skrll bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 166 1.5.2.2 skrll 167 1.5.2.2 skrll static const char * const compatible[] = { 168 1.5.2.2 skrll "allwinner,sun5i-a13-mmc", 169 1.5.2.2 skrll "allwinner,sun7i-a20-mmc", 170 1.5.2.2 skrll NULL 171 1.5.2.2 skrll }; 172 1.5.2.2 skrll 173 1.5.2.2 skrll static int 174 1.5.2.2 skrll sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux) 175 1.5.2.2 skrll { 176 1.5.2.2 skrll struct fdt_attach_args * const faa = aux; 177 1.5.2.2 skrll 178 1.5.2.2 skrll return of_match_compatible(faa->faa_phandle, compatible); 179 1.5.2.2 skrll } 180 1.5.2.2 skrll 181 1.5.2.2 skrll static void 182 1.5.2.2 skrll sunxi_mmc_attach(device_t parent, device_t self, void *aux) 183 1.5.2.2 skrll { 184 1.5.2.2 skrll struct sunxi_mmc_softc * const sc = device_private(self); 185 1.5.2.2 skrll struct fdt_attach_args * const faa = aux; 186 1.5.2.2 skrll const int phandle = faa->faa_phandle; 187 1.5.2.2 skrll char intrstr[128]; 188 1.5.2.2 skrll bus_addr_t addr; 189 1.5.2.2 skrll bus_size_t size; 190 1.5.2.2 skrll 191 1.5.2.2 skrll if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 192 1.5.2.2 skrll aprint_error(": couldn't get registers\n"); 193 1.5.2.2 skrll return; 194 1.5.2.2 skrll } 195 1.5.2.2 skrll 196 1.5.2.2 skrll sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 197 1.5.2.2 skrll sc->sc_clk_mmc = fdtbus_clock_get(phandle, "mmc"); 198 1.5.2.2 skrll sc->sc_clk_output = fdtbus_clock_get(phandle, "output"); 199 1.5.2.2 skrll sc->sc_clk_sample = fdtbus_clock_get(phandle, "sample"); 200 1.5.2.2 skrll 201 1.5.2.2 skrll #if notyet 202 1.5.2.2 skrll if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL || 203 1.5.2.2 skrll sc->sc_clk_output == NULL || sc->sc_clk_sample == NULL) { 204 1.5.2.2 skrll #else 205 1.5.2.2 skrll if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL) { 206 1.5.2.2 skrll #endif 207 1.5.2.2 skrll aprint_error(": couldn't get clocks\n"); 208 1.5.2.2 skrll return; 209 1.5.2.2 skrll } 210 1.5.2.2 skrll 211 1.5.2.2 skrll sc->sc_rst_ahb = fdtbus_reset_get(phandle, "ahb"); 212 1.5.2.2 skrll if (sc->sc_rst_ahb == NULL) { 213 1.5.2.2 skrll aprint_error(": couldn't get resets\n"); 214 1.5.2.2 skrll return; 215 1.5.2.2 skrll } 216 1.5.2.2 skrll 217 1.5.2.2 skrll sc->sc_reg_vqmmc = fdtbus_regulator_acquire(phandle, "vqmmc-supply"); 218 1.5.2.2 skrll 219 1.5.2.2 skrll if (clk_enable(sc->sc_clk_ahb) != 0 || 220 1.5.2.2 skrll clk_enable(sc->sc_clk_mmc) != 0) { 221 1.5.2.2 skrll aprint_error(": couldn't enable clocks\n"); 222 1.5.2.2 skrll return; 223 1.5.2.2 skrll } 224 1.5.2.2 skrll 225 1.5.2.2 skrll if (fdtbus_reset_deassert(sc->sc_rst_ahb) != 0) { 226 1.5.2.2 skrll aprint_error(": couldn't de-assert resets\n"); 227 1.5.2.2 skrll return; 228 1.5.2.2 skrll } 229 1.5.2.2 skrll 230 1.5.2.2 skrll sc->sc_dev = self; 231 1.5.2.2 skrll sc->sc_phandle = phandle; 232 1.5.2.2 skrll sc->sc_bst = faa->faa_bst; 233 1.5.2.2 skrll sc->sc_dmat = faa->faa_dmat; 234 1.5.2.2 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 235 1.5.2.2 skrll cv_init(&sc->sc_intr_cv, "awinmmcirq"); 236 1.5.2.2 skrll cv_init(&sc->sc_idst_cv, "awinmmcdma"); 237 1.5.2.2 skrll 238 1.5.2.2 skrll if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 239 1.5.2.2 skrll aprint_error(": couldn't map registers\n"); 240 1.5.2.2 skrll return; 241 1.5.2.2 skrll } 242 1.5.2.2 skrll 243 1.5.2.2 skrll aprint_naive("\n"); 244 1.5.2.2 skrll aprint_normal(": SD/MMC controller\n"); 245 1.5.2.2 skrll 246 1.5.2.2 skrll sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 247 1.5.2.2 skrll GPIO_PIN_INPUT); 248 1.5.2.2 skrll sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 249 1.5.2.2 skrll GPIO_PIN_INPUT); 250 1.5.2.2 skrll 251 1.5.2.2 skrll sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 0 : 1; 252 1.5.2.2 skrll sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 0 : 1; 253 1.5.2.2 skrll 254 1.5.2.2 skrll sc->sc_dma_ftrglevel = SUNXI_MMC_DMA_FTRGLEVEL; 255 1.5.2.2 skrll 256 1.5.2.2 skrll if (sunxi_mmc_idma_setup(sc) != 0) { 257 1.5.2.2 skrll aprint_error_dev(self, "failed to setup DMA\n"); 258 1.5.2.2 skrll return; 259 1.5.2.2 skrll } 260 1.5.2.2 skrll 261 1.5.2.2 skrll if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 262 1.5.2.2 skrll aprint_error_dev(self, "failed to decode interrupt\n"); 263 1.5.2.2 skrll return; 264 1.5.2.2 skrll } 265 1.5.2.2 skrll 266 1.5.2.2 skrll sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, FDT_INTR_MPSAFE, 267 1.5.2.2 skrll sunxi_mmc_intr, sc); 268 1.5.2.2 skrll if (sc->sc_ih == NULL) { 269 1.5.2.2 skrll aprint_error_dev(self, "failed to establish interrupt on %s\n", 270 1.5.2.2 skrll intrstr); 271 1.5.2.2 skrll return; 272 1.5.2.2 skrll } 273 1.5.2.2 skrll aprint_normal_dev(self, "interrupting on %s\n", intrstr); 274 1.5.2.2 skrll 275 1.5.2.2 skrll config_interrupts(self, sunxi_mmc_attach_i); 276 1.5.2.2 skrll } 277 1.5.2.2 skrll 278 1.5.2.2 skrll static int 279 1.5.2.2 skrll sunxi_mmc_idma_setup(struct sunxi_mmc_softc *sc) 280 1.5.2.2 skrll { 281 1.5.2.2 skrll int error; 282 1.5.2.2 skrll 283 1.5.2.2 skrll sc->sc_idma_xferlen = SUNXI_MMC_DMA_XFERLEN; 284 1.5.2.2 skrll 285 1.5.2.2 skrll sc->sc_idma_ndesc = SUNXI_MMC_NDESC; 286 1.5.2.2 skrll sc->sc_idma_size = sizeof(struct sunxi_mmc_idma_descriptor) * 287 1.5.2.2 skrll sc->sc_idma_ndesc; 288 1.5.2.2 skrll error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 0, 289 1.5.2.2 skrll sc->sc_idma_size, sc->sc_idma_segs, 1, 290 1.5.2.2 skrll &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 291 1.5.2.2 skrll if (error) 292 1.5.2.2 skrll return error; 293 1.5.2.2 skrll error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 294 1.5.2.2 skrll sc->sc_idma_nsegs, sc->sc_idma_size, 295 1.5.2.2 skrll &sc->sc_idma_desc, BUS_DMA_WAITOK); 296 1.5.2.2 skrll if (error) 297 1.5.2.2 skrll goto free; 298 1.5.2.2 skrll error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 299 1.5.2.2 skrll sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 300 1.5.2.2 skrll if (error) 301 1.5.2.2 skrll goto unmap; 302 1.5.2.2 skrll error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 303 1.5.2.2 skrll sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 304 1.5.2.2 skrll if (error) 305 1.5.2.2 skrll goto destroy; 306 1.5.2.2 skrll return 0; 307 1.5.2.2 skrll 308 1.5.2.2 skrll destroy: 309 1.5.2.2 skrll bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 310 1.5.2.2 skrll unmap: 311 1.5.2.2 skrll bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 312 1.5.2.2 skrll free: 313 1.5.2.2 skrll bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 314 1.5.2.2 skrll return error; 315 1.5.2.2 skrll } 316 1.5.2.2 skrll 317 1.5.2.2 skrll static int 318 1.5.2.2 skrll sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr) 319 1.5.2.2 skrll { 320 1.5.2.2 skrll const struct sunxi_mmc_delay *delays; 321 1.5.2.2 skrll int error, timing; 322 1.5.2.2 skrll 323 1.5.2.2 skrll if (freq <= 400) { 324 1.5.2.2 skrll timing = SUNXI_MMC_TIMING_400K; 325 1.5.2.2 skrll } else if (freq <= 25000) { 326 1.5.2.2 skrll timing = SUNXI_MMC_TIMING_25M; 327 1.5.2.2 skrll } else if (freq <= 52000) { 328 1.5.2.2 skrll if (ddr) { 329 1.5.2.2 skrll timing = sc->sc_mmc_width == 8 ? 330 1.5.2.2 skrll SUNXI_MMC_TIMING_50M_DDR_8BIT : 331 1.5.2.2 skrll SUNXI_MMC_TIMING_50M_DDR; 332 1.5.2.2 skrll } else { 333 1.5.2.2 skrll timing = SUNXI_MMC_TIMING_50M; 334 1.5.2.2 skrll } 335 1.5.2.2 skrll } else 336 1.5.2.2 skrll return EINVAL; 337 1.5.2.2 skrll 338 1.5.2.2 skrll delays = &sunxi_mmc_delays[timing]; 339 1.5.2.2 skrll 340 1.5.2.2 skrll error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << ddr); 341 1.5.2.2 skrll if (error != 0) 342 1.5.2.2 skrll return error; 343 1.5.2.2 skrll 344 1.5.2.2 skrll if (sc->sc_clk_sample) { 345 1.5.2.2 skrll error = clk_set_rate(sc->sc_clk_sample, delays->sample_phase); 346 1.5.2.2 skrll if (error != 0) 347 1.5.2.2 skrll return error; 348 1.5.2.2 skrll } 349 1.5.2.2 skrll if (sc->sc_clk_output) { 350 1.5.2.2 skrll error = clk_set_rate(sc->sc_clk_output, delays->output_phase); 351 1.5.2.2 skrll if (error != 0) 352 1.5.2.2 skrll return error; 353 1.5.2.2 skrll } 354 1.5.2.2 skrll 355 1.5.2.2 skrll return 0; 356 1.5.2.2 skrll } 357 1.5.2.2 skrll 358 1.5.2.2 skrll static void 359 1.5.2.2 skrll sunxi_mmc_attach_i(device_t self) 360 1.5.2.2 skrll { 361 1.5.2.2 skrll struct sunxi_mmc_softc *sc = device_private(self); 362 1.5.2.2 skrll struct sdmmcbus_attach_args saa; 363 1.5.2.2 skrll uint32_t width; 364 1.5.2.2 skrll 365 1.5.2.2 skrll sunxi_mmc_host_reset(sc); 366 1.5.2.2 skrll sunxi_mmc_bus_width(sc, 1); 367 1.5.2.2 skrll sunxi_mmc_set_clock(sc, 400, false); 368 1.5.2.2 skrll 369 1.5.2.2 skrll if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 370 1.5.2.2 skrll width = 4; 371 1.5.2.2 skrll 372 1.5.2.2 skrll memset(&saa, 0, sizeof(saa)); 373 1.5.2.2 skrll saa.saa_busname = "sdmmc"; 374 1.5.2.2 skrll saa.saa_sct = &sunxi_mmc_chip_functions; 375 1.5.2.2 skrll saa.saa_sch = sc; 376 1.5.2.2 skrll saa.saa_dmat = sc->sc_dmat; 377 1.5.2.2 skrll saa.saa_clkmin = 400; 378 1.5.2.2 skrll saa.saa_clkmax = 52000; 379 1.5.2.2 skrll saa.saa_caps = SMC_CAPS_DMA | 380 1.5.2.2 skrll SMC_CAPS_MULTI_SEG_DMA | 381 1.5.2.2 skrll SMC_CAPS_AUTO_STOP | 382 1.5.2.2 skrll SMC_CAPS_SD_HIGHSPEED | 383 1.5.2.2 skrll SMC_CAPS_MMC_HIGHSPEED | 384 1.5.2.2 skrll SMC_CAPS_MMC_DDR52 | 385 1.5.2.2 skrll SMC_CAPS_POLLING; 386 1.5.2.2 skrll if (width == 4) 387 1.5.2.2 skrll saa.saa_caps |= SMC_CAPS_4BIT_MODE; 388 1.5.2.2 skrll if (width == 8) 389 1.5.2.2 skrll saa.saa_caps |= SMC_CAPS_8BIT_MODE; 390 1.5.2.2 skrll 391 1.5.2.2 skrll if (sc->sc_gpio_cd) 392 1.5.2.2 skrll saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 393 1.5.2.2 skrll 394 1.5.2.2 skrll sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 395 1.5.2.2 skrll } 396 1.5.2.2 skrll 397 1.5.2.2 skrll static int 398 1.5.2.2 skrll sunxi_mmc_intr(void *priv) 399 1.5.2.2 skrll { 400 1.5.2.2 skrll struct sunxi_mmc_softc *sc = priv; 401 1.5.2.2 skrll uint32_t idst, rint, mint; 402 1.5.2.2 skrll 403 1.5.2.2 skrll mutex_enter(&sc->sc_intr_lock); 404 1.5.2.2 skrll idst = MMC_READ(sc, SUNXI_MMC_IDST); 405 1.5.2.2 skrll rint = MMC_READ(sc, SUNXI_MMC_RINT); 406 1.5.2.2 skrll mint = MMC_READ(sc, SUNXI_MMC_MINT); 407 1.5.2.2 skrll if (!idst && !rint && !mint) { 408 1.5.2.2 skrll mutex_exit(&sc->sc_intr_lock); 409 1.5.2.2 skrll return 0; 410 1.5.2.2 skrll } 411 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_IDST, idst); 412 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_RINT, rint); 413 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_MINT, mint); 414 1.5.2.2 skrll 415 1.5.2.2 skrll #ifdef SUNXI_MMC_DEBUG 416 1.5.2.2 skrll device_printf(sc->sc_dev, "mmc intr idst=%08X rint=%08X mint=%08X\n", 417 1.5.2.2 skrll idst, rint, mint); 418 1.5.2.2 skrll #endif 419 1.5.2.2 skrll 420 1.5.2.2 skrll if (idst) { 421 1.5.2.2 skrll sc->sc_idma_idst |= idst; 422 1.5.2.2 skrll cv_broadcast(&sc->sc_idst_cv); 423 1.5.2.2 skrll } 424 1.5.2.2 skrll 425 1.5.2.2 skrll if (rint) { 426 1.5.2.2 skrll sc->sc_intr_rint |= rint; 427 1.5.2.2 skrll cv_broadcast(&sc->sc_intr_cv); 428 1.5.2.2 skrll } 429 1.5.2.2 skrll 430 1.5.2.2 skrll mutex_exit(&sc->sc_intr_lock); 431 1.5.2.2 skrll 432 1.5.2.2 skrll return 1; 433 1.5.2.2 skrll } 434 1.5.2.2 skrll 435 1.5.2.2 skrll static int 436 1.5.2.2 skrll sunxi_mmc_wait_rint(struct sunxi_mmc_softc *sc, uint32_t mask, 437 1.5.2.2 skrll int timeout, bool poll) 438 1.5.2.2 skrll { 439 1.5.2.2 skrll int retry; 440 1.5.2.2 skrll int error; 441 1.5.2.2 skrll 442 1.5.2.2 skrll KASSERT(mutex_owned(&sc->sc_intr_lock)); 443 1.5.2.2 skrll 444 1.5.2.2 skrll if (sc->sc_intr_rint & mask) 445 1.5.2.2 skrll return 0; 446 1.5.2.2 skrll 447 1.5.2.2 skrll if (poll) 448 1.5.2.2 skrll retry = timeout / hz * 1000; 449 1.5.2.2 skrll else 450 1.5.2.2 skrll retry = timeout / hz; 451 1.5.2.2 skrll 452 1.5.2.2 skrll while (retry > 0) { 453 1.5.2.2 skrll if (poll) { 454 1.5.2.2 skrll sc->sc_intr_rint |= MMC_READ(sc, SUNXI_MMC_RINT); 455 1.5.2.2 skrll } else { 456 1.5.2.2 skrll error = cv_timedwait(&sc->sc_intr_cv, 457 1.5.2.2 skrll &sc->sc_intr_lock, hz); 458 1.5.2.2 skrll if (error && error != EWOULDBLOCK) 459 1.5.2.2 skrll return error; 460 1.5.2.2 skrll } 461 1.5.2.2 skrll if (sc->sc_intr_rint & mask) 462 1.5.2.2 skrll return 0; 463 1.5.2.2 skrll if (poll) 464 1.5.2.2 skrll delay(1000); 465 1.5.2.2 skrll --retry; 466 1.5.2.2 skrll } 467 1.5.2.2 skrll 468 1.5.2.2 skrll return ETIMEDOUT; 469 1.5.2.2 skrll } 470 1.5.2.2 skrll 471 1.5.2.2 skrll static int 472 1.5.2.2 skrll sunxi_mmc_host_reset(sdmmc_chipset_handle_t sch) 473 1.5.2.2 skrll { 474 1.5.2.2 skrll struct sunxi_mmc_softc *sc = sch; 475 1.5.2.2 skrll int retry = 1000; 476 1.5.2.2 skrll 477 1.5.2.2 skrll #ifdef SUNXI_MMC_DEBUG 478 1.5.2.2 skrll aprint_normal_dev(sc->sc_dev, "host reset\n"); 479 1.5.2.2 skrll #endif 480 1.5.2.2 skrll 481 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_GCTRL, 482 1.5.2.2 skrll MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_RESET); 483 1.5.2.2 skrll while (--retry > 0) { 484 1.5.2.2 skrll if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 485 1.5.2.2 skrll break; 486 1.5.2.2 skrll delay(100); 487 1.5.2.2 skrll } 488 1.5.2.2 skrll 489 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_TIMEOUT, 0xffffffff); 490 1.5.2.2 skrll 491 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_IMASK, 492 1.5.2.2 skrll SUNXI_MMC_INT_CMD_DONE | SUNXI_MMC_INT_ERROR | 493 1.5.2.2 skrll SUNXI_MMC_INT_DATA_OVER | SUNXI_MMC_INT_AUTO_CMD_DONE); 494 1.5.2.2 skrll 495 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_GCTRL, 496 1.5.2.2 skrll MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_INTEN); 497 1.5.2.2 skrll 498 1.5.2.2 skrll return 0; 499 1.5.2.2 skrll } 500 1.5.2.2 skrll 501 1.5.2.2 skrll static uint32_t 502 1.5.2.2 skrll sunxi_mmc_host_ocr(sdmmc_chipset_handle_t sch) 503 1.5.2.2 skrll { 504 1.5.2.2 skrll return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 505 1.5.2.2 skrll } 506 1.5.2.2 skrll 507 1.5.2.2 skrll static int 508 1.5.2.2 skrll sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 509 1.5.2.2 skrll { 510 1.5.2.2 skrll return 8192; 511 1.5.2.2 skrll } 512 1.5.2.2 skrll 513 1.5.2.2 skrll static int 514 1.5.2.2 skrll sunxi_mmc_card_detect(sdmmc_chipset_handle_t sch) 515 1.5.2.2 skrll { 516 1.5.2.2 skrll struct sunxi_mmc_softc *sc = sch; 517 1.5.2.2 skrll 518 1.5.2.2 skrll if (sc->sc_gpio_cd == NULL) { 519 1.5.2.2 skrll return 1; /* no card detect pin, assume present */ 520 1.5.2.2 skrll } else { 521 1.5.2.2 skrll int v = 0, i; 522 1.5.2.2 skrll for (i = 0; i < 5; i++) { 523 1.5.2.2 skrll v += (fdtbus_gpio_read(sc->sc_gpio_cd) ^ 524 1.5.2.2 skrll sc->sc_gpio_cd_inverted); 525 1.5.2.2 skrll delay(1000); 526 1.5.2.2 skrll } 527 1.5.2.2 skrll if (v == 5) 528 1.5.2.2 skrll sc->sc_mmc_present = 0; 529 1.5.2.2 skrll else if (v == 0) 530 1.5.2.2 skrll sc->sc_mmc_present = 1; 531 1.5.2.2 skrll return sc->sc_mmc_present; 532 1.5.2.2 skrll } 533 1.5.2.2 skrll } 534 1.5.2.2 skrll 535 1.5.2.2 skrll static int 536 1.5.2.2 skrll sunxi_mmc_write_protect(sdmmc_chipset_handle_t sch) 537 1.5.2.2 skrll { 538 1.5.2.2 skrll struct sunxi_mmc_softc *sc = sch; 539 1.5.2.2 skrll 540 1.5.2.2 skrll if (sc->sc_gpio_wp == NULL) { 541 1.5.2.2 skrll return 0; /* no write protect pin, assume rw */ 542 1.5.2.2 skrll } else { 543 1.5.2.2 skrll return fdtbus_gpio_read(sc->sc_gpio_wp) ^ 544 1.5.2.2 skrll sc->sc_gpio_wp_inverted; 545 1.5.2.2 skrll } 546 1.5.2.2 skrll } 547 1.5.2.2 skrll 548 1.5.2.2 skrll static int 549 1.5.2.2 skrll sunxi_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 550 1.5.2.2 skrll { 551 1.5.2.2 skrll return 0; 552 1.5.2.2 skrll } 553 1.5.2.2 skrll 554 1.5.2.2 skrll static int 555 1.5.2.2 skrll sunxi_mmc_update_clock(struct sunxi_mmc_softc *sc) 556 1.5.2.2 skrll { 557 1.5.2.2 skrll uint32_t cmd; 558 1.5.2.2 skrll int retry; 559 1.5.2.2 skrll 560 1.5.2.2 skrll #ifdef SUNXI_MMC_DEBUG 561 1.5.2.2 skrll aprint_normal_dev(sc->sc_dev, "update clock\n"); 562 1.5.2.2 skrll #endif 563 1.5.2.2 skrll 564 1.5.2.2 skrll cmd = SUNXI_MMC_CMD_START | 565 1.5.2.2 skrll SUNXI_MMC_CMD_UPCLK_ONLY | 566 1.5.2.2 skrll SUNXI_MMC_CMD_WAIT_PRE_OVER; 567 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_CMD, cmd); 568 1.5.2.2 skrll retry = 0xfffff; 569 1.5.2.2 skrll while (--retry > 0) { 570 1.5.2.2 skrll if (!(MMC_READ(sc, SUNXI_MMC_CMD) & SUNXI_MMC_CMD_START)) 571 1.5.2.2 skrll break; 572 1.5.2.2 skrll delay(10); 573 1.5.2.2 skrll } 574 1.5.2.2 skrll 575 1.5.2.2 skrll if (retry == 0) { 576 1.5.2.2 skrll aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 577 1.5.2.2 skrll #ifdef SUNXI_MMC_DEBUG 578 1.5.2.2 skrll device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 579 1.5.2.2 skrll MMC_READ(sc, SUNXI_MMC_GCTRL)); 580 1.5.2.2 skrll device_printf(sc->sc_dev, "CLKCR: 0x%08x\n", 581 1.5.2.2 skrll MMC_READ(sc, SUNXI_MMC_CLKCR)); 582 1.5.2.2 skrll device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 583 1.5.2.2 skrll MMC_READ(sc, SUNXI_MMC_TIMEOUT)); 584 1.5.2.2 skrll device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 585 1.5.2.2 skrll MMC_READ(sc, SUNXI_MMC_WIDTH)); 586 1.5.2.2 skrll device_printf(sc->sc_dev, "CMD: 0x%08x\n", 587 1.5.2.2 skrll MMC_READ(sc, SUNXI_MMC_CMD)); 588 1.5.2.2 skrll device_printf(sc->sc_dev, "MINT: 0x%08x\n", 589 1.5.2.2 skrll MMC_READ(sc, SUNXI_MMC_MINT)); 590 1.5.2.2 skrll device_printf(sc->sc_dev, "RINT: 0x%08x\n", 591 1.5.2.2 skrll MMC_READ(sc, SUNXI_MMC_RINT)); 592 1.5.2.2 skrll device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 593 1.5.2.2 skrll MMC_READ(sc, SUNXI_MMC_STATUS)); 594 1.5.2.2 skrll #endif 595 1.5.2.2 skrll return ETIMEDOUT; 596 1.5.2.2 skrll } 597 1.5.2.2 skrll 598 1.5.2.2 skrll return 0; 599 1.5.2.2 skrll } 600 1.5.2.2 skrll 601 1.5.2.2 skrll static int 602 1.5.2.2 skrll sunxi_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 603 1.5.2.2 skrll { 604 1.5.2.2 skrll struct sunxi_mmc_softc *sc = sch; 605 1.5.2.2 skrll uint32_t clkcr, gctrl; 606 1.5.2.2 skrll 607 1.5.2.2 skrll clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 608 1.5.2.2 skrll if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) { 609 1.5.2.2 skrll clkcr &= ~SUNXI_MMC_CLKCR_CARDCLKON; 610 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 611 1.5.2.2 skrll if (sunxi_mmc_update_clock(sc) != 0) 612 1.5.2.2 skrll return 1; 613 1.5.2.2 skrll } 614 1.5.2.2 skrll 615 1.5.2.2 skrll if (freq) { 616 1.5.2.2 skrll 617 1.5.2.2 skrll clkcr &= ~SUNXI_MMC_CLKCR_DIV; 618 1.5.2.2 skrll clkcr |= __SHIFTIN(ddr, SUNXI_MMC_CLKCR_DIV); 619 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 620 1.5.2.2 skrll if (sunxi_mmc_update_clock(sc) != 0) 621 1.5.2.2 skrll return 1; 622 1.5.2.2 skrll 623 1.5.2.2 skrll gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 624 1.5.2.2 skrll if (ddr) 625 1.5.2.2 skrll gctrl |= SUNXI_MMC_GCTRL_DDR_MODE; 626 1.5.2.2 skrll else 627 1.5.2.2 skrll gctrl &= ~SUNXI_MMC_GCTRL_DDR_MODE; 628 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 629 1.5.2.2 skrll 630 1.5.2.2 skrll if (sunxi_mmc_set_clock(sc, freq, ddr) != 0) 631 1.5.2.2 skrll return 1; 632 1.5.2.2 skrll 633 1.5.2.2 skrll clkcr |= SUNXI_MMC_CLKCR_CARDCLKON; 634 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 635 1.5.2.2 skrll if (sunxi_mmc_update_clock(sc) != 0) 636 1.5.2.2 skrll return 1; 637 1.5.2.2 skrll } 638 1.5.2.2 skrll 639 1.5.2.2 skrll return 0; 640 1.5.2.2 skrll } 641 1.5.2.2 skrll 642 1.5.2.2 skrll static int 643 1.5.2.2 skrll sunxi_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 644 1.5.2.2 skrll { 645 1.5.2.2 skrll struct sunxi_mmc_softc *sc = sch; 646 1.5.2.2 skrll 647 1.5.2.2 skrll #ifdef SUNXI_MMC_DEBUG 648 1.5.2.2 skrll aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 649 1.5.2.2 skrll #endif 650 1.5.2.2 skrll 651 1.5.2.2 skrll switch (width) { 652 1.5.2.2 skrll case 1: 653 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_1); 654 1.5.2.2 skrll break; 655 1.5.2.2 skrll case 4: 656 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_4); 657 1.5.2.2 skrll break; 658 1.5.2.2 skrll case 8: 659 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_8); 660 1.5.2.2 skrll break; 661 1.5.2.2 skrll default: 662 1.5.2.2 skrll return 1; 663 1.5.2.2 skrll } 664 1.5.2.2 skrll 665 1.5.2.2 skrll sc->sc_mmc_width = width; 666 1.5.2.2 skrll 667 1.5.2.2 skrll return 0; 668 1.5.2.2 skrll } 669 1.5.2.2 skrll 670 1.5.2.2 skrll static int 671 1.5.2.2 skrll sunxi_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 672 1.5.2.2 skrll { 673 1.5.2.2 skrll return -1; 674 1.5.2.2 skrll } 675 1.5.2.2 skrll 676 1.5.2.2 skrll static int 677 1.5.2.2 skrll sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 678 1.5.2.2 skrll { 679 1.5.2.2 skrll struct sunxi_mmc_softc *sc = sch; 680 1.5.2.2 skrll u_int uvol; 681 1.5.2.2 skrll int error; 682 1.5.2.2 skrll 683 1.5.2.2 skrll if (sc->sc_reg_vqmmc == NULL) 684 1.5.2.2 skrll return 0; 685 1.5.2.2 skrll 686 1.5.2.2 skrll switch (signal_voltage) { 687 1.5.2.2 skrll case SDMMC_SIGNAL_VOLTAGE_330: 688 1.5.2.2 skrll uvol = 3300000; 689 1.5.2.2 skrll break; 690 1.5.2.2 skrll case SDMMC_SIGNAL_VOLTAGE_180: 691 1.5.2.2 skrll uvol = 1800000; 692 1.5.2.2 skrll break; 693 1.5.2.2 skrll default: 694 1.5.2.2 skrll return EINVAL; 695 1.5.2.2 skrll } 696 1.5.2.2 skrll 697 1.5.2.2 skrll error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 698 1.5.2.2 skrll if (error != 0) 699 1.5.2.2 skrll return error; 700 1.5.2.2 skrll 701 1.5.2.2 skrll return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 702 1.5.2.2 skrll } 703 1.5.2.2 skrll 704 1.5.2.2 skrll static int 705 1.5.2.2 skrll sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 706 1.5.2.2 skrll { 707 1.5.2.2 skrll struct sunxi_mmc_idma_descriptor *dma = sc->sc_idma_desc; 708 1.5.2.2 skrll bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 709 1.5.2.2 skrll bus_size_t off; 710 1.5.2.2 skrll int desc, resid, seg; 711 1.5.2.2 skrll uint32_t val; 712 1.5.2.2 skrll 713 1.5.2.2 skrll desc = 0; 714 1.5.2.2 skrll for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 715 1.5.2.2 skrll bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr; 716 1.5.2.2 skrll bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 717 1.5.2.2 skrll resid = min(len, cmd->c_resid); 718 1.5.2.2 skrll off = 0; 719 1.5.2.2 skrll while (resid > 0) { 720 1.5.2.2 skrll if (desc == sc->sc_idma_ndesc) 721 1.5.2.2 skrll break; 722 1.5.2.2 skrll len = min(sc->sc_idma_xferlen, resid); 723 1.5.2.2 skrll dma[desc].dma_buf_size = htole32(len); 724 1.5.2.2 skrll dma[desc].dma_buf_addr = htole32(paddr + off); 725 1.5.2.2 skrll dma[desc].dma_config = htole32(SUNXI_MMC_IDMA_CONFIG_CH | 726 1.5.2.2 skrll SUNXI_MMC_IDMA_CONFIG_OWN); 727 1.5.2.2 skrll cmd->c_resid -= len; 728 1.5.2.2 skrll resid -= len; 729 1.5.2.2 skrll off += len; 730 1.5.2.2 skrll if (desc == 0) { 731 1.5.2.2 skrll dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_FD); 732 1.5.2.2 skrll } 733 1.5.2.2 skrll if (cmd->c_resid == 0) { 734 1.5.2.2 skrll dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_LD); 735 1.5.2.2 skrll dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_ER); 736 1.5.2.2 skrll dma[desc].dma_next = 0; 737 1.5.2.2 skrll } else { 738 1.5.2.2 skrll dma[desc].dma_config |= 739 1.5.2.2 skrll htole32(SUNXI_MMC_IDMA_CONFIG_DIC); 740 1.5.2.2 skrll dma[desc].dma_next = htole32( 741 1.5.2.2 skrll desc_paddr + ((desc+1) * 742 1.5.2.2 skrll sizeof(struct sunxi_mmc_idma_descriptor))); 743 1.5.2.2 skrll } 744 1.5.2.2 skrll ++desc; 745 1.5.2.2 skrll } 746 1.5.2.2 skrll } 747 1.5.2.2 skrll if (desc == sc->sc_idma_ndesc) { 748 1.5.2.2 skrll aprint_error_dev(sc->sc_dev, 749 1.5.2.2 skrll "not enough descriptors for %d byte transfer!\n", 750 1.5.2.2 skrll cmd->c_datalen); 751 1.5.2.2 skrll return EIO; 752 1.5.2.2 skrll } 753 1.5.2.2 skrll 754 1.5.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 755 1.5.2.2 skrll sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 756 1.5.2.2 skrll 757 1.5.2.2 skrll sc->sc_idma_idst = 0; 758 1.5.2.2 skrll 759 1.5.2.2 skrll val = MMC_READ(sc, SUNXI_MMC_GCTRL); 760 1.5.2.2 skrll val |= SUNXI_MMC_GCTRL_DMAEN; 761 1.5.2.2 skrll val |= SUNXI_MMC_GCTRL_INTEN; 762 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 763 1.5.2.2 skrll val |= SUNXI_MMC_GCTRL_DMARESET; 764 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 765 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_DMAC, SUNXI_MMC_DMAC_SOFTRESET); 766 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_DMAC, 767 1.5.2.2 skrll SUNXI_MMC_DMAC_IDMA_ON|SUNXI_MMC_DMAC_FIX_BURST); 768 1.5.2.2 skrll val = MMC_READ(sc, SUNXI_MMC_IDIE); 769 1.5.2.2 skrll val &= ~(SUNXI_MMC_IDST_RECEIVE_INT|SUNXI_MMC_IDST_TRANSMIT_INT); 770 1.5.2.2 skrll if (cmd->c_flags & SCF_CMD_READ) 771 1.5.2.2 skrll val |= SUNXI_MMC_IDST_RECEIVE_INT; 772 1.5.2.2 skrll else 773 1.5.2.2 skrll val |= SUNXI_MMC_IDST_TRANSMIT_INT; 774 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_IDIE, val); 775 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_DLBA, desc_paddr); 776 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_FTRGLEVEL, sc->sc_dma_ftrglevel); 777 1.5.2.2 skrll 778 1.5.2.2 skrll return 0; 779 1.5.2.2 skrll } 780 1.5.2.2 skrll 781 1.5.2.2 skrll static void 782 1.5.2.2 skrll sunxi_mmc_dma_complete(struct sunxi_mmc_softc *sc) 783 1.5.2.2 skrll { 784 1.5.2.2 skrll bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 785 1.5.2.2 skrll sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 786 1.5.2.2 skrll } 787 1.5.2.2 skrll 788 1.5.2.2 skrll static void 789 1.5.2.2 skrll sunxi_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 790 1.5.2.2 skrll { 791 1.5.2.2 skrll struct sunxi_mmc_softc *sc = sch; 792 1.5.2.2 skrll uint32_t cmdval = SUNXI_MMC_CMD_START; 793 1.5.2.2 skrll const bool poll = (cmd->c_flags & SCF_POLL) != 0; 794 1.5.2.2 skrll int retry; 795 1.5.2.2 skrll 796 1.5.2.2 skrll #ifdef SUNXI_MMC_DEBUG 797 1.5.2.2 skrll aprint_normal_dev(sc->sc_dev, 798 1.5.2.2 skrll "opcode %d flags 0x%x data %p datalen %d blklen %d poll %d\n", 799 1.5.2.2 skrll cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 800 1.5.2.2 skrll cmd->c_blklen, poll); 801 1.5.2.2 skrll #endif 802 1.5.2.2 skrll 803 1.5.2.2 skrll mutex_enter(&sc->sc_intr_lock); 804 1.5.2.2 skrll 805 1.5.2.2 skrll if (cmd->c_opcode == 0) 806 1.5.2.2 skrll cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 807 1.5.2.2 skrll if (cmd->c_flags & SCF_RSP_PRESENT) 808 1.5.2.2 skrll cmdval |= SUNXI_MMC_CMD_RSP_EXP; 809 1.5.2.2 skrll if (cmd->c_flags & SCF_RSP_136) 810 1.5.2.2 skrll cmdval |= SUNXI_MMC_CMD_LONG_RSP; 811 1.5.2.2 skrll if (cmd->c_flags & SCF_RSP_CRC) 812 1.5.2.2 skrll cmdval |= SUNXI_MMC_CMD_CHECK_RSP_CRC; 813 1.5.2.2 skrll 814 1.5.2.2 skrll if (cmd->c_datalen > 0) { 815 1.5.2.2 skrll unsigned int nblks; 816 1.5.2.2 skrll 817 1.5.2.2 skrll cmdval |= SUNXI_MMC_CMD_DATA_EXP | SUNXI_MMC_CMD_WAIT_PRE_OVER; 818 1.5.2.2 skrll if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 819 1.5.2.2 skrll cmdval |= SUNXI_MMC_CMD_WRITE; 820 1.5.2.2 skrll } 821 1.5.2.2 skrll 822 1.5.2.2 skrll nblks = cmd->c_datalen / cmd->c_blklen; 823 1.5.2.2 skrll if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 824 1.5.2.2 skrll ++nblks; 825 1.5.2.2 skrll 826 1.5.2.2 skrll if (nblks > 1) { 827 1.5.2.2 skrll cmdval |= SUNXI_MMC_CMD_SEND_AUTO_STOP; 828 1.5.2.2 skrll } 829 1.5.2.2 skrll 830 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_BLKSZ, cmd->c_blklen); 831 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_BYTECNT, nblks * cmd->c_blklen); 832 1.5.2.2 skrll } 833 1.5.2.2 skrll 834 1.5.2.2 skrll sc->sc_intr_rint = 0; 835 1.5.2.2 skrll 836 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_A12A, 837 1.5.2.2 skrll (cmdval & SUNXI_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff); 838 1.5.2.2 skrll 839 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_ARG, cmd->c_arg); 840 1.5.2.2 skrll 841 1.5.2.2 skrll #ifdef SUNXI_MMC_DEBUG 842 1.5.2.2 skrll aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 843 1.5.2.2 skrll #endif 844 1.5.2.2 skrll 845 1.5.2.2 skrll if (cmd->c_datalen == 0) { 846 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 847 1.5.2.2 skrll } else { 848 1.5.2.2 skrll cmd->c_resid = cmd->c_datalen; 849 1.5.2.2 skrll cmd->c_error = sunxi_mmc_dma_prepare(sc, cmd); 850 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 851 1.5.2.2 skrll if (cmd->c_error == 0) { 852 1.5.2.2 skrll const uint32_t idst_mask = 853 1.5.2.2 skrll SUNXI_MMC_IDST_ERROR | SUNXI_MMC_IDST_COMPLETE; 854 1.5.2.2 skrll retry = 10; 855 1.5.2.2 skrll while ((sc->sc_idma_idst & idst_mask) == 0) { 856 1.5.2.2 skrll if (retry-- == 0) { 857 1.5.2.2 skrll cmd->c_error = ETIMEDOUT; 858 1.5.2.2 skrll break; 859 1.5.2.2 skrll } 860 1.5.2.2 skrll cv_timedwait(&sc->sc_idst_cv, 861 1.5.2.2 skrll &sc->sc_intr_lock, hz); 862 1.5.2.2 skrll } 863 1.5.2.2 skrll } 864 1.5.2.2 skrll sunxi_mmc_dma_complete(sc); 865 1.5.2.2 skrll if (sc->sc_idma_idst & SUNXI_MMC_IDST_ERROR) { 866 1.5.2.2 skrll cmd->c_error = EIO; 867 1.5.2.2 skrll } else if (!(sc->sc_idma_idst & SUNXI_MMC_IDST_COMPLETE)) { 868 1.5.2.2 skrll cmd->c_error = ETIMEDOUT; 869 1.5.2.2 skrll } 870 1.5.2.2 skrll if (cmd->c_error) { 871 1.5.2.2 skrll #ifdef SUNXI_MMC_DEBUG 872 1.5.2.2 skrll aprint_error_dev(sc->sc_dev, 873 1.5.2.2 skrll "xfer failed, error %d\n", cmd->c_error); 874 1.5.2.2 skrll #endif 875 1.5.2.2 skrll goto done; 876 1.5.2.2 skrll } 877 1.5.2.2 skrll } 878 1.5.2.2 skrll 879 1.5.2.2 skrll cmd->c_error = sunxi_mmc_wait_rint(sc, 880 1.5.2.2 skrll SUNXI_MMC_INT_ERROR|SUNXI_MMC_INT_CMD_DONE, hz * 10, poll); 881 1.5.2.2 skrll if (cmd->c_error == 0 && (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 882 1.5.2.2 skrll if (sc->sc_intr_rint & SUNXI_MMC_INT_RESP_TIMEOUT) { 883 1.5.2.2 skrll cmd->c_error = ETIMEDOUT; 884 1.5.2.2 skrll } else { 885 1.5.2.2 skrll cmd->c_error = EIO; 886 1.5.2.2 skrll } 887 1.5.2.2 skrll } 888 1.5.2.2 skrll if (cmd->c_error) { 889 1.5.2.2 skrll #ifdef SUNXI_MMC_DEBUG 890 1.5.2.2 skrll aprint_error_dev(sc->sc_dev, 891 1.5.2.2 skrll "cmd failed, error %d\n", cmd->c_error); 892 1.5.2.2 skrll #endif 893 1.5.2.2 skrll goto done; 894 1.5.2.2 skrll } 895 1.5.2.2 skrll 896 1.5.2.2 skrll if (cmd->c_datalen > 0) { 897 1.5.2.2 skrll cmd->c_error = sunxi_mmc_wait_rint(sc, 898 1.5.2.2 skrll SUNXI_MMC_INT_ERROR| 899 1.5.2.2 skrll SUNXI_MMC_INT_AUTO_CMD_DONE| 900 1.5.2.2 skrll SUNXI_MMC_INT_DATA_OVER, 901 1.5.2.2 skrll hz*10, poll); 902 1.5.2.2 skrll if (cmd->c_error == 0 && 903 1.5.2.2 skrll (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 904 1.5.2.2 skrll cmd->c_error = ETIMEDOUT; 905 1.5.2.2 skrll } 906 1.5.2.2 skrll if (cmd->c_error) { 907 1.5.2.2 skrll #ifdef SUNXI_MMC_DEBUG 908 1.5.2.2 skrll aprint_error_dev(sc->sc_dev, 909 1.5.2.2 skrll "data timeout, rint = %08x\n", 910 1.5.2.2 skrll sc->sc_intr_rint); 911 1.5.2.2 skrll #endif 912 1.5.2.2 skrll cmd->c_error = ETIMEDOUT; 913 1.5.2.2 skrll goto done; 914 1.5.2.2 skrll } 915 1.5.2.2 skrll } 916 1.5.2.2 skrll 917 1.5.2.2 skrll if (cmd->c_flags & SCF_RSP_PRESENT) { 918 1.5.2.2 skrll if (cmd->c_flags & SCF_RSP_136) { 919 1.5.2.2 skrll cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 920 1.5.2.2 skrll cmd->c_resp[1] = MMC_READ(sc, SUNXI_MMC_RESP1); 921 1.5.2.2 skrll cmd->c_resp[2] = MMC_READ(sc, SUNXI_MMC_RESP2); 922 1.5.2.2 skrll cmd->c_resp[3] = MMC_READ(sc, SUNXI_MMC_RESP3); 923 1.5.2.2 skrll if (cmd->c_flags & SCF_RSP_CRC) { 924 1.5.2.2 skrll cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 925 1.5.2.2 skrll (cmd->c_resp[1] << 24); 926 1.5.2.2 skrll cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 927 1.5.2.2 skrll (cmd->c_resp[2] << 24); 928 1.5.2.2 skrll cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 929 1.5.2.2 skrll (cmd->c_resp[3] << 24); 930 1.5.2.2 skrll cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 931 1.5.2.2 skrll } 932 1.5.2.2 skrll } else { 933 1.5.2.2 skrll cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 934 1.5.2.2 skrll } 935 1.5.2.2 skrll } 936 1.5.2.2 skrll 937 1.5.2.2 skrll done: 938 1.5.2.2 skrll cmd->c_flags |= SCF_ITSDONE; 939 1.5.2.2 skrll mutex_exit(&sc->sc_intr_lock); 940 1.5.2.2 skrll 941 1.5.2.2 skrll if (cmd->c_error) { 942 1.5.2.2 skrll #ifdef SUNXI_MMC_DEBUG 943 1.5.2.2 skrll aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 944 1.5.2.2 skrll #endif 945 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_GCTRL, 946 1.5.2.2 skrll MMC_READ(sc, SUNXI_MMC_GCTRL) | 947 1.5.2.2 skrll SUNXI_MMC_GCTRL_DMARESET | SUNXI_MMC_GCTRL_FIFORESET); 948 1.5.2.2 skrll for (retry = 0; retry < 1000; retry++) { 949 1.5.2.2 skrll if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 950 1.5.2.2 skrll break; 951 1.5.2.2 skrll delay(10); 952 1.5.2.2 skrll } 953 1.5.2.2 skrll sunxi_mmc_update_clock(sc); 954 1.5.2.2 skrll } 955 1.5.2.2 skrll 956 1.5.2.2 skrll MMC_WRITE(sc, SUNXI_MMC_GCTRL, 957 1.5.2.2 skrll MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_FIFORESET); 958 1.5.2.2 skrll } 959 1.5.2.2 skrll 960 1.5.2.2 skrll static void 961 1.5.2.2 skrll sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 962 1.5.2.2 skrll { 963 1.5.2.2 skrll } 964 1.5.2.2 skrll 965 1.5.2.2 skrll static void 966 1.5.2.2 skrll sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 967 1.5.2.2 skrll { 968 1.5.2.2 skrll } 969
Indexes created Mon Nov 03 10:09:51 GMT 2025