sunxi_mmc.c revision 1.10
1 /* $NetBSD: sunxi_mmc.c,v 1.10 2017/10/08 18:00:36 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.10 2017/10/08 18:00:36 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/gpio.h> 39 40 #include <dev/sdmmc/sdmmcvar.h> 41 #include <dev/sdmmc/sdmmcchip.h> 42 #include <dev/sdmmc/sdmmc_ioreg.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/sunxi/sunxi_mmc.h> 47 48 enum sunxi_mmc_timing { 49 SUNXI_MMC_TIMING_400K, 50 SUNXI_MMC_TIMING_25M, 51 SUNXI_MMC_TIMING_50M, 52 SUNXI_MMC_TIMING_50M_DDR, 53 SUNXI_MMC_TIMING_50M_DDR_8BIT, 54 }; 55 56 struct sunxi_mmc_delay { 57 u_int output_phase; 58 u_int sample_phase; 59 }; 60 61 static const struct sunxi_mmc_delay sun7i_mmc_delays[] = { 62 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 63 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 64 [SUNXI_MMC_TIMING_50M] = { 90, 120 }, 65 [SUNXI_MMC_TIMING_50M_DDR] = { 60, 120 }, 66 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 90, 180 }, 67 }; 68 69 static const struct sunxi_mmc_delay sun9i_mmc_delays[] = { 70 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 71 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 72 [SUNXI_MMC_TIMING_50M] = { 150, 120 }, 73 [SUNXI_MMC_TIMING_50M_DDR] = { 54, 36 }, 74 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 72, 72 }, 75 }; 76 77 #define SUNXI_MMC_NDESC 16 78 79 struct sunxi_mmc_softc; 80 81 static int sunxi_mmc_match(device_t, cfdata_t, void *); 82 static void sunxi_mmc_attach(device_t, device_t, void *); 83 static void sunxi_mmc_attach_i(device_t); 84 85 static int sunxi_mmc_intr(void *); 86 static int sunxi_mmc_idma_setup(struct sunxi_mmc_softc *); 87 88 static int sunxi_mmc_host_reset(sdmmc_chipset_handle_t); 89 static uint32_t sunxi_mmc_host_ocr(sdmmc_chipset_handle_t); 90 static int sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t); 91 static int sunxi_mmc_card_detect(sdmmc_chipset_handle_t); 92 static int sunxi_mmc_write_protect(sdmmc_chipset_handle_t); 93 static int sunxi_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 94 static int sunxi_mmc_bus_clock(sdmmc_chipset_handle_t, int, bool); 95 static int sunxi_mmc_bus_width(sdmmc_chipset_handle_t, int); 96 static int sunxi_mmc_bus_rod(sdmmc_chipset_handle_t, int); 97 static int sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 98 static void sunxi_mmc_exec_command(sdmmc_chipset_handle_t, 99 struct sdmmc_command *); 100 static void sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 101 static void sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t); 102 103 static struct sdmmc_chip_functions sunxi_mmc_chip_functions = { 104 .host_reset = sunxi_mmc_host_reset, 105 .host_ocr = sunxi_mmc_host_ocr, 106 .host_maxblklen = sunxi_mmc_host_maxblklen, 107 .card_detect = sunxi_mmc_card_detect, 108 .write_protect = sunxi_mmc_write_protect, 109 .bus_power = sunxi_mmc_bus_power, 110 .bus_clock_ddr = sunxi_mmc_bus_clock, 111 .bus_width = sunxi_mmc_bus_width, 112 .bus_rod = sunxi_mmc_bus_rod, 113 .signal_voltage = sunxi_mmc_signal_voltage, 114 .exec_command = sunxi_mmc_exec_command, 115 .card_enable_intr = sunxi_mmc_card_enable_intr, 116 .card_intr_ack = sunxi_mmc_card_intr_ack, 117 }; 118 119 struct sunxi_mmc_config { 120 u_int idma_xferlen; 121 u_int flags; 122 #define SUNXI_MMC_FLAG_CALIB_REG 0x01 123 #define SUNXI_MMC_FLAG_NEW_TIMINGS 0x02 124 #define SUNXI_MMC_FLAG_MASK_DATA0 0x04 125 const struct sunxi_mmc_delay *delays; 126 uint32_t dma_ftrglevel; 127 }; 128 129 struct sunxi_mmc_softc { 130 device_t sc_dev; 131 bus_space_tag_t sc_bst; 132 bus_space_handle_t sc_bsh; 133 bus_dma_tag_t sc_dmat; 134 int sc_phandle; 135 136 void *sc_ih; 137 kmutex_t sc_intr_lock; 138 kcondvar_t sc_intr_cv; 139 kcondvar_t sc_idst_cv; 140 141 int sc_mmc_width; 142 int sc_mmc_present; 143 144 device_t sc_sdmmc_dev; 145 146 struct sunxi_mmc_config *sc_config; 147 148 bus_dma_segment_t sc_idma_segs[1]; 149 int sc_idma_nsegs; 150 bus_size_t sc_idma_size; 151 bus_dmamap_t sc_idma_map; 152 int sc_idma_ndesc; 153 void *sc_idma_desc; 154 155 uint32_t sc_intr_rint; 156 uint32_t sc_intr_mint; 157 uint32_t sc_idma_idst; 158 159 struct clk *sc_clk_ahb; 160 struct clk *sc_clk_mmc; 161 struct clk *sc_clk_output; 162 struct clk *sc_clk_sample; 163 164 struct fdtbus_reset *sc_rst_ahb; 165 166 struct fdtbus_gpio_pin *sc_gpio_cd; 167 int sc_gpio_cd_inverted; 168 struct fdtbus_gpio_pin *sc_gpio_wp; 169 int sc_gpio_wp_inverted; 170 171 struct fdtbus_regulator *sc_reg_vqmmc; 172 }; 173 174 CFATTACH_DECL_NEW(sunxi_mmc, sizeof(struct sunxi_mmc_softc), 175 sunxi_mmc_match, sunxi_mmc_attach, NULL, NULL); 176 177 #define MMC_WRITE(sc, reg, val) \ 178 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 179 #define MMC_READ(sc, reg) \ 180 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 181 182 static const struct sunxi_mmc_config sun4i_a10_mmc_config = { 183 .idma_xferlen = 0x2000, 184 .dma_ftrglevel = 0x20070008, 185 .delays = NULL, 186 .flags = 0, 187 }; 188 189 static const struct sunxi_mmc_config sun5i_a13_mmc_config = { 190 .idma_xferlen = 0x10000, 191 .dma_ftrglevel = 0x20070008, 192 .delays = NULL, 193 .flags = 0, 194 }; 195 196 static const struct sunxi_mmc_config sun7i_a20_mmc_config = { 197 .idma_xferlen = 0x2000, 198 .dma_ftrglevel = 0x20070008, 199 .delays = sun7i_mmc_delays, 200 .flags = 0, 201 }; 202 203 static const struct sunxi_mmc_config sun9i_a80_mmc_config = { 204 .idma_xferlen = 0x10000, 205 .dma_ftrglevel = 0x200f0010, 206 .delays = sun9i_mmc_delays, 207 .flags = 0, 208 }; 209 210 static const struct sunxi_mmc_config sun50i_a64_mmc_config = { 211 .idma_xferlen = 0x10000, 212 .dma_ftrglevel = 0x20070008, 213 .delays = NULL, 214 .flags = SUNXI_MMC_FLAG_CALIB_REG | 215 SUNXI_MMC_FLAG_NEW_TIMINGS | 216 SUNXI_MMC_FLAG_MASK_DATA0, 217 }; 218 219 static const struct of_compat_data compat_data[] = { 220 { "allwinner,sun4i-a10-mmc", (uintptr_t)&sun4i_a10_mmc_config }, 221 { "allwinner,sun5i-a13-mmc", (uintptr_t)&sun5i_a13_mmc_config }, 222 { "allwinner,sun7i-a20-mmc", (uintptr_t)&sun7i_a20_mmc_config }, 223 { "allwinner,sun9i-a80-mmc", (uintptr_t)&sun9i_a80_mmc_config }, 224 { "allwinner,sun50i-a64-mmc", (uintptr_t)&sun50i_a64_mmc_config }, 225 { NULL } 226 }; 227 228 static int 229 sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux) 230 { 231 struct fdt_attach_args * const faa = aux; 232 233 return of_match_compat_data(faa->faa_phandle, compat_data); 234 } 235 236 static void 237 sunxi_mmc_attach(device_t parent, device_t self, void *aux) 238 { 239 struct sunxi_mmc_softc * const sc = device_private(self); 240 struct fdt_attach_args * const faa = aux; 241 const int phandle = faa->faa_phandle; 242 char intrstr[128]; 243 bus_addr_t addr; 244 bus_size_t size; 245 246 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 247 aprint_error(": couldn't get registers\n"); 248 return; 249 } 250 251 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 252 sc->sc_clk_mmc = fdtbus_clock_get(phandle, "mmc"); 253 sc->sc_clk_output = fdtbus_clock_get(phandle, "output"); 254 sc->sc_clk_sample = fdtbus_clock_get(phandle, "sample"); 255 256 #if notyet 257 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL || 258 sc->sc_clk_output == NULL || sc->sc_clk_sample == NULL) { 259 #else 260 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL) { 261 #endif 262 aprint_error(": couldn't get clocks\n"); 263 return; 264 } 265 266 sc->sc_rst_ahb = fdtbus_reset_get(phandle, "ahb"); 267 268 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(phandle, "vqmmc-supply"); 269 270 if (clk_enable(sc->sc_clk_ahb) != 0 || 271 clk_enable(sc->sc_clk_mmc) != 0) { 272 aprint_error(": couldn't enable clocks\n"); 273 return; 274 } 275 276 if (sc->sc_rst_ahb != NULL) { 277 if (fdtbus_reset_deassert(sc->sc_rst_ahb) != 0) { 278 aprint_error(": couldn't de-assert resets\n"); 279 return; 280 } 281 } 282 283 sc->sc_dev = self; 284 sc->sc_phandle = phandle; 285 sc->sc_config = (void *)of_search_compatible(phandle, compat_data)->data; 286 sc->sc_bst = faa->faa_bst; 287 sc->sc_dmat = faa->faa_dmat; 288 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 289 cv_init(&sc->sc_intr_cv, "awinmmcirq"); 290 cv_init(&sc->sc_idst_cv, "awinmmcdma"); 291 292 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 293 aprint_error(": couldn't map registers\n"); 294 return; 295 } 296 297 aprint_naive("\n"); 298 aprint_normal(": SD/MMC controller\n"); 299 300 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 301 GPIO_PIN_INPUT); 302 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 303 GPIO_PIN_INPUT); 304 305 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 0 : 1; 306 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 0 : 1; 307 308 if (sunxi_mmc_idma_setup(sc) != 0) { 309 aprint_error_dev(self, "failed to setup DMA\n"); 310 return; 311 } 312 313 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 314 aprint_error_dev(self, "failed to decode interrupt\n"); 315 return; 316 } 317 318 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, FDT_INTR_MPSAFE, 319 sunxi_mmc_intr, sc); 320 if (sc->sc_ih == NULL) { 321 aprint_error_dev(self, "failed to establish interrupt on %s\n", 322 intrstr); 323 return; 324 } 325 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 326 327 config_interrupts(self, sunxi_mmc_attach_i); 328 } 329 330 static int 331 sunxi_mmc_idma_setup(struct sunxi_mmc_softc *sc) 332 { 333 int error; 334 335 sc->sc_idma_ndesc = SUNXI_MMC_NDESC; 336 sc->sc_idma_size = sizeof(struct sunxi_mmc_idma_descriptor) * 337 sc->sc_idma_ndesc; 338 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 0, 339 sc->sc_idma_size, sc->sc_idma_segs, 1, 340 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 341 if (error) 342 return error; 343 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 344 sc->sc_idma_nsegs, sc->sc_idma_size, 345 &sc->sc_idma_desc, BUS_DMA_WAITOK); 346 if (error) 347 goto free; 348 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 349 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 350 if (error) 351 goto unmap; 352 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 353 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 354 if (error) 355 goto destroy; 356 return 0; 357 358 destroy: 359 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 360 unmap: 361 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 362 free: 363 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 364 return error; 365 } 366 367 static int 368 sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr) 369 { 370 const struct sunxi_mmc_delay *delays; 371 int error, timing; 372 373 if (freq <= 400) { 374 timing = SUNXI_MMC_TIMING_400K; 375 } else if (freq <= 25000) { 376 timing = SUNXI_MMC_TIMING_25M; 377 } else if (freq <= 52000) { 378 if (ddr) { 379 timing = sc->sc_mmc_width == 8 ? 380 SUNXI_MMC_TIMING_50M_DDR_8BIT : 381 SUNXI_MMC_TIMING_50M_DDR; 382 } else { 383 timing = SUNXI_MMC_TIMING_50M; 384 } 385 } else 386 return EINVAL; 387 388 error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << ddr); 389 if (error != 0) 390 return error; 391 392 if (sc->sc_config->delays == NULL) 393 return 0; 394 395 delays = &sc->sc_config->delays[timing]; 396 397 if (sc->sc_clk_sample) { 398 error = clk_set_rate(sc->sc_clk_sample, delays->sample_phase); 399 if (error != 0) 400 return error; 401 } 402 if (sc->sc_clk_output) { 403 error = clk_set_rate(sc->sc_clk_output, delays->output_phase); 404 if (error != 0) 405 return error; 406 } 407 408 return 0; 409 } 410 411 static void 412 sunxi_mmc_attach_i(device_t self) 413 { 414 struct sunxi_mmc_softc *sc = device_private(self); 415 struct sdmmcbus_attach_args saa; 416 uint32_t width; 417 418 sunxi_mmc_host_reset(sc); 419 sunxi_mmc_bus_width(sc, 1); 420 sunxi_mmc_set_clock(sc, 400, false); 421 422 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 423 width = 4; 424 425 memset(&saa, 0, sizeof(saa)); 426 saa.saa_busname = "sdmmc"; 427 saa.saa_sct = &sunxi_mmc_chip_functions; 428 saa.saa_sch = sc; 429 saa.saa_dmat = sc->sc_dmat; 430 saa.saa_clkmin = 400; 431 saa.saa_clkmax = 52000; 432 saa.saa_caps = SMC_CAPS_DMA | 433 SMC_CAPS_MULTI_SEG_DMA | 434 SMC_CAPS_AUTO_STOP | 435 SMC_CAPS_SD_HIGHSPEED | 436 SMC_CAPS_MMC_HIGHSPEED | 437 SMC_CAPS_MMC_DDR52 | 438 SMC_CAPS_POLLING; 439 if (width == 4) 440 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 441 if (width == 8) 442 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 443 444 if (sc->sc_gpio_cd) 445 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 446 447 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 448 } 449 450 static int 451 sunxi_mmc_intr(void *priv) 452 { 453 struct sunxi_mmc_softc *sc = priv; 454 uint32_t idst, rint, mint; 455 456 mutex_enter(&sc->sc_intr_lock); 457 idst = MMC_READ(sc, SUNXI_MMC_IDST); 458 rint = MMC_READ(sc, SUNXI_MMC_RINT); 459 mint = MMC_READ(sc, SUNXI_MMC_MINT); 460 if (!idst && !rint && !mint) { 461 mutex_exit(&sc->sc_intr_lock); 462 return 0; 463 } 464 MMC_WRITE(sc, SUNXI_MMC_IDST, idst); 465 MMC_WRITE(sc, SUNXI_MMC_RINT, rint); 466 MMC_WRITE(sc, SUNXI_MMC_MINT, mint); 467 468 #ifdef SUNXI_MMC_DEBUG 469 device_printf(sc->sc_dev, "mmc intr idst=%08X rint=%08X mint=%08X\n", 470 idst, rint, mint); 471 #endif 472 473 if (idst) { 474 sc->sc_idma_idst |= idst; 475 cv_broadcast(&sc->sc_idst_cv); 476 } 477 478 if (rint) { 479 sc->sc_intr_rint |= rint; 480 cv_broadcast(&sc->sc_intr_cv); 481 } 482 483 mutex_exit(&sc->sc_intr_lock); 484 485 return 1; 486 } 487 488 static int 489 sunxi_mmc_wait_rint(struct sunxi_mmc_softc *sc, uint32_t mask, 490 int timeout, bool poll) 491 { 492 int retry; 493 int error; 494 495 KASSERT(mutex_owned(&sc->sc_intr_lock)); 496 497 if (sc->sc_intr_rint & mask) 498 return 0; 499 500 if (poll) 501 retry = timeout / hz * 1000; 502 else 503 retry = timeout / hz; 504 505 while (retry > 0) { 506 if (poll) { 507 sc->sc_intr_rint |= MMC_READ(sc, SUNXI_MMC_RINT); 508 } else { 509 error = cv_timedwait(&sc->sc_intr_cv, 510 &sc->sc_intr_lock, hz); 511 if (error && error != EWOULDBLOCK) 512 return error; 513 } 514 if (sc->sc_intr_rint & mask) 515 return 0; 516 if (poll) 517 delay(1000); 518 --retry; 519 } 520 521 return ETIMEDOUT; 522 } 523 524 static int 525 sunxi_mmc_host_reset(sdmmc_chipset_handle_t sch) 526 { 527 struct sunxi_mmc_softc *sc = sch; 528 int retry = 1000; 529 530 #ifdef SUNXI_MMC_DEBUG 531 aprint_normal_dev(sc->sc_dev, "host reset\n"); 532 #endif 533 534 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 535 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_RESET); 536 while (--retry > 0) { 537 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 538 break; 539 delay(100); 540 } 541 542 MMC_WRITE(sc, SUNXI_MMC_TIMEOUT, 0xffffffff); 543 544 MMC_WRITE(sc, SUNXI_MMC_IMASK, 545 SUNXI_MMC_INT_CMD_DONE | SUNXI_MMC_INT_ERROR | 546 SUNXI_MMC_INT_DATA_OVER | SUNXI_MMC_INT_AUTO_CMD_DONE); 547 548 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 549 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_INTEN); 550 551 return 0; 552 } 553 554 static uint32_t 555 sunxi_mmc_host_ocr(sdmmc_chipset_handle_t sch) 556 { 557 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 558 } 559 560 static int 561 sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 562 { 563 return 8192; 564 } 565 566 static int 567 sunxi_mmc_card_detect(sdmmc_chipset_handle_t sch) 568 { 569 struct sunxi_mmc_softc *sc = sch; 570 571 if (sc->sc_gpio_cd == NULL) { 572 return 1; /* no card detect pin, assume present */ 573 } else { 574 int v = 0, i; 575 for (i = 0; i < 5; i++) { 576 v += (fdtbus_gpio_read(sc->sc_gpio_cd) ^ 577 sc->sc_gpio_cd_inverted); 578 delay(1000); 579 } 580 if (v == 5) 581 sc->sc_mmc_present = 0; 582 else if (v == 0) 583 sc->sc_mmc_present = 1; 584 return sc->sc_mmc_present; 585 } 586 } 587 588 static int 589 sunxi_mmc_write_protect(sdmmc_chipset_handle_t sch) 590 { 591 struct sunxi_mmc_softc *sc = sch; 592 593 if (sc->sc_gpio_wp == NULL) { 594 return 0; /* no write protect pin, assume rw */ 595 } else { 596 return fdtbus_gpio_read(sc->sc_gpio_wp) ^ 597 sc->sc_gpio_wp_inverted; 598 } 599 } 600 601 static int 602 sunxi_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 603 { 604 return 0; 605 } 606 607 static int 608 sunxi_mmc_update_clock(struct sunxi_mmc_softc *sc) 609 { 610 uint32_t cmd; 611 int retry; 612 613 #ifdef SUNXI_MMC_DEBUG 614 aprint_normal_dev(sc->sc_dev, "update clock\n"); 615 #endif 616 617 cmd = SUNXI_MMC_CMD_START | 618 SUNXI_MMC_CMD_UPCLK_ONLY | 619 SUNXI_MMC_CMD_WAIT_PRE_OVER; 620 MMC_WRITE(sc, SUNXI_MMC_CMD, cmd); 621 retry = 0xfffff; 622 while (--retry > 0) { 623 if (!(MMC_READ(sc, SUNXI_MMC_CMD) & SUNXI_MMC_CMD_START)) 624 break; 625 delay(10); 626 } 627 628 if (retry == 0) { 629 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 630 #ifdef SUNXI_MMC_DEBUG 631 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 632 MMC_READ(sc, SUNXI_MMC_GCTRL)); 633 device_printf(sc->sc_dev, "CLKCR: 0x%08x\n", 634 MMC_READ(sc, SUNXI_MMC_CLKCR)); 635 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 636 MMC_READ(sc, SUNXI_MMC_TIMEOUT)); 637 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 638 MMC_READ(sc, SUNXI_MMC_WIDTH)); 639 device_printf(sc->sc_dev, "CMD: 0x%08x\n", 640 MMC_READ(sc, SUNXI_MMC_CMD)); 641 device_printf(sc->sc_dev, "MINT: 0x%08x\n", 642 MMC_READ(sc, SUNXI_MMC_MINT)); 643 device_printf(sc->sc_dev, "RINT: 0x%08x\n", 644 MMC_READ(sc, SUNXI_MMC_RINT)); 645 device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 646 MMC_READ(sc, SUNXI_MMC_STATUS)); 647 #endif 648 return ETIMEDOUT; 649 } 650 651 return 0; 652 } 653 654 static int 655 sunxi_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 656 { 657 struct sunxi_mmc_softc *sc = sch; 658 uint32_t clkcr, gctrl, ntsr; 659 const u_int flags = sc->sc_config->flags; 660 661 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 662 if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) { 663 clkcr &= ~SUNXI_MMC_CLKCR_CARDCLKON; 664 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 665 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 666 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 667 if (sunxi_mmc_update_clock(sc) != 0) 668 return 1; 669 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 670 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 671 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 672 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 673 } 674 } 675 676 if (freq) { 677 678 clkcr &= ~SUNXI_MMC_CLKCR_DIV; 679 clkcr |= __SHIFTIN(ddr, SUNXI_MMC_CLKCR_DIV); 680 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 681 682 if (flags & SUNXI_MMC_FLAG_NEW_TIMINGS) { 683 ntsr = MMC_READ(sc, SUNXI_MMC_NTSR); 684 ntsr |= SUNXI_MMC_NTSR_MODE_SELECT; 685 MMC_WRITE(sc, SUNXI_MMC_NTSR, ntsr); 686 } 687 688 if (flags & SUNXI_MMC_FLAG_CALIB_REG) 689 MMC_WRITE(sc, SUNXI_MMC_SAMP_DL, SUNXI_MMC_SAMP_DL_SW_EN); 690 691 if (sunxi_mmc_update_clock(sc) != 0) 692 return 1; 693 694 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 695 if (ddr) 696 gctrl |= SUNXI_MMC_GCTRL_DDR_MODE; 697 else 698 gctrl &= ~SUNXI_MMC_GCTRL_DDR_MODE; 699 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 700 701 if (sunxi_mmc_set_clock(sc, freq, ddr) != 0) 702 return 1; 703 704 clkcr |= SUNXI_MMC_CLKCR_CARDCLKON; 705 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 706 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 707 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 708 if (sunxi_mmc_update_clock(sc) != 0) 709 return 1; 710 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 711 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 712 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 713 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 714 } 715 } 716 717 return 0; 718 } 719 720 static int 721 sunxi_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 722 { 723 struct sunxi_mmc_softc *sc = sch; 724 725 #ifdef SUNXI_MMC_DEBUG 726 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 727 #endif 728 729 switch (width) { 730 case 1: 731 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_1); 732 break; 733 case 4: 734 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_4); 735 break; 736 case 8: 737 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_8); 738 break; 739 default: 740 return 1; 741 } 742 743 sc->sc_mmc_width = width; 744 745 return 0; 746 } 747 748 static int 749 sunxi_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 750 { 751 return -1; 752 } 753 754 static int 755 sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 756 { 757 struct sunxi_mmc_softc *sc = sch; 758 u_int uvol; 759 int error; 760 761 if (sc->sc_reg_vqmmc == NULL) 762 return 0; 763 764 switch (signal_voltage) { 765 case SDMMC_SIGNAL_VOLTAGE_330: 766 uvol = 3300000; 767 break; 768 case SDMMC_SIGNAL_VOLTAGE_180: 769 uvol = 1800000; 770 break; 771 default: 772 return EINVAL; 773 } 774 775 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 776 if (error != 0) 777 return error; 778 779 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 780 } 781 782 static int 783 sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 784 { 785 struct sunxi_mmc_idma_descriptor *dma = sc->sc_idma_desc; 786 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 787 bus_size_t off; 788 int desc, resid, seg; 789 uint32_t val; 790 791 desc = 0; 792 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 793 bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr; 794 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 795 resid = min(len, cmd->c_resid); 796 off = 0; 797 while (resid > 0) { 798 if (desc == sc->sc_idma_ndesc) 799 break; 800 len = min(sc->sc_config->idma_xferlen, resid); 801 dma[desc].dma_buf_size = htole32(len); 802 dma[desc].dma_buf_addr = htole32(paddr + off); 803 dma[desc].dma_config = htole32(SUNXI_MMC_IDMA_CONFIG_CH | 804 SUNXI_MMC_IDMA_CONFIG_OWN); 805 cmd->c_resid -= len; 806 resid -= len; 807 off += len; 808 if (desc == 0) { 809 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_FD); 810 } 811 if (cmd->c_resid == 0) { 812 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_LD); 813 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_ER); 814 dma[desc].dma_next = 0; 815 } else { 816 dma[desc].dma_config |= 817 htole32(SUNXI_MMC_IDMA_CONFIG_DIC); 818 dma[desc].dma_next = htole32( 819 desc_paddr + ((desc+1) * 820 sizeof(struct sunxi_mmc_idma_descriptor))); 821 } 822 ++desc; 823 } 824 } 825 if (desc == sc->sc_idma_ndesc) { 826 aprint_error_dev(sc->sc_dev, 827 "not enough descriptors for %d byte transfer!\n", 828 cmd->c_datalen); 829 return EIO; 830 } 831 832 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 833 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 834 835 sc->sc_idma_idst = 0; 836 837 val = MMC_READ(sc, SUNXI_MMC_GCTRL); 838 val |= SUNXI_MMC_GCTRL_DMAEN; 839 val |= SUNXI_MMC_GCTRL_INTEN; 840 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 841 val |= SUNXI_MMC_GCTRL_DMARESET; 842 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 843 MMC_WRITE(sc, SUNXI_MMC_DMAC, SUNXI_MMC_DMAC_SOFTRESET); 844 MMC_WRITE(sc, SUNXI_MMC_DMAC, 845 SUNXI_MMC_DMAC_IDMA_ON|SUNXI_MMC_DMAC_FIX_BURST); 846 val = MMC_READ(sc, SUNXI_MMC_IDIE); 847 val &= ~(SUNXI_MMC_IDST_RECEIVE_INT|SUNXI_MMC_IDST_TRANSMIT_INT); 848 if (cmd->c_flags & SCF_CMD_READ) 849 val |= SUNXI_MMC_IDST_RECEIVE_INT; 850 else 851 val |= SUNXI_MMC_IDST_TRANSMIT_INT; 852 MMC_WRITE(sc, SUNXI_MMC_IDIE, val); 853 MMC_WRITE(sc, SUNXI_MMC_DLBA, desc_paddr); 854 MMC_WRITE(sc, SUNXI_MMC_FTRGLEVEL, sc->sc_config->dma_ftrglevel); 855 856 return 0; 857 } 858 859 static void 860 sunxi_mmc_dma_complete(struct sunxi_mmc_softc *sc) 861 { 862 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 863 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 864 } 865 866 static void 867 sunxi_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 868 { 869 struct sunxi_mmc_softc *sc = sch; 870 uint32_t cmdval = SUNXI_MMC_CMD_START; 871 const bool poll = (cmd->c_flags & SCF_POLL) != 0; 872 int retry; 873 874 #ifdef SUNXI_MMC_DEBUG 875 aprint_normal_dev(sc->sc_dev, 876 "opcode %d flags 0x%x data %p datalen %d blklen %d poll %d\n", 877 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 878 cmd->c_blklen, poll); 879 #endif 880 881 mutex_enter(&sc->sc_intr_lock); 882 883 if (cmd->c_opcode == 0) 884 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 885 if (cmd->c_flags & SCF_RSP_PRESENT) 886 cmdval |= SUNXI_MMC_CMD_RSP_EXP; 887 if (cmd->c_flags & SCF_RSP_136) 888 cmdval |= SUNXI_MMC_CMD_LONG_RSP; 889 if (cmd->c_flags & SCF_RSP_CRC) 890 cmdval |= SUNXI_MMC_CMD_CHECK_RSP_CRC; 891 892 if (cmd->c_datalen > 0) { 893 unsigned int nblks; 894 895 cmdval |= SUNXI_MMC_CMD_DATA_EXP | SUNXI_MMC_CMD_WAIT_PRE_OVER; 896 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 897 cmdval |= SUNXI_MMC_CMD_WRITE; 898 } 899 900 nblks = cmd->c_datalen / cmd->c_blklen; 901 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 902 ++nblks; 903 904 if (nblks > 1) { 905 cmdval |= SUNXI_MMC_CMD_SEND_AUTO_STOP; 906 } 907 908 MMC_WRITE(sc, SUNXI_MMC_BLKSZ, cmd->c_blklen); 909 MMC_WRITE(sc, SUNXI_MMC_BYTECNT, nblks * cmd->c_blklen); 910 } 911 912 sc->sc_intr_rint = 0; 913 914 MMC_WRITE(sc, SUNXI_MMC_A12A, 915 (cmdval & SUNXI_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff); 916 917 MMC_WRITE(sc, SUNXI_MMC_ARG, cmd->c_arg); 918 919 #ifdef SUNXI_MMC_DEBUG 920 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 921 #endif 922 923 if (cmd->c_datalen == 0) { 924 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 925 } else { 926 cmd->c_resid = cmd->c_datalen; 927 cmd->c_error = sunxi_mmc_dma_prepare(sc, cmd); 928 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 929 if (cmd->c_error == 0) { 930 const uint32_t idst_mask = 931 SUNXI_MMC_IDST_ERROR | SUNXI_MMC_IDST_COMPLETE; 932 retry = 10; 933 while ((sc->sc_idma_idst & idst_mask) == 0) { 934 if (retry-- == 0) { 935 cmd->c_error = ETIMEDOUT; 936 break; 937 } 938 cv_timedwait(&sc->sc_idst_cv, 939 &sc->sc_intr_lock, hz); 940 } 941 } 942 sunxi_mmc_dma_complete(sc); 943 if (sc->sc_idma_idst & SUNXI_MMC_IDST_ERROR) { 944 cmd->c_error = EIO; 945 } else if (!(sc->sc_idma_idst & SUNXI_MMC_IDST_COMPLETE)) { 946 cmd->c_error = ETIMEDOUT; 947 } 948 if (cmd->c_error) { 949 #ifdef SUNXI_MMC_DEBUG 950 aprint_error_dev(sc->sc_dev, 951 "xfer failed, error %d\n", cmd->c_error); 952 #endif 953 goto done; 954 } 955 } 956 957 cmd->c_error = sunxi_mmc_wait_rint(sc, 958 SUNXI_MMC_INT_ERROR|SUNXI_MMC_INT_CMD_DONE, hz * 10, poll); 959 if (cmd->c_error == 0 && (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 960 if (sc->sc_intr_rint & SUNXI_MMC_INT_RESP_TIMEOUT) { 961 cmd->c_error = ETIMEDOUT; 962 } else { 963 cmd->c_error = EIO; 964 } 965 } 966 if (cmd->c_error) { 967 #ifdef SUNXI_MMC_DEBUG 968 aprint_error_dev(sc->sc_dev, 969 "cmd failed, error %d\n", cmd->c_error); 970 #endif 971 goto done; 972 } 973 974 if (cmd->c_datalen > 0) { 975 cmd->c_error = sunxi_mmc_wait_rint(sc, 976 SUNXI_MMC_INT_ERROR| 977 SUNXI_MMC_INT_AUTO_CMD_DONE| 978 SUNXI_MMC_INT_DATA_OVER, 979 hz*10, poll); 980 if (cmd->c_error == 0 && 981 (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 982 cmd->c_error = ETIMEDOUT; 983 } 984 if (cmd->c_error) { 985 #ifdef SUNXI_MMC_DEBUG 986 aprint_error_dev(sc->sc_dev, 987 "data timeout, rint = %08x\n", 988 sc->sc_intr_rint); 989 #endif 990 cmd->c_error = ETIMEDOUT; 991 goto done; 992 } 993 } 994 995 if (cmd->c_flags & SCF_RSP_PRESENT) { 996 if (cmd->c_flags & SCF_RSP_136) { 997 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 998 cmd->c_resp[1] = MMC_READ(sc, SUNXI_MMC_RESP1); 999 cmd->c_resp[2] = MMC_READ(sc, SUNXI_MMC_RESP2); 1000 cmd->c_resp[3] = MMC_READ(sc, SUNXI_MMC_RESP3); 1001 if (cmd->c_flags & SCF_RSP_CRC) { 1002 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1003 (cmd->c_resp[1] << 24); 1004 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1005 (cmd->c_resp[2] << 24); 1006 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1007 (cmd->c_resp[3] << 24); 1008 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1009 } 1010 } else { 1011 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 1012 } 1013 } 1014 1015 done: 1016 cmd->c_flags |= SCF_ITSDONE; 1017 mutex_exit(&sc->sc_intr_lock); 1018 1019 if (cmd->c_error) { 1020 #ifdef SUNXI_MMC_DEBUG 1021 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 1022 #endif 1023 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1024 MMC_READ(sc, SUNXI_MMC_GCTRL) | 1025 SUNXI_MMC_GCTRL_DMARESET | SUNXI_MMC_GCTRL_FIFORESET); 1026 for (retry = 0; retry < 1000; retry++) { 1027 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 1028 break; 1029 delay(10); 1030 } 1031 sunxi_mmc_update_clock(sc); 1032 } 1033 1034 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1035 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_FIFORESET); 1036 } 1037 1038 static void 1039 sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1040 { 1041 } 1042 1043 static void 1044 sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 1045 { 1046 } 1047
Indexes created Tue Sep 30 11:09:46 GMT 2025