sunxi_mmc.c revision 1.16
1 /* $NetBSD: sunxi_mmc.c,v 1.16 2017/10/28 13:13:45 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_sunximmc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.16 2017/10/28 13:13:45 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/gpio.h> 41 42 #include <dev/sdmmc/sdmmcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmc_ioreg.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #include <arm/sunxi/sunxi_mmc.h> 49 50 #ifdef SUNXI_MMC_DEBUG 51 static int sunxi_mmc_debug = SUNXI_MMC_DEBUG; 52 #define DPRINTF(dev, fmt, ...) \ 53 do { \ 54 if (sunxi_mmc_debug & __BIT(device_unit(dev))) \ 55 device_printf((dev), fmt, ##__VA_ARGS__); \ 56 } while (0) 57 #else 58 #define DPRINTF(dev, fmt, ...) ((void)0) 59 #endif 60 61 enum sunxi_mmc_timing { 62 SUNXI_MMC_TIMING_400K, 63 SUNXI_MMC_TIMING_25M, 64 SUNXI_MMC_TIMING_50M, 65 SUNXI_MMC_TIMING_50M_DDR, 66 SUNXI_MMC_TIMING_50M_DDR_8BIT, 67 }; 68 69 struct sunxi_mmc_delay { 70 u_int output_phase; 71 u_int sample_phase; 72 }; 73 74 static const struct sunxi_mmc_delay sun7i_mmc_delays[] = { 75 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 76 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 77 [SUNXI_MMC_TIMING_50M] = { 90, 120 }, 78 [SUNXI_MMC_TIMING_50M_DDR] = { 60, 120 }, 79 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 90, 180 }, 80 }; 81 82 static const struct sunxi_mmc_delay sun9i_mmc_delays[] = { 83 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 84 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 85 [SUNXI_MMC_TIMING_50M] = { 150, 120 }, 86 [SUNXI_MMC_TIMING_50M_DDR] = { 54, 36 }, 87 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 72, 72 }, 88 }; 89 90 #define SUNXI_MMC_NDESC 16 91 92 struct sunxi_mmc_softc; 93 94 static int sunxi_mmc_match(device_t, cfdata_t, void *); 95 static void sunxi_mmc_attach(device_t, device_t, void *); 96 static void sunxi_mmc_attach_i(device_t); 97 98 static int sunxi_mmc_intr(void *); 99 static int sunxi_mmc_dmabounce_setup(struct sunxi_mmc_softc *); 100 static int sunxi_mmc_idma_setup(struct sunxi_mmc_softc *); 101 102 static int sunxi_mmc_host_reset(sdmmc_chipset_handle_t); 103 static uint32_t sunxi_mmc_host_ocr(sdmmc_chipset_handle_t); 104 static int sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t); 105 static int sunxi_mmc_card_detect(sdmmc_chipset_handle_t); 106 static int sunxi_mmc_write_protect(sdmmc_chipset_handle_t); 107 static int sunxi_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 108 static int sunxi_mmc_bus_clock(sdmmc_chipset_handle_t, int, bool); 109 static int sunxi_mmc_bus_width(sdmmc_chipset_handle_t, int); 110 static int sunxi_mmc_bus_rod(sdmmc_chipset_handle_t, int); 111 static int sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 112 static void sunxi_mmc_exec_command(sdmmc_chipset_handle_t, 113 struct sdmmc_command *); 114 static void sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 115 static void sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t); 116 117 static struct sdmmc_chip_functions sunxi_mmc_chip_functions = { 118 .host_reset = sunxi_mmc_host_reset, 119 .host_ocr = sunxi_mmc_host_ocr, 120 .host_maxblklen = sunxi_mmc_host_maxblklen, 121 .card_detect = sunxi_mmc_card_detect, 122 .write_protect = sunxi_mmc_write_protect, 123 .bus_power = sunxi_mmc_bus_power, 124 .bus_clock_ddr = sunxi_mmc_bus_clock, 125 .bus_width = sunxi_mmc_bus_width, 126 .bus_rod = sunxi_mmc_bus_rod, 127 .signal_voltage = sunxi_mmc_signal_voltage, 128 .exec_command = sunxi_mmc_exec_command, 129 .card_enable_intr = sunxi_mmc_card_enable_intr, 130 .card_intr_ack = sunxi_mmc_card_intr_ack, 131 }; 132 133 struct sunxi_mmc_config { 134 u_int idma_xferlen; 135 u_int flags; 136 #define SUNXI_MMC_FLAG_CALIB_REG 0x01 137 #define SUNXI_MMC_FLAG_NEW_TIMINGS 0x02 138 #define SUNXI_MMC_FLAG_MASK_DATA0 0x04 139 const struct sunxi_mmc_delay *delays; 140 uint32_t dma_ftrglevel; 141 }; 142 143 struct sunxi_mmc_softc { 144 device_t sc_dev; 145 bus_space_tag_t sc_bst; 146 bus_space_handle_t sc_bsh; 147 bus_dma_tag_t sc_dmat; 148 int sc_phandle; 149 150 void *sc_ih; 151 kmutex_t sc_intr_lock; 152 kcondvar_t sc_intr_cv; 153 kcondvar_t sc_idst_cv; 154 155 int sc_mmc_width; 156 int sc_mmc_present; 157 158 device_t sc_sdmmc_dev; 159 160 struct sunxi_mmc_config *sc_config; 161 162 bus_dma_segment_t sc_idma_segs[1]; 163 int sc_idma_nsegs; 164 bus_size_t sc_idma_size; 165 bus_dmamap_t sc_idma_map; 166 int sc_idma_ndesc; 167 void *sc_idma_desc; 168 169 bus_dmamap_t sc_dmabounce_map; 170 void *sc_dmabounce_buf; 171 size_t sc_dmabounce_buflen; 172 173 uint32_t sc_intr_rint; 174 uint32_t sc_idma_idst; 175 176 struct clk *sc_clk_ahb; 177 struct clk *sc_clk_mmc; 178 struct clk *sc_clk_output; 179 struct clk *sc_clk_sample; 180 181 struct fdtbus_reset *sc_rst_ahb; 182 183 struct fdtbus_gpio_pin *sc_gpio_cd; 184 int sc_gpio_cd_inverted; 185 struct fdtbus_gpio_pin *sc_gpio_wp; 186 int sc_gpio_wp_inverted; 187 188 struct fdtbus_regulator *sc_reg_vqmmc; 189 190 struct fdtbus_mmc_pwrseq *sc_pwrseq; 191 }; 192 193 CFATTACH_DECL_NEW(sunxi_mmc, sizeof(struct sunxi_mmc_softc), 194 sunxi_mmc_match, sunxi_mmc_attach, NULL, NULL); 195 196 #define MMC_WRITE(sc, reg, val) \ 197 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 198 #define MMC_READ(sc, reg) \ 199 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 200 201 static const struct sunxi_mmc_config sun4i_a10_mmc_config = { 202 .idma_xferlen = 0x2000, 203 .dma_ftrglevel = 0x20070008, 204 .delays = NULL, 205 .flags = 0, 206 }; 207 208 static const struct sunxi_mmc_config sun5i_a13_mmc_config = { 209 .idma_xferlen = 0x10000, 210 .dma_ftrglevel = 0x20070008, 211 .delays = NULL, 212 .flags = 0, 213 }; 214 215 static const struct sunxi_mmc_config sun7i_a20_mmc_config = { 216 .idma_xferlen = 0x2000, 217 .dma_ftrglevel = 0x20070008, 218 .delays = sun7i_mmc_delays, 219 .flags = 0, 220 }; 221 222 static const struct sunxi_mmc_config sun8i_a83t_emmc_config = { 223 .idma_xferlen = 0x10000, 224 .dma_ftrglevel = 0x20070008, 225 .delays = NULL, 226 .flags = SUNXI_MMC_FLAG_NEW_TIMINGS, 227 }; 228 229 static const struct sunxi_mmc_config sun9i_a80_mmc_config = { 230 .idma_xferlen = 0x10000, 231 .dma_ftrglevel = 0x200f0010, 232 .delays = sun9i_mmc_delays, 233 .flags = 0, 234 }; 235 236 static const struct sunxi_mmc_config sun50i_a64_mmc_config = { 237 .idma_xferlen = 0x10000, 238 .dma_ftrglevel = 0x20070008, 239 .delays = NULL, 240 .flags = SUNXI_MMC_FLAG_CALIB_REG | 241 SUNXI_MMC_FLAG_NEW_TIMINGS | 242 SUNXI_MMC_FLAG_MASK_DATA0, 243 }; 244 245 static const struct of_compat_data compat_data[] = { 246 { "allwinner,sun4i-a10-mmc", (uintptr_t)&sun4i_a10_mmc_config }, 247 { "allwinner,sun5i-a13-mmc", (uintptr_t)&sun5i_a13_mmc_config }, 248 { "allwinner,sun7i-a20-mmc", (uintptr_t)&sun7i_a20_mmc_config }, 249 { "allwinner,sun8i-a83t-emmc", (uintptr_t)&sun8i_a83t_emmc_config }, 250 { "allwinner,sun9i-a80-mmc", (uintptr_t)&sun9i_a80_mmc_config }, 251 { "allwinner,sun50i-a64-mmc", (uintptr_t)&sun50i_a64_mmc_config }, 252 { NULL } 253 }; 254 255 static int 256 sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux) 257 { 258 struct fdt_attach_args * const faa = aux; 259 260 return of_match_compat_data(faa->faa_phandle, compat_data); 261 } 262 263 static void 264 sunxi_mmc_attach(device_t parent, device_t self, void *aux) 265 { 266 struct sunxi_mmc_softc * const sc = device_private(self); 267 struct fdt_attach_args * const faa = aux; 268 const int phandle = faa->faa_phandle; 269 char intrstr[128]; 270 bus_addr_t addr; 271 bus_size_t size; 272 273 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 274 aprint_error(": couldn't get registers\n"); 275 return; 276 } 277 278 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 279 sc->sc_clk_mmc = fdtbus_clock_get(phandle, "mmc"); 280 sc->sc_clk_output = fdtbus_clock_get(phandle, "output"); 281 sc->sc_clk_sample = fdtbus_clock_get(phandle, "sample"); 282 283 #if notyet 284 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL || 285 sc->sc_clk_output == NULL || sc->sc_clk_sample == NULL) { 286 #else 287 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL) { 288 #endif 289 aprint_error(": couldn't get clocks\n"); 290 return; 291 } 292 293 sc->sc_rst_ahb = fdtbus_reset_get(phandle, "ahb"); 294 295 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(phandle, "vqmmc-supply"); 296 297 sc->sc_pwrseq = fdtbus_mmc_pwrseq_get(phandle); 298 299 if (clk_enable(sc->sc_clk_ahb) != 0 || 300 clk_enable(sc->sc_clk_mmc) != 0) { 301 aprint_error(": couldn't enable clocks\n"); 302 return; 303 } 304 305 if (sc->sc_rst_ahb != NULL) { 306 if (fdtbus_reset_deassert(sc->sc_rst_ahb) != 0) { 307 aprint_error(": couldn't de-assert resets\n"); 308 return; 309 } 310 } 311 312 sc->sc_dev = self; 313 sc->sc_phandle = phandle; 314 sc->sc_config = (void *)of_search_compatible(phandle, compat_data)->data; 315 sc->sc_bst = faa->faa_bst; 316 sc->sc_dmat = faa->faa_dmat; 317 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 318 cv_init(&sc->sc_intr_cv, "awinmmcirq"); 319 cv_init(&sc->sc_idst_cv, "awinmmcdma"); 320 321 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 322 aprint_error(": couldn't map registers\n"); 323 return; 324 } 325 326 aprint_naive("\n"); 327 aprint_normal(": SD/MMC controller\n"); 328 329 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 330 GPIO_PIN_INPUT); 331 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 332 GPIO_PIN_INPUT); 333 334 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 0 : 1; 335 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 0 : 1; 336 337 if (sunxi_mmc_dmabounce_setup(sc) != 0 || 338 sunxi_mmc_idma_setup(sc) != 0) { 339 aprint_error_dev(self, "failed to setup DMA\n"); 340 return; 341 } 342 343 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 344 aprint_error_dev(self, "failed to decode interrupt\n"); 345 return; 346 } 347 348 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, FDT_INTR_MPSAFE, 349 sunxi_mmc_intr, sc); 350 if (sc->sc_ih == NULL) { 351 aprint_error_dev(self, "failed to establish interrupt on %s\n", 352 intrstr); 353 return; 354 } 355 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 356 357 config_interrupts(self, sunxi_mmc_attach_i); 358 } 359 360 static int 361 sunxi_mmc_dmabounce_setup(struct sunxi_mmc_softc *sc) 362 { 363 bus_dma_segment_t ds[1]; 364 int error, rseg; 365 366 sc->sc_dmabounce_buflen = sunxi_mmc_host_maxblklen(sc); 367 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_dmabounce_buflen, 0, 368 sc->sc_dmabounce_buflen, ds, 1, &rseg, BUS_DMA_WAITOK); 369 if (error) 370 return error; 371 error = bus_dmamem_map(sc->sc_dmat, ds, 1, sc->sc_dmabounce_buflen, 372 &sc->sc_dmabounce_buf, BUS_DMA_WAITOK); 373 if (error) 374 goto free; 375 error = bus_dmamap_create(sc->sc_dmat, sc->sc_dmabounce_buflen, 1, 376 sc->sc_dmabounce_buflen, 0, BUS_DMA_WAITOK, &sc->sc_dmabounce_map); 377 if (error) 378 goto unmap; 379 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmabounce_map, 380 sc->sc_dmabounce_buf, sc->sc_dmabounce_buflen, NULL, 381 BUS_DMA_WAITOK); 382 if (error) 383 goto destroy; 384 return 0; 385 386 destroy: 387 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmabounce_map); 388 unmap: 389 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dmabounce_buf, 390 sc->sc_dmabounce_buflen); 391 free: 392 bus_dmamem_free(sc->sc_dmat, ds, rseg); 393 return error; 394 } 395 396 static int 397 sunxi_mmc_idma_setup(struct sunxi_mmc_softc *sc) 398 { 399 int error; 400 401 sc->sc_idma_ndesc = SUNXI_MMC_NDESC; 402 sc->sc_idma_size = sizeof(struct sunxi_mmc_idma_descriptor) * 403 sc->sc_idma_ndesc; 404 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 0, 405 sc->sc_idma_size, sc->sc_idma_segs, 1, 406 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 407 if (error) 408 return error; 409 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 410 sc->sc_idma_nsegs, sc->sc_idma_size, 411 &sc->sc_idma_desc, BUS_DMA_WAITOK); 412 if (error) 413 goto free; 414 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 415 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 416 if (error) 417 goto unmap; 418 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 419 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 420 if (error) 421 goto destroy; 422 return 0; 423 424 destroy: 425 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 426 unmap: 427 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 428 free: 429 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 430 return error; 431 } 432 433 static int 434 sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr) 435 { 436 const struct sunxi_mmc_delay *delays; 437 int error, timing; 438 439 if (freq <= 400) { 440 timing = SUNXI_MMC_TIMING_400K; 441 } else if (freq <= 25000) { 442 timing = SUNXI_MMC_TIMING_25M; 443 } else if (freq <= 52000) { 444 if (ddr) { 445 timing = sc->sc_mmc_width == 8 ? 446 SUNXI_MMC_TIMING_50M_DDR_8BIT : 447 SUNXI_MMC_TIMING_50M_DDR; 448 } else { 449 timing = SUNXI_MMC_TIMING_50M; 450 } 451 } else 452 return EINVAL; 453 454 error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << ddr); 455 if (error != 0) 456 return error; 457 458 if (sc->sc_config->delays == NULL) 459 return 0; 460 461 delays = &sc->sc_config->delays[timing]; 462 463 if (sc->sc_clk_sample) { 464 error = clk_set_rate(sc->sc_clk_sample, delays->sample_phase); 465 if (error != 0) 466 return error; 467 } 468 if (sc->sc_clk_output) { 469 error = clk_set_rate(sc->sc_clk_output, delays->output_phase); 470 if (error != 0) 471 return error; 472 } 473 474 return 0; 475 } 476 477 static void 478 sunxi_mmc_attach_i(device_t self) 479 { 480 struct sunxi_mmc_softc *sc = device_private(self); 481 struct sdmmcbus_attach_args saa; 482 uint32_t width; 483 484 if (sc->sc_pwrseq) 485 fdtbus_mmc_pwrseq_pre_power_on(sc->sc_pwrseq); 486 487 sunxi_mmc_host_reset(sc); 488 sunxi_mmc_bus_width(sc, 1); 489 sunxi_mmc_set_clock(sc, 400, false); 490 491 if (sc->sc_pwrseq) 492 fdtbus_mmc_pwrseq_post_power_on(sc->sc_pwrseq); 493 494 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 495 width = 4; 496 497 memset(&saa, 0, sizeof(saa)); 498 saa.saa_busname = "sdmmc"; 499 saa.saa_sct = &sunxi_mmc_chip_functions; 500 saa.saa_sch = sc; 501 saa.saa_dmat = sc->sc_dmat; 502 saa.saa_clkmin = 400; 503 saa.saa_clkmax = 52000; 504 saa.saa_caps = SMC_CAPS_DMA | 505 SMC_CAPS_MULTI_SEG_DMA | 506 SMC_CAPS_AUTO_STOP | 507 SMC_CAPS_SD_HIGHSPEED | 508 SMC_CAPS_MMC_HIGHSPEED | 509 SMC_CAPS_MMC_DDR52 | 510 SMC_CAPS_POLLING; 511 if (width == 4) 512 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 513 if (width == 8) 514 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 515 516 if (sc->sc_gpio_cd) 517 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 518 519 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 520 } 521 522 static int 523 sunxi_mmc_intr(void *priv) 524 { 525 struct sunxi_mmc_softc *sc = priv; 526 uint32_t idst, rint; 527 528 mutex_enter(&sc->sc_intr_lock); 529 idst = MMC_READ(sc, SUNXI_MMC_IDST); 530 rint = MMC_READ(sc, SUNXI_MMC_RINT); 531 if (!idst && !rint) { 532 mutex_exit(&sc->sc_intr_lock); 533 return 0; 534 } 535 MMC_WRITE(sc, SUNXI_MMC_IDST, idst); 536 MMC_WRITE(sc, SUNXI_MMC_RINT, rint); 537 538 DPRINTF(sc->sc_dev, "mmc intr idst=%08X rint=%08X\n", 539 idst, rint); 540 541 if (idst != 0) { 542 sc->sc_idma_idst |= idst; 543 cv_broadcast(&sc->sc_idst_cv); 544 } 545 546 if ((rint & ~SUNXI_MMC_INT_SDIO_INT) != 0) { 547 sc->sc_intr_rint |= (rint & ~SUNXI_MMC_INT_SDIO_INT); 548 cv_broadcast(&sc->sc_intr_cv); 549 } 550 551 if ((rint & SUNXI_MMC_INT_SDIO_INT) != 0) { 552 sdmmc_card_intr(sc->sc_sdmmc_dev); 553 } 554 555 mutex_exit(&sc->sc_intr_lock); 556 557 return 1; 558 } 559 560 static int 561 sunxi_mmc_wait_rint(struct sunxi_mmc_softc *sc, uint32_t mask, 562 int timeout, bool poll) 563 { 564 int retry; 565 int error; 566 567 KASSERT(mutex_owned(&sc->sc_intr_lock)); 568 569 if (sc->sc_intr_rint & mask) 570 return 0; 571 572 if (poll) 573 retry = timeout / hz * 1000; 574 else 575 retry = timeout / hz; 576 577 while (retry > 0) { 578 if (poll) { 579 sc->sc_intr_rint |= MMC_READ(sc, SUNXI_MMC_RINT); 580 } else { 581 error = cv_timedwait(&sc->sc_intr_cv, 582 &sc->sc_intr_lock, hz); 583 if (error && error != EWOULDBLOCK) 584 return error; 585 } 586 if (sc->sc_intr_rint & mask) 587 return 0; 588 if (poll) 589 delay(1000); 590 --retry; 591 } 592 593 return ETIMEDOUT; 594 } 595 596 static int 597 sunxi_mmc_host_reset(sdmmc_chipset_handle_t sch) 598 { 599 struct sunxi_mmc_softc *sc = sch; 600 int retry = 1000; 601 602 DPRINTF(sc->sc_dev, "host reset\n"); 603 604 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 605 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_RESET); 606 while (--retry > 0) { 607 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 608 break; 609 delay(100); 610 } 611 612 MMC_WRITE(sc, SUNXI_MMC_TIMEOUT, 0xffffffff); 613 614 MMC_WRITE(sc, SUNXI_MMC_IMASK, 615 SUNXI_MMC_INT_CMD_DONE | SUNXI_MMC_INT_ERROR | 616 SUNXI_MMC_INT_DATA_OVER | SUNXI_MMC_INT_AUTO_CMD_DONE); 617 618 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 619 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_INTEN); 620 621 return 0; 622 } 623 624 static uint32_t 625 sunxi_mmc_host_ocr(sdmmc_chipset_handle_t sch) 626 { 627 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 628 } 629 630 static int 631 sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 632 { 633 return 8192; 634 } 635 636 static int 637 sunxi_mmc_card_detect(sdmmc_chipset_handle_t sch) 638 { 639 struct sunxi_mmc_softc *sc = sch; 640 641 if (sc->sc_gpio_cd == NULL) { 642 return 1; /* no card detect pin, assume present */ 643 } else { 644 int v = 0, i; 645 for (i = 0; i < 5; i++) { 646 v += (fdtbus_gpio_read(sc->sc_gpio_cd) ^ 647 sc->sc_gpio_cd_inverted); 648 delay(1000); 649 } 650 if (v == 5) 651 sc->sc_mmc_present = 0; 652 else if (v == 0) 653 sc->sc_mmc_present = 1; 654 return sc->sc_mmc_present; 655 } 656 } 657 658 static int 659 sunxi_mmc_write_protect(sdmmc_chipset_handle_t sch) 660 { 661 struct sunxi_mmc_softc *sc = sch; 662 663 if (sc->sc_gpio_wp == NULL) { 664 return 0; /* no write protect pin, assume rw */ 665 } else { 666 return fdtbus_gpio_read(sc->sc_gpio_wp) ^ 667 sc->sc_gpio_wp_inverted; 668 } 669 } 670 671 static int 672 sunxi_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 673 { 674 return 0; 675 } 676 677 static int 678 sunxi_mmc_update_clock(struct sunxi_mmc_softc *sc) 679 { 680 uint32_t cmd; 681 int retry; 682 683 DPRINTF(sc->sc_dev, "update clock\n"); 684 685 cmd = SUNXI_MMC_CMD_START | 686 SUNXI_MMC_CMD_UPCLK_ONLY | 687 SUNXI_MMC_CMD_WAIT_PRE_OVER; 688 MMC_WRITE(sc, SUNXI_MMC_CMD, cmd); 689 retry = 0xfffff; 690 while (--retry > 0) { 691 if (!(MMC_READ(sc, SUNXI_MMC_CMD) & SUNXI_MMC_CMD_START)) 692 break; 693 delay(10); 694 } 695 696 if (retry == 0) { 697 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 698 DPRINTF(sc->sc_dev, "GCTRL: 0x%08x\n", 699 MMC_READ(sc, SUNXI_MMC_GCTRL)); 700 DPRINTF(sc->sc_dev, "CLKCR: 0x%08x\n", 701 MMC_READ(sc, SUNXI_MMC_CLKCR)); 702 DPRINTF(sc->sc_dev, "TIMEOUT: 0x%08x\n", 703 MMC_READ(sc, SUNXI_MMC_TIMEOUT)); 704 DPRINTF(sc->sc_dev, "WIDTH: 0x%08x\n", 705 MMC_READ(sc, SUNXI_MMC_WIDTH)); 706 DPRINTF(sc->sc_dev, "CMD: 0x%08x\n", 707 MMC_READ(sc, SUNXI_MMC_CMD)); 708 DPRINTF(sc->sc_dev, "MINT: 0x%08x\n", 709 MMC_READ(sc, SUNXI_MMC_MINT)); 710 DPRINTF(sc->sc_dev, "RINT: 0x%08x\n", 711 MMC_READ(sc, SUNXI_MMC_RINT)); 712 DPRINTF(sc->sc_dev, "STATUS: 0x%08x\n", 713 MMC_READ(sc, SUNXI_MMC_STATUS)); 714 return ETIMEDOUT; 715 } 716 717 return 0; 718 } 719 720 static int 721 sunxi_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 722 { 723 struct sunxi_mmc_softc *sc = sch; 724 uint32_t clkcr, gctrl, ntsr; 725 const u_int flags = sc->sc_config->flags; 726 727 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 728 if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) { 729 clkcr &= ~SUNXI_MMC_CLKCR_CARDCLKON; 730 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 731 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 732 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 733 if (sunxi_mmc_update_clock(sc) != 0) 734 return 1; 735 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 736 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 737 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 738 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 739 } 740 } 741 742 if (freq) { 743 744 clkcr &= ~SUNXI_MMC_CLKCR_DIV; 745 clkcr |= __SHIFTIN(ddr, SUNXI_MMC_CLKCR_DIV); 746 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 747 748 if (flags & SUNXI_MMC_FLAG_NEW_TIMINGS) { 749 ntsr = MMC_READ(sc, SUNXI_MMC_NTSR); 750 ntsr |= SUNXI_MMC_NTSR_MODE_SELECT; 751 MMC_WRITE(sc, SUNXI_MMC_NTSR, ntsr); 752 } 753 754 if (flags & SUNXI_MMC_FLAG_CALIB_REG) 755 MMC_WRITE(sc, SUNXI_MMC_SAMP_DL, SUNXI_MMC_SAMP_DL_SW_EN); 756 757 if (sunxi_mmc_update_clock(sc) != 0) 758 return 1; 759 760 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 761 if (ddr) 762 gctrl |= SUNXI_MMC_GCTRL_DDR_MODE; 763 else 764 gctrl &= ~SUNXI_MMC_GCTRL_DDR_MODE; 765 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 766 767 if (sunxi_mmc_set_clock(sc, freq, ddr) != 0) 768 return 1; 769 770 clkcr |= SUNXI_MMC_CLKCR_CARDCLKON; 771 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 772 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 773 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 774 if (sunxi_mmc_update_clock(sc) != 0) 775 return 1; 776 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 777 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 778 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 779 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 780 } 781 } 782 783 return 0; 784 } 785 786 static int 787 sunxi_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 788 { 789 struct sunxi_mmc_softc *sc = sch; 790 791 DPRINTF(sc->sc_dev, "width = %d\n", width); 792 793 switch (width) { 794 case 1: 795 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_1); 796 break; 797 case 4: 798 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_4); 799 break; 800 case 8: 801 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_8); 802 break; 803 default: 804 return 1; 805 } 806 807 sc->sc_mmc_width = width; 808 809 return 0; 810 } 811 812 static int 813 sunxi_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 814 { 815 return -1; 816 } 817 818 static int 819 sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 820 { 821 struct sunxi_mmc_softc *sc = sch; 822 u_int uvol; 823 int error; 824 825 if (sc->sc_reg_vqmmc == NULL) 826 return 0; 827 828 switch (signal_voltage) { 829 case SDMMC_SIGNAL_VOLTAGE_330: 830 uvol = 3300000; 831 break; 832 case SDMMC_SIGNAL_VOLTAGE_180: 833 uvol = 1800000; 834 break; 835 default: 836 return EINVAL; 837 } 838 839 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 840 if (error != 0) 841 return error; 842 843 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 844 } 845 846 static int 847 sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 848 { 849 struct sunxi_mmc_idma_descriptor *dma = sc->sc_idma_desc; 850 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 851 bus_dmamap_t map; 852 bus_size_t off; 853 int desc, resid, seg; 854 uint32_t val; 855 856 /* 857 * If the command includes a dma map use it, otherwise we need to 858 * bounce. This can happen for SDIO IO_RW_EXTENDED (CMD53) commands. 859 */ 860 if (cmd->c_dmamap) { 861 map = cmd->c_dmamap; 862 } else { 863 if (cmd->c_datalen > sc->sc_dmabounce_buflen) 864 return E2BIG; 865 map = sc->sc_dmabounce_map; 866 867 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 868 memset(sc->sc_dmabounce_buf, 0, cmd->c_datalen); 869 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 870 0, cmd->c_datalen, BUS_DMASYNC_PREREAD); 871 } else { 872 memcpy(sc->sc_dmabounce_buf, cmd->c_data, 873 cmd->c_datalen); 874 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 875 0, cmd->c_datalen, BUS_DMASYNC_PREWRITE); 876 } 877 } 878 879 desc = 0; 880 for (seg = 0; seg < map->dm_nsegs; seg++) { 881 bus_addr_t paddr = map->dm_segs[seg].ds_addr; 882 bus_size_t len = map->dm_segs[seg].ds_len; 883 resid = min(len, cmd->c_resid); 884 off = 0; 885 while (resid > 0) { 886 if (desc == sc->sc_idma_ndesc) 887 break; 888 len = min(sc->sc_config->idma_xferlen, resid); 889 dma[desc].dma_buf_size = htole32(len); 890 dma[desc].dma_buf_addr = htole32(paddr + off); 891 dma[desc].dma_config = htole32(SUNXI_MMC_IDMA_CONFIG_CH | 892 SUNXI_MMC_IDMA_CONFIG_OWN); 893 cmd->c_resid -= len; 894 resid -= len; 895 off += len; 896 if (desc == 0) { 897 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_FD); 898 } 899 if (cmd->c_resid == 0) { 900 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_LD); 901 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_ER); 902 dma[desc].dma_next = 0; 903 } else { 904 dma[desc].dma_config |= 905 htole32(SUNXI_MMC_IDMA_CONFIG_DIC); 906 dma[desc].dma_next = htole32( 907 desc_paddr + ((desc+1) * 908 sizeof(struct sunxi_mmc_idma_descriptor))); 909 } 910 ++desc; 911 } 912 } 913 if (desc == sc->sc_idma_ndesc) { 914 aprint_error_dev(sc->sc_dev, 915 "not enough descriptors for %d byte transfer!\n", 916 cmd->c_datalen); 917 return EIO; 918 } 919 920 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 921 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 922 923 sc->sc_idma_idst = 0; 924 925 val = MMC_READ(sc, SUNXI_MMC_GCTRL); 926 val |= SUNXI_MMC_GCTRL_DMAEN; 927 val |= SUNXI_MMC_GCTRL_INTEN; 928 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 929 val |= SUNXI_MMC_GCTRL_DMARESET; 930 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 931 MMC_WRITE(sc, SUNXI_MMC_DMAC, SUNXI_MMC_DMAC_SOFTRESET); 932 MMC_WRITE(sc, SUNXI_MMC_DMAC, 933 SUNXI_MMC_DMAC_IDMA_ON|SUNXI_MMC_DMAC_FIX_BURST); 934 val = MMC_READ(sc, SUNXI_MMC_IDIE); 935 val &= ~(SUNXI_MMC_IDST_RECEIVE_INT|SUNXI_MMC_IDST_TRANSMIT_INT); 936 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 937 val |= SUNXI_MMC_IDST_RECEIVE_INT; 938 else 939 val |= SUNXI_MMC_IDST_TRANSMIT_INT; 940 MMC_WRITE(sc, SUNXI_MMC_IDIE, val); 941 MMC_WRITE(sc, SUNXI_MMC_DLBA, desc_paddr); 942 MMC_WRITE(sc, SUNXI_MMC_FTRGLEVEL, sc->sc_config->dma_ftrglevel); 943 944 return 0; 945 } 946 947 static void 948 sunxi_mmc_dma_complete(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 949 { 950 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 951 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 952 953 if (cmd->c_dmamap == NULL) { 954 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 955 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 956 0, cmd->c_datalen, BUS_DMASYNC_POSTREAD); 957 memcpy(cmd->c_data, sc->sc_dmabounce_buf, 958 cmd->c_datalen); 959 } else { 960 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 961 0, cmd->c_datalen, BUS_DMASYNC_POSTWRITE); 962 } 963 } 964 } 965 966 static void 967 sunxi_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 968 { 969 struct sunxi_mmc_softc *sc = sch; 970 uint32_t cmdval = SUNXI_MMC_CMD_START; 971 const bool poll = (cmd->c_flags & SCF_POLL) != 0; 972 int retry; 973 974 DPRINTF(sc->sc_dev, 975 "opcode %d flags 0x%x data %p datalen %d blklen %d poll %d\n", 976 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 977 cmd->c_blklen, poll); 978 979 mutex_enter(&sc->sc_intr_lock); 980 981 if (cmd->c_opcode == 0) 982 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 983 if (cmd->c_flags & SCF_RSP_PRESENT) 984 cmdval |= SUNXI_MMC_CMD_RSP_EXP; 985 if (cmd->c_flags & SCF_RSP_136) 986 cmdval |= SUNXI_MMC_CMD_LONG_RSP; 987 if (cmd->c_flags & SCF_RSP_CRC) 988 cmdval |= SUNXI_MMC_CMD_CHECK_RSP_CRC; 989 990 if (cmd->c_datalen > 0) { 991 unsigned int nblks; 992 993 cmdval |= SUNXI_MMC_CMD_DATA_EXP | SUNXI_MMC_CMD_WAIT_PRE_OVER; 994 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 995 cmdval |= SUNXI_MMC_CMD_WRITE; 996 } 997 998 nblks = cmd->c_datalen / cmd->c_blklen; 999 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 1000 ++nblks; 1001 1002 if (nblks > 1) { 1003 cmdval |= SUNXI_MMC_CMD_SEND_AUTO_STOP; 1004 } 1005 1006 MMC_WRITE(sc, SUNXI_MMC_BLKSZ, cmd->c_blklen); 1007 MMC_WRITE(sc, SUNXI_MMC_BYTECNT, nblks * cmd->c_blklen); 1008 } 1009 1010 sc->sc_intr_rint = 0; 1011 1012 MMC_WRITE(sc, SUNXI_MMC_A12A, 1013 (cmdval & SUNXI_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff); 1014 1015 MMC_WRITE(sc, SUNXI_MMC_ARG, cmd->c_arg); 1016 1017 DPRINTF(sc->sc_dev, "cmdval = %08x\n", cmdval); 1018 1019 if (cmd->c_datalen == 0) { 1020 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 1021 } else { 1022 cmd->c_resid = cmd->c_datalen; 1023 cmd->c_error = sunxi_mmc_dma_prepare(sc, cmd); 1024 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 1025 if (cmd->c_error == 0) { 1026 const uint32_t idst_mask = 1027 SUNXI_MMC_IDST_ERROR | SUNXI_MMC_IDST_COMPLETE; 1028 retry = 10; 1029 while ((sc->sc_idma_idst & idst_mask) == 0) { 1030 if (retry-- == 0) { 1031 cmd->c_error = ETIMEDOUT; 1032 break; 1033 } 1034 cv_timedwait(&sc->sc_idst_cv, 1035 &sc->sc_intr_lock, hz); 1036 } 1037 } 1038 sunxi_mmc_dma_complete(sc, cmd); 1039 if (sc->sc_idma_idst & SUNXI_MMC_IDST_ERROR) { 1040 cmd->c_error = EIO; 1041 } else if (!(sc->sc_idma_idst & SUNXI_MMC_IDST_COMPLETE)) { 1042 cmd->c_error = ETIMEDOUT; 1043 } 1044 if (cmd->c_error) { 1045 DPRINTF(sc->sc_dev, 1046 "xfer failed, error %d\n", cmd->c_error); 1047 goto done; 1048 } 1049 } 1050 1051 cmd->c_error = sunxi_mmc_wait_rint(sc, 1052 SUNXI_MMC_INT_ERROR|SUNXI_MMC_INT_CMD_DONE, hz * 10, poll); 1053 if (cmd->c_error == 0 && (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 1054 if (sc->sc_intr_rint & SUNXI_MMC_INT_RESP_TIMEOUT) { 1055 cmd->c_error = ETIMEDOUT; 1056 } else { 1057 cmd->c_error = EIO; 1058 } 1059 } 1060 if (cmd->c_error) { 1061 DPRINTF(sc->sc_dev, 1062 "cmd failed, error %d\n", cmd->c_error); 1063 goto done; 1064 } 1065 1066 if (cmd->c_datalen > 0) { 1067 cmd->c_error = sunxi_mmc_wait_rint(sc, 1068 SUNXI_MMC_INT_ERROR| 1069 SUNXI_MMC_INT_AUTO_CMD_DONE| 1070 SUNXI_MMC_INT_DATA_OVER, 1071 hz*10, poll); 1072 if (cmd->c_error == 0 && 1073 (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 1074 cmd->c_error = ETIMEDOUT; 1075 } 1076 if (cmd->c_error) { 1077 DPRINTF(sc->sc_dev, 1078 "data timeout, rint = %08x\n", 1079 sc->sc_intr_rint); 1080 cmd->c_error = ETIMEDOUT; 1081 goto done; 1082 } 1083 } 1084 1085 if (cmd->c_flags & SCF_RSP_PRESENT) { 1086 if (cmd->c_flags & SCF_RSP_136) { 1087 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 1088 cmd->c_resp[1] = MMC_READ(sc, SUNXI_MMC_RESP1); 1089 cmd->c_resp[2] = MMC_READ(sc, SUNXI_MMC_RESP2); 1090 cmd->c_resp[3] = MMC_READ(sc, SUNXI_MMC_RESP3); 1091 if (cmd->c_flags & SCF_RSP_CRC) { 1092 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1093 (cmd->c_resp[1] << 24); 1094 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1095 (cmd->c_resp[2] << 24); 1096 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1097 (cmd->c_resp[3] << 24); 1098 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1099 } 1100 } else { 1101 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 1102 } 1103 } 1104 1105 done: 1106 cmd->c_flags |= SCF_ITSDONE; 1107 mutex_exit(&sc->sc_intr_lock); 1108 1109 if (cmd->c_error) { 1110 DPRINTF(sc->sc_dev, "i/o error %d\n", cmd->c_error); 1111 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1112 MMC_READ(sc, SUNXI_MMC_GCTRL) | 1113 SUNXI_MMC_GCTRL_DMARESET | SUNXI_MMC_GCTRL_FIFORESET); 1114 for (retry = 0; retry < 1000; retry++) { 1115 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 1116 break; 1117 delay(10); 1118 } 1119 sunxi_mmc_update_clock(sc); 1120 } 1121 1122 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1123 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_FIFORESET); 1124 } 1125 1126 static void 1127 sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1128 { 1129 struct sunxi_mmc_softc *sc = sch; 1130 uint32_t imask; 1131 1132 imask = MMC_READ(sc, SUNXI_MMC_IMASK); 1133 if (enable) 1134 imask |= SUNXI_MMC_INT_SDIO_INT; 1135 else 1136 imask &= ~SUNXI_MMC_INT_SDIO_INT; 1137 MMC_WRITE(sc, SUNXI_MMC_IMASK, imask); 1138 } 1139 1140 static void 1141 sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 1142 { 1143 struct sunxi_mmc_softc *sc = sch; 1144 1145 MMC_WRITE(sc, SUNXI_MMC_RINT, SUNXI_MMC_INT_SDIO_INT); 1146 } 1147
Indexes created Tue Sep 30 17:09:57 GMT 2025