sunxi_mmc.c revision 1.19
1 /* $NetBSD: sunxi_mmc.c,v 1.19 2018/01/08 14:40:18 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_sunximmc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.19 2018/01/08 14:40:18 jakllsch Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/gpio.h> 41 42 #include <dev/sdmmc/sdmmcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmc_ioreg.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #include <arm/sunxi/sunxi_mmc.h> 49 50 #ifdef SUNXI_MMC_DEBUG 51 static int sunxi_mmc_debug = SUNXI_MMC_DEBUG; 52 #define DPRINTF(dev, fmt, ...) \ 53 do { \ 54 if (sunxi_mmc_debug & __BIT(device_unit(dev))) \ 55 device_printf((dev), fmt, ##__VA_ARGS__); \ 56 } while (0) 57 #else 58 #define DPRINTF(dev, fmt, ...) ((void)0) 59 #endif 60 61 enum sunxi_mmc_timing { 62 SUNXI_MMC_TIMING_400K, 63 SUNXI_MMC_TIMING_25M, 64 SUNXI_MMC_TIMING_50M, 65 SUNXI_MMC_TIMING_50M_DDR, 66 SUNXI_MMC_TIMING_50M_DDR_8BIT, 67 }; 68 69 struct sunxi_mmc_delay { 70 u_int output_phase; 71 u_int sample_phase; 72 }; 73 74 static const struct sunxi_mmc_delay sun7i_mmc_delays[] = { 75 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 76 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 77 [SUNXI_MMC_TIMING_50M] = { 90, 120 }, 78 [SUNXI_MMC_TIMING_50M_DDR] = { 60, 120 }, 79 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 90, 180 }, 80 }; 81 82 static const struct sunxi_mmc_delay sun9i_mmc_delays[] = { 83 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 84 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 85 [SUNXI_MMC_TIMING_50M] = { 150, 120 }, 86 [SUNXI_MMC_TIMING_50M_DDR] = { 54, 36 }, 87 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 72, 72 }, 88 }; 89 90 #define SUNXI_MMC_NDESC 16 91 92 struct sunxi_mmc_softc; 93 94 static int sunxi_mmc_match(device_t, cfdata_t, void *); 95 static void sunxi_mmc_attach(device_t, device_t, void *); 96 static void sunxi_mmc_attach_i(device_t); 97 98 static int sunxi_mmc_intr(void *); 99 static int sunxi_mmc_dmabounce_setup(struct sunxi_mmc_softc *); 100 static int sunxi_mmc_idma_setup(struct sunxi_mmc_softc *); 101 102 static int sunxi_mmc_host_reset(sdmmc_chipset_handle_t); 103 static uint32_t sunxi_mmc_host_ocr(sdmmc_chipset_handle_t); 104 static int sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t); 105 static int sunxi_mmc_card_detect(sdmmc_chipset_handle_t); 106 static int sunxi_mmc_write_protect(sdmmc_chipset_handle_t); 107 static int sunxi_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 108 static int sunxi_mmc_bus_clock(sdmmc_chipset_handle_t, int, bool); 109 static int sunxi_mmc_bus_width(sdmmc_chipset_handle_t, int); 110 static int sunxi_mmc_bus_rod(sdmmc_chipset_handle_t, int); 111 static int sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 112 static void sunxi_mmc_exec_command(sdmmc_chipset_handle_t, 113 struct sdmmc_command *); 114 static void sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 115 static void sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t); 116 117 static struct sdmmc_chip_functions sunxi_mmc_chip_functions = { 118 .host_reset = sunxi_mmc_host_reset, 119 .host_ocr = sunxi_mmc_host_ocr, 120 .host_maxblklen = sunxi_mmc_host_maxblklen, 121 .card_detect = sunxi_mmc_card_detect, 122 .write_protect = sunxi_mmc_write_protect, 123 .bus_power = sunxi_mmc_bus_power, 124 .bus_clock_ddr = sunxi_mmc_bus_clock, 125 .bus_width = sunxi_mmc_bus_width, 126 .bus_rod = sunxi_mmc_bus_rod, 127 .signal_voltage = sunxi_mmc_signal_voltage, 128 .exec_command = sunxi_mmc_exec_command, 129 .card_enable_intr = sunxi_mmc_card_enable_intr, 130 .card_intr_ack = sunxi_mmc_card_intr_ack, 131 }; 132 133 struct sunxi_mmc_config { 134 u_int idma_xferlen; 135 u_int flags; 136 #define SUNXI_MMC_FLAG_CALIB_REG 0x01 137 #define SUNXI_MMC_FLAG_NEW_TIMINGS 0x02 138 #define SUNXI_MMC_FLAG_MASK_DATA0 0x04 139 const struct sunxi_mmc_delay *delays; 140 uint32_t dma_ftrglevel; 141 }; 142 143 struct sunxi_mmc_softc { 144 device_t sc_dev; 145 bus_space_tag_t sc_bst; 146 bus_space_handle_t sc_bsh; 147 bus_dma_tag_t sc_dmat; 148 int sc_phandle; 149 150 void *sc_ih; 151 kmutex_t sc_intr_lock; 152 kcondvar_t sc_intr_cv; 153 kcondvar_t sc_idst_cv; 154 155 int sc_mmc_width; 156 int sc_mmc_present; 157 158 device_t sc_sdmmc_dev; 159 160 struct sunxi_mmc_config *sc_config; 161 162 bus_dma_segment_t sc_idma_segs[1]; 163 int sc_idma_nsegs; 164 bus_size_t sc_idma_size; 165 bus_dmamap_t sc_idma_map; 166 int sc_idma_ndesc; 167 void *sc_idma_desc; 168 169 bus_dmamap_t sc_dmabounce_map; 170 void *sc_dmabounce_buf; 171 size_t sc_dmabounce_buflen; 172 173 uint32_t sc_intr_rint; 174 uint32_t sc_idma_idst; 175 176 struct clk *sc_clk_ahb; 177 struct clk *sc_clk_mmc; 178 struct clk *sc_clk_output; 179 struct clk *sc_clk_sample; 180 181 struct fdtbus_reset *sc_rst_ahb; 182 183 struct fdtbus_gpio_pin *sc_gpio_cd; 184 int sc_gpio_cd_inverted; 185 struct fdtbus_gpio_pin *sc_gpio_wp; 186 int sc_gpio_wp_inverted; 187 188 struct fdtbus_regulator *sc_reg_vqmmc; 189 190 struct fdtbus_mmc_pwrseq *sc_pwrseq; 191 192 bool sc_non_removable; 193 bool sc_broken_cd; 194 }; 195 196 CFATTACH_DECL_NEW(sunxi_mmc, sizeof(struct sunxi_mmc_softc), 197 sunxi_mmc_match, sunxi_mmc_attach, NULL, NULL); 198 199 #define MMC_WRITE(sc, reg, val) \ 200 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 201 #define MMC_READ(sc, reg) \ 202 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 203 204 static const struct sunxi_mmc_config sun4i_a10_mmc_config = { 205 .idma_xferlen = 0x2000, 206 .dma_ftrglevel = 0x20070008, 207 .delays = NULL, 208 .flags = 0, 209 }; 210 211 static const struct sunxi_mmc_config sun5i_a13_mmc_config = { 212 .idma_xferlen = 0x10000, 213 .dma_ftrglevel = 0x20070008, 214 .delays = NULL, 215 .flags = 0, 216 }; 217 218 static const struct sunxi_mmc_config sun7i_a20_mmc_config = { 219 .idma_xferlen = 0x2000, 220 .dma_ftrglevel = 0x20070008, 221 .delays = sun7i_mmc_delays, 222 .flags = 0, 223 }; 224 225 static const struct sunxi_mmc_config sun8i_a83t_emmc_config = { 226 .idma_xferlen = 0x10000, 227 .dma_ftrglevel = 0x20070008, 228 .delays = NULL, 229 .flags = SUNXI_MMC_FLAG_NEW_TIMINGS, 230 }; 231 232 static const struct sunxi_mmc_config sun9i_a80_mmc_config = { 233 .idma_xferlen = 0x10000, 234 .dma_ftrglevel = 0x200f0010, 235 .delays = sun9i_mmc_delays, 236 .flags = 0, 237 }; 238 239 static const struct sunxi_mmc_config sun50i_a64_mmc_config = { 240 .idma_xferlen = 0x10000, 241 .dma_ftrglevel = 0x20070008, 242 .delays = NULL, 243 .flags = SUNXI_MMC_FLAG_CALIB_REG | 244 SUNXI_MMC_FLAG_NEW_TIMINGS | 245 SUNXI_MMC_FLAG_MASK_DATA0, 246 }; 247 248 static const struct sunxi_mmc_config sun50i_a64_emmc_config = { 249 .idma_xferlen = 0x2000, 250 .dma_ftrglevel = 0x20070008, 251 .delays = NULL, 252 .flags = SUNXI_MMC_FLAG_CALIB_REG, 253 }; 254 255 static const struct of_compat_data compat_data[] = { 256 { "allwinner,sun4i-a10-mmc", (uintptr_t)&sun4i_a10_mmc_config }, 257 { "allwinner,sun5i-a13-mmc", (uintptr_t)&sun5i_a13_mmc_config }, 258 { "allwinner,sun7i-a20-mmc", (uintptr_t)&sun7i_a20_mmc_config }, 259 { "allwinner,sun8i-a83t-emmc", (uintptr_t)&sun8i_a83t_emmc_config }, 260 { "allwinner,sun9i-a80-mmc", (uintptr_t)&sun9i_a80_mmc_config }, 261 { "allwinner,sun50i-a64-mmc", (uintptr_t)&sun50i_a64_mmc_config }, 262 { "allwinner,sun50i-a64-emmc", (uintptr_t)&sun50i_a64_emmc_config }, 263 { NULL } 264 }; 265 266 static int 267 sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux) 268 { 269 struct fdt_attach_args * const faa = aux; 270 271 return of_match_compat_data(faa->faa_phandle, compat_data); 272 } 273 274 static void 275 sunxi_mmc_attach(device_t parent, device_t self, void *aux) 276 { 277 struct sunxi_mmc_softc * const sc = device_private(self); 278 struct fdt_attach_args * const faa = aux; 279 const int phandle = faa->faa_phandle; 280 char intrstr[128]; 281 bus_addr_t addr; 282 bus_size_t size; 283 284 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 285 aprint_error(": couldn't get registers\n"); 286 return; 287 } 288 289 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 290 sc->sc_clk_mmc = fdtbus_clock_get(phandle, "mmc"); 291 sc->sc_clk_output = fdtbus_clock_get(phandle, "output"); 292 sc->sc_clk_sample = fdtbus_clock_get(phandle, "sample"); 293 294 #if notyet 295 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL || 296 sc->sc_clk_output == NULL || sc->sc_clk_sample == NULL) { 297 #else 298 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL) { 299 #endif 300 aprint_error(": couldn't get clocks\n"); 301 return; 302 } 303 304 sc->sc_rst_ahb = fdtbus_reset_get(phandle, "ahb"); 305 306 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(phandle, "vqmmc-supply"); 307 308 sc->sc_pwrseq = fdtbus_mmc_pwrseq_get(phandle); 309 310 if (clk_enable(sc->sc_clk_ahb) != 0 || 311 clk_enable(sc->sc_clk_mmc) != 0) { 312 aprint_error(": couldn't enable clocks\n"); 313 return; 314 } 315 316 if (sc->sc_rst_ahb != NULL) { 317 if (fdtbus_reset_deassert(sc->sc_rst_ahb) != 0) { 318 aprint_error(": couldn't de-assert resets\n"); 319 return; 320 } 321 } 322 323 sc->sc_dev = self; 324 sc->sc_phandle = phandle; 325 sc->sc_config = (void *)of_search_compatible(phandle, compat_data)->data; 326 sc->sc_bst = faa->faa_bst; 327 sc->sc_dmat = faa->faa_dmat; 328 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 329 cv_init(&sc->sc_intr_cv, "awinmmcirq"); 330 cv_init(&sc->sc_idst_cv, "awinmmcdma"); 331 332 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 333 aprint_error(": couldn't map registers\n"); 334 return; 335 } 336 337 aprint_naive("\n"); 338 aprint_normal(": SD/MMC controller\n"); 339 340 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 341 GPIO_PIN_INPUT); 342 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 343 GPIO_PIN_INPUT); 344 345 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 0 : 1; 346 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 0 : 1; 347 348 sc->sc_non_removable = of_hasprop(phandle, "non-removable"); 349 sc->sc_broken_cd = of_hasprop(phandle, "broken-cd"); 350 351 if (sunxi_mmc_dmabounce_setup(sc) != 0 || 352 sunxi_mmc_idma_setup(sc) != 0) { 353 aprint_error_dev(self, "failed to setup DMA\n"); 354 return; 355 } 356 357 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 358 aprint_error_dev(self, "failed to decode interrupt\n"); 359 return; 360 } 361 362 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, FDT_INTR_MPSAFE, 363 sunxi_mmc_intr, sc); 364 if (sc->sc_ih == NULL) { 365 aprint_error_dev(self, "failed to establish interrupt on %s\n", 366 intrstr); 367 return; 368 } 369 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 370 371 config_interrupts(self, sunxi_mmc_attach_i); 372 } 373 374 static int 375 sunxi_mmc_dmabounce_setup(struct sunxi_mmc_softc *sc) 376 { 377 bus_dma_segment_t ds[1]; 378 int error, rseg; 379 380 sc->sc_dmabounce_buflen = sunxi_mmc_host_maxblklen(sc); 381 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_dmabounce_buflen, 0, 382 sc->sc_dmabounce_buflen, ds, 1, &rseg, BUS_DMA_WAITOK); 383 if (error) 384 return error; 385 error = bus_dmamem_map(sc->sc_dmat, ds, 1, sc->sc_dmabounce_buflen, 386 &sc->sc_dmabounce_buf, BUS_DMA_WAITOK); 387 if (error) 388 goto free; 389 error = bus_dmamap_create(sc->sc_dmat, sc->sc_dmabounce_buflen, 1, 390 sc->sc_dmabounce_buflen, 0, BUS_DMA_WAITOK, &sc->sc_dmabounce_map); 391 if (error) 392 goto unmap; 393 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmabounce_map, 394 sc->sc_dmabounce_buf, sc->sc_dmabounce_buflen, NULL, 395 BUS_DMA_WAITOK); 396 if (error) 397 goto destroy; 398 return 0; 399 400 destroy: 401 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmabounce_map); 402 unmap: 403 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dmabounce_buf, 404 sc->sc_dmabounce_buflen); 405 free: 406 bus_dmamem_free(sc->sc_dmat, ds, rseg); 407 return error; 408 } 409 410 static int 411 sunxi_mmc_idma_setup(struct sunxi_mmc_softc *sc) 412 { 413 int error; 414 415 sc->sc_idma_ndesc = SUNXI_MMC_NDESC; 416 sc->sc_idma_size = sizeof(struct sunxi_mmc_idma_descriptor) * 417 sc->sc_idma_ndesc; 418 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 0, 419 sc->sc_idma_size, sc->sc_idma_segs, 1, 420 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 421 if (error) 422 return error; 423 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 424 sc->sc_idma_nsegs, sc->sc_idma_size, 425 &sc->sc_idma_desc, BUS_DMA_WAITOK); 426 if (error) 427 goto free; 428 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 429 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 430 if (error) 431 goto unmap; 432 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 433 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 434 if (error) 435 goto destroy; 436 return 0; 437 438 destroy: 439 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 440 unmap: 441 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 442 free: 443 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 444 return error; 445 } 446 447 static int 448 sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr) 449 { 450 const struct sunxi_mmc_delay *delays; 451 int error, timing; 452 453 if (freq <= 400) { 454 timing = SUNXI_MMC_TIMING_400K; 455 } else if (freq <= 25000) { 456 timing = SUNXI_MMC_TIMING_25M; 457 } else if (freq <= 52000) { 458 if (ddr) { 459 timing = sc->sc_mmc_width == 8 ? 460 SUNXI_MMC_TIMING_50M_DDR_8BIT : 461 SUNXI_MMC_TIMING_50M_DDR; 462 } else { 463 timing = SUNXI_MMC_TIMING_50M; 464 } 465 } else 466 return EINVAL; 467 468 error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << ddr); 469 if (error != 0) 470 return error; 471 472 if (sc->sc_config->delays == NULL) 473 return 0; 474 475 delays = &sc->sc_config->delays[timing]; 476 477 if (sc->sc_clk_sample) { 478 error = clk_set_rate(sc->sc_clk_sample, delays->sample_phase); 479 if (error != 0) 480 return error; 481 } 482 if (sc->sc_clk_output) { 483 error = clk_set_rate(sc->sc_clk_output, delays->output_phase); 484 if (error != 0) 485 return error; 486 } 487 488 return 0; 489 } 490 491 static void 492 sunxi_mmc_attach_i(device_t self) 493 { 494 struct sunxi_mmc_softc *sc = device_private(self); 495 struct sdmmcbus_attach_args saa; 496 uint32_t width; 497 498 if (sc->sc_pwrseq) 499 fdtbus_mmc_pwrseq_pre_power_on(sc->sc_pwrseq); 500 501 sunxi_mmc_host_reset(sc); 502 sunxi_mmc_bus_width(sc, 1); 503 sunxi_mmc_set_clock(sc, 400, false); 504 505 if (sc->sc_pwrseq) 506 fdtbus_mmc_pwrseq_post_power_on(sc->sc_pwrseq); 507 508 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 509 width = 4; 510 511 memset(&saa, 0, sizeof(saa)); 512 saa.saa_busname = "sdmmc"; 513 saa.saa_sct = &sunxi_mmc_chip_functions; 514 saa.saa_sch = sc; 515 saa.saa_dmat = sc->sc_dmat; 516 saa.saa_clkmin = 400; 517 saa.saa_clkmax = 52000; 518 saa.saa_caps = SMC_CAPS_DMA | 519 SMC_CAPS_MULTI_SEG_DMA | 520 SMC_CAPS_AUTO_STOP | 521 SMC_CAPS_SD_HIGHSPEED | 522 SMC_CAPS_MMC_HIGHSPEED | 523 SMC_CAPS_MMC_DDR52 | 524 SMC_CAPS_POLLING; 525 if (width == 4) 526 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 527 if (width == 8) 528 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 529 530 if (sc->sc_gpio_cd) 531 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 532 533 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 534 } 535 536 static int 537 sunxi_mmc_intr(void *priv) 538 { 539 struct sunxi_mmc_softc *sc = priv; 540 uint32_t idst, rint; 541 542 mutex_enter(&sc->sc_intr_lock); 543 idst = MMC_READ(sc, SUNXI_MMC_IDST); 544 rint = MMC_READ(sc, SUNXI_MMC_RINT); 545 if (!idst && !rint) { 546 mutex_exit(&sc->sc_intr_lock); 547 return 0; 548 } 549 MMC_WRITE(sc, SUNXI_MMC_IDST, idst); 550 MMC_WRITE(sc, SUNXI_MMC_RINT, rint); 551 552 DPRINTF(sc->sc_dev, "mmc intr idst=%08X rint=%08X\n", 553 idst, rint); 554 555 if (idst != 0) { 556 sc->sc_idma_idst |= idst; 557 cv_broadcast(&sc->sc_idst_cv); 558 } 559 560 if ((rint & ~SUNXI_MMC_INT_SDIO_INT) != 0) { 561 sc->sc_intr_rint |= (rint & ~SUNXI_MMC_INT_SDIO_INT); 562 cv_broadcast(&sc->sc_intr_cv); 563 } 564 565 if ((rint & SUNXI_MMC_INT_SDIO_INT) != 0) { 566 sdmmc_card_intr(sc->sc_sdmmc_dev); 567 } 568 569 mutex_exit(&sc->sc_intr_lock); 570 571 return 1; 572 } 573 574 static int 575 sunxi_mmc_wait_rint(struct sunxi_mmc_softc *sc, uint32_t mask, 576 int timeout, bool poll) 577 { 578 int retry; 579 int error; 580 581 KASSERT(mutex_owned(&sc->sc_intr_lock)); 582 583 if (sc->sc_intr_rint & mask) 584 return 0; 585 586 if (poll) 587 retry = timeout / hz * 1000; 588 else 589 retry = timeout / hz; 590 591 while (retry > 0) { 592 if (poll) { 593 sc->sc_intr_rint |= MMC_READ(sc, SUNXI_MMC_RINT); 594 } else { 595 error = cv_timedwait(&sc->sc_intr_cv, 596 &sc->sc_intr_lock, hz); 597 if (error && error != EWOULDBLOCK) 598 return error; 599 } 600 if (sc->sc_intr_rint & mask) 601 return 0; 602 if (poll) 603 delay(1000); 604 --retry; 605 } 606 607 return ETIMEDOUT; 608 } 609 610 static int 611 sunxi_mmc_host_reset(sdmmc_chipset_handle_t sch) 612 { 613 struct sunxi_mmc_softc *sc = sch; 614 int retry = 1000; 615 616 DPRINTF(sc->sc_dev, "host reset\n"); 617 618 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 619 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_RESET); 620 while (--retry > 0) { 621 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 622 break; 623 delay(100); 624 } 625 626 MMC_WRITE(sc, SUNXI_MMC_TIMEOUT, 0xffffffff); 627 628 MMC_WRITE(sc, SUNXI_MMC_IMASK, 629 SUNXI_MMC_INT_CMD_DONE | SUNXI_MMC_INT_ERROR | 630 SUNXI_MMC_INT_DATA_OVER | SUNXI_MMC_INT_AUTO_CMD_DONE); 631 632 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 633 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_INTEN); 634 635 return 0; 636 } 637 638 static uint32_t 639 sunxi_mmc_host_ocr(sdmmc_chipset_handle_t sch) 640 { 641 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 642 } 643 644 static int 645 sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 646 { 647 return 8192; 648 } 649 650 static int 651 sunxi_mmc_card_detect(sdmmc_chipset_handle_t sch) 652 { 653 struct sunxi_mmc_softc *sc = sch; 654 655 if (sc->sc_non_removable || sc->sc_broken_cd) { 656 /* 657 * Non-removable or broken card detect flag set in 658 * DT, assume always present 659 */ 660 return 1; 661 } else if (sc->sc_gpio_cd != NULL) { 662 /* Use card detect GPIO */ 663 int v = 0, i; 664 for (i = 0; i < 5; i++) { 665 v += (fdtbus_gpio_read(sc->sc_gpio_cd) ^ 666 sc->sc_gpio_cd_inverted); 667 delay(1000); 668 } 669 if (v == 5) 670 sc->sc_mmc_present = 0; 671 else if (v == 0) 672 sc->sc_mmc_present = 1; 673 return sc->sc_mmc_present; 674 } else { 675 /* Use CARD_PRESENT field of SD_STATUS register */ 676 const uint32_t present = MMC_READ(sc, SUNXI_MMC_STATUS) & 677 SUNXI_MMC_STATUS_CARD_PRESENT; 678 return present != 0; 679 } 680 } 681 682 static int 683 sunxi_mmc_write_protect(sdmmc_chipset_handle_t sch) 684 { 685 struct sunxi_mmc_softc *sc = sch; 686 687 if (sc->sc_gpio_wp == NULL) { 688 return 0; /* no write protect pin, assume rw */ 689 } else { 690 return fdtbus_gpio_read(sc->sc_gpio_wp) ^ 691 sc->sc_gpio_wp_inverted; 692 } 693 } 694 695 static int 696 sunxi_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 697 { 698 return 0; 699 } 700 701 static int 702 sunxi_mmc_update_clock(struct sunxi_mmc_softc *sc) 703 { 704 uint32_t cmd; 705 int retry; 706 707 DPRINTF(sc->sc_dev, "update clock\n"); 708 709 cmd = SUNXI_MMC_CMD_START | 710 SUNXI_MMC_CMD_UPCLK_ONLY | 711 SUNXI_MMC_CMD_WAIT_PRE_OVER; 712 MMC_WRITE(sc, SUNXI_MMC_CMD, cmd); 713 retry = 0xfffff; 714 while (--retry > 0) { 715 if (!(MMC_READ(sc, SUNXI_MMC_CMD) & SUNXI_MMC_CMD_START)) 716 break; 717 delay(10); 718 } 719 720 if (retry == 0) { 721 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 722 DPRINTF(sc->sc_dev, "GCTRL: 0x%08x\n", 723 MMC_READ(sc, SUNXI_MMC_GCTRL)); 724 DPRINTF(sc->sc_dev, "CLKCR: 0x%08x\n", 725 MMC_READ(sc, SUNXI_MMC_CLKCR)); 726 DPRINTF(sc->sc_dev, "TIMEOUT: 0x%08x\n", 727 MMC_READ(sc, SUNXI_MMC_TIMEOUT)); 728 DPRINTF(sc->sc_dev, "WIDTH: 0x%08x\n", 729 MMC_READ(sc, SUNXI_MMC_WIDTH)); 730 DPRINTF(sc->sc_dev, "CMD: 0x%08x\n", 731 MMC_READ(sc, SUNXI_MMC_CMD)); 732 DPRINTF(sc->sc_dev, "MINT: 0x%08x\n", 733 MMC_READ(sc, SUNXI_MMC_MINT)); 734 DPRINTF(sc->sc_dev, "RINT: 0x%08x\n", 735 MMC_READ(sc, SUNXI_MMC_RINT)); 736 DPRINTF(sc->sc_dev, "STATUS: 0x%08x\n", 737 MMC_READ(sc, SUNXI_MMC_STATUS)); 738 return ETIMEDOUT; 739 } 740 741 return 0; 742 } 743 744 static int 745 sunxi_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 746 { 747 struct sunxi_mmc_softc *sc = sch; 748 uint32_t clkcr, gctrl, ntsr; 749 const u_int flags = sc->sc_config->flags; 750 751 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 752 if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) { 753 clkcr &= ~SUNXI_MMC_CLKCR_CARDCLKON; 754 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 755 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 756 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 757 if (sunxi_mmc_update_clock(sc) != 0) 758 return 1; 759 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 760 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 761 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 762 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 763 } 764 } 765 766 if (freq) { 767 768 clkcr &= ~SUNXI_MMC_CLKCR_DIV; 769 clkcr |= __SHIFTIN(ddr, SUNXI_MMC_CLKCR_DIV); 770 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 771 772 if (flags & SUNXI_MMC_FLAG_NEW_TIMINGS) { 773 ntsr = MMC_READ(sc, SUNXI_MMC_NTSR); 774 ntsr |= SUNXI_MMC_NTSR_MODE_SELECT; 775 MMC_WRITE(sc, SUNXI_MMC_NTSR, ntsr); 776 } 777 778 if (flags & SUNXI_MMC_FLAG_CALIB_REG) 779 MMC_WRITE(sc, SUNXI_MMC_SAMP_DL, SUNXI_MMC_SAMP_DL_SW_EN); 780 781 if (sunxi_mmc_update_clock(sc) != 0) 782 return 1; 783 784 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 785 if (ddr) 786 gctrl |= SUNXI_MMC_GCTRL_DDR_MODE; 787 else 788 gctrl &= ~SUNXI_MMC_GCTRL_DDR_MODE; 789 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 790 791 if (sunxi_mmc_set_clock(sc, freq, ddr) != 0) 792 return 1; 793 794 clkcr |= SUNXI_MMC_CLKCR_CARDCLKON; 795 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 796 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 797 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 798 if (sunxi_mmc_update_clock(sc) != 0) 799 return 1; 800 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 801 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 802 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 803 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 804 } 805 } 806 807 return 0; 808 } 809 810 static int 811 sunxi_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 812 { 813 struct sunxi_mmc_softc *sc = sch; 814 815 DPRINTF(sc->sc_dev, "width = %d\n", width); 816 817 switch (width) { 818 case 1: 819 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_1); 820 break; 821 case 4: 822 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_4); 823 break; 824 case 8: 825 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_8); 826 break; 827 default: 828 return 1; 829 } 830 831 sc->sc_mmc_width = width; 832 833 return 0; 834 } 835 836 static int 837 sunxi_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 838 { 839 return -1; 840 } 841 842 static int 843 sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 844 { 845 struct sunxi_mmc_softc *sc = sch; 846 u_int uvol; 847 int error; 848 849 if (sc->sc_reg_vqmmc == NULL) 850 return 0; 851 852 switch (signal_voltage) { 853 case SDMMC_SIGNAL_VOLTAGE_330: 854 uvol = 3300000; 855 break; 856 case SDMMC_SIGNAL_VOLTAGE_180: 857 uvol = 1800000; 858 break; 859 default: 860 return EINVAL; 861 } 862 863 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 864 if (error != 0) 865 return error; 866 867 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 868 } 869 870 static int 871 sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 872 { 873 struct sunxi_mmc_idma_descriptor *dma = sc->sc_idma_desc; 874 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 875 bus_dmamap_t map; 876 bus_size_t off; 877 int desc, resid, seg; 878 uint32_t val; 879 880 /* 881 * If the command includes a dma map use it, otherwise we need to 882 * bounce. This can happen for SDIO IO_RW_EXTENDED (CMD53) commands. 883 */ 884 if (cmd->c_dmamap) { 885 map = cmd->c_dmamap; 886 } else { 887 if (cmd->c_datalen > sc->sc_dmabounce_buflen) 888 return E2BIG; 889 map = sc->sc_dmabounce_map; 890 891 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 892 memset(sc->sc_dmabounce_buf, 0, cmd->c_datalen); 893 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 894 0, cmd->c_datalen, BUS_DMASYNC_PREREAD); 895 } else { 896 memcpy(sc->sc_dmabounce_buf, cmd->c_data, 897 cmd->c_datalen); 898 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 899 0, cmd->c_datalen, BUS_DMASYNC_PREWRITE); 900 } 901 } 902 903 desc = 0; 904 for (seg = 0; seg < map->dm_nsegs; seg++) { 905 bus_addr_t paddr = map->dm_segs[seg].ds_addr; 906 bus_size_t len = map->dm_segs[seg].ds_len; 907 resid = min(len, cmd->c_resid); 908 off = 0; 909 while (resid > 0) { 910 if (desc == sc->sc_idma_ndesc) 911 break; 912 len = min(sc->sc_config->idma_xferlen, resid); 913 dma[desc].dma_buf_size = htole32(len); 914 dma[desc].dma_buf_addr = htole32(paddr + off); 915 dma[desc].dma_config = htole32(SUNXI_MMC_IDMA_CONFIG_CH | 916 SUNXI_MMC_IDMA_CONFIG_OWN); 917 cmd->c_resid -= len; 918 resid -= len; 919 off += len; 920 if (desc == 0) { 921 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_FD); 922 } 923 if (cmd->c_resid == 0) { 924 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_LD); 925 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_ER); 926 dma[desc].dma_next = 0; 927 } else { 928 dma[desc].dma_config |= 929 htole32(SUNXI_MMC_IDMA_CONFIG_DIC); 930 dma[desc].dma_next = htole32( 931 desc_paddr + ((desc+1) * 932 sizeof(struct sunxi_mmc_idma_descriptor))); 933 } 934 ++desc; 935 } 936 } 937 if (desc == sc->sc_idma_ndesc) { 938 aprint_error_dev(sc->sc_dev, 939 "not enough descriptors for %d byte transfer!\n", 940 cmd->c_datalen); 941 return EIO; 942 } 943 944 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 945 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 946 947 sc->sc_idma_idst = 0; 948 949 val = MMC_READ(sc, SUNXI_MMC_GCTRL); 950 val |= SUNXI_MMC_GCTRL_DMAEN; 951 val |= SUNXI_MMC_GCTRL_INTEN; 952 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 953 val |= SUNXI_MMC_GCTRL_DMARESET; 954 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 955 MMC_WRITE(sc, SUNXI_MMC_DMAC, SUNXI_MMC_DMAC_SOFTRESET); 956 MMC_WRITE(sc, SUNXI_MMC_DMAC, 957 SUNXI_MMC_DMAC_IDMA_ON|SUNXI_MMC_DMAC_FIX_BURST); 958 val = MMC_READ(sc, SUNXI_MMC_IDIE); 959 val &= ~(SUNXI_MMC_IDST_RECEIVE_INT|SUNXI_MMC_IDST_TRANSMIT_INT); 960 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 961 val |= SUNXI_MMC_IDST_RECEIVE_INT; 962 else 963 val |= SUNXI_MMC_IDST_TRANSMIT_INT; 964 MMC_WRITE(sc, SUNXI_MMC_IDIE, val); 965 MMC_WRITE(sc, SUNXI_MMC_DLBA, desc_paddr); 966 MMC_WRITE(sc, SUNXI_MMC_FTRGLEVEL, sc->sc_config->dma_ftrglevel); 967 968 return 0; 969 } 970 971 static void 972 sunxi_mmc_dma_complete(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 973 { 974 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 975 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 976 977 if (cmd->c_dmamap == NULL) { 978 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 979 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 980 0, cmd->c_datalen, BUS_DMASYNC_POSTREAD); 981 memcpy(cmd->c_data, sc->sc_dmabounce_buf, 982 cmd->c_datalen); 983 } else { 984 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 985 0, cmd->c_datalen, BUS_DMASYNC_POSTWRITE); 986 } 987 } 988 } 989 990 static void 991 sunxi_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 992 { 993 struct sunxi_mmc_softc *sc = sch; 994 uint32_t cmdval = SUNXI_MMC_CMD_START; 995 const bool poll = (cmd->c_flags & SCF_POLL) != 0; 996 int retry; 997 998 DPRINTF(sc->sc_dev, 999 "opcode %d flags 0x%x data %p datalen %d blklen %d poll %d\n", 1000 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 1001 cmd->c_blklen, poll); 1002 1003 mutex_enter(&sc->sc_intr_lock); 1004 1005 if (cmd->c_opcode == 0) 1006 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 1007 if (cmd->c_flags & SCF_RSP_PRESENT) 1008 cmdval |= SUNXI_MMC_CMD_RSP_EXP; 1009 if (cmd->c_flags & SCF_RSP_136) 1010 cmdval |= SUNXI_MMC_CMD_LONG_RSP; 1011 if (cmd->c_flags & SCF_RSP_CRC) 1012 cmdval |= SUNXI_MMC_CMD_CHECK_RSP_CRC; 1013 1014 if (cmd->c_datalen > 0) { 1015 unsigned int nblks; 1016 1017 cmdval |= SUNXI_MMC_CMD_DATA_EXP | SUNXI_MMC_CMD_WAIT_PRE_OVER; 1018 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 1019 cmdval |= SUNXI_MMC_CMD_WRITE; 1020 } 1021 1022 nblks = cmd->c_datalen / cmd->c_blklen; 1023 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 1024 ++nblks; 1025 1026 if (nblks > 1) { 1027 cmdval |= SUNXI_MMC_CMD_SEND_AUTO_STOP; 1028 } 1029 1030 MMC_WRITE(sc, SUNXI_MMC_BLKSZ, cmd->c_blklen); 1031 MMC_WRITE(sc, SUNXI_MMC_BYTECNT, nblks * cmd->c_blklen); 1032 } 1033 1034 sc->sc_intr_rint = 0; 1035 1036 MMC_WRITE(sc, SUNXI_MMC_A12A, 1037 (cmdval & SUNXI_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff); 1038 1039 MMC_WRITE(sc, SUNXI_MMC_ARG, cmd->c_arg); 1040 1041 DPRINTF(sc->sc_dev, "cmdval = %08x\n", cmdval); 1042 1043 if (cmd->c_datalen == 0) { 1044 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 1045 } else { 1046 cmd->c_resid = cmd->c_datalen; 1047 cmd->c_error = sunxi_mmc_dma_prepare(sc, cmd); 1048 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 1049 if (cmd->c_error == 0) { 1050 const uint32_t idst_mask = 1051 SUNXI_MMC_IDST_ERROR | SUNXI_MMC_IDST_COMPLETE; 1052 retry = 10; 1053 while ((sc->sc_idma_idst & idst_mask) == 0) { 1054 if (retry-- == 0) { 1055 cmd->c_error = ETIMEDOUT; 1056 break; 1057 } 1058 cv_timedwait(&sc->sc_idst_cv, 1059 &sc->sc_intr_lock, hz); 1060 } 1061 } 1062 sunxi_mmc_dma_complete(sc, cmd); 1063 if (sc->sc_idma_idst & SUNXI_MMC_IDST_ERROR) { 1064 cmd->c_error = EIO; 1065 } else if (!(sc->sc_idma_idst & SUNXI_MMC_IDST_COMPLETE)) { 1066 cmd->c_error = ETIMEDOUT; 1067 } 1068 if (cmd->c_error) { 1069 DPRINTF(sc->sc_dev, 1070 "xfer failed, error %d\n", cmd->c_error); 1071 goto done; 1072 } 1073 } 1074 1075 cmd->c_error = sunxi_mmc_wait_rint(sc, 1076 SUNXI_MMC_INT_ERROR|SUNXI_MMC_INT_CMD_DONE, hz * 10, poll); 1077 if (cmd->c_error == 0 && (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 1078 if (sc->sc_intr_rint & SUNXI_MMC_INT_RESP_TIMEOUT) { 1079 cmd->c_error = ETIMEDOUT; 1080 } else { 1081 cmd->c_error = EIO; 1082 } 1083 } 1084 if (cmd->c_error) { 1085 DPRINTF(sc->sc_dev, 1086 "cmd failed, error %d\n", cmd->c_error); 1087 goto done; 1088 } 1089 1090 if (cmd->c_datalen > 0) { 1091 cmd->c_error = sunxi_mmc_wait_rint(sc, 1092 SUNXI_MMC_INT_ERROR| 1093 SUNXI_MMC_INT_AUTO_CMD_DONE| 1094 SUNXI_MMC_INT_DATA_OVER, 1095 hz*10, poll); 1096 if (cmd->c_error == 0 && 1097 (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 1098 cmd->c_error = ETIMEDOUT; 1099 } 1100 if (cmd->c_error) { 1101 DPRINTF(sc->sc_dev, 1102 "data timeout, rint = %08x\n", 1103 sc->sc_intr_rint); 1104 cmd->c_error = ETIMEDOUT; 1105 goto done; 1106 } 1107 } 1108 1109 if (cmd->c_flags & SCF_RSP_PRESENT) { 1110 if (cmd->c_flags & SCF_RSP_136) { 1111 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 1112 cmd->c_resp[1] = MMC_READ(sc, SUNXI_MMC_RESP1); 1113 cmd->c_resp[2] = MMC_READ(sc, SUNXI_MMC_RESP2); 1114 cmd->c_resp[3] = MMC_READ(sc, SUNXI_MMC_RESP3); 1115 if (cmd->c_flags & SCF_RSP_CRC) { 1116 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1117 (cmd->c_resp[1] << 24); 1118 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1119 (cmd->c_resp[2] << 24); 1120 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1121 (cmd->c_resp[3] << 24); 1122 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1123 } 1124 } else { 1125 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 1126 } 1127 } 1128 1129 done: 1130 cmd->c_flags |= SCF_ITSDONE; 1131 mutex_exit(&sc->sc_intr_lock); 1132 1133 if (cmd->c_error) { 1134 DPRINTF(sc->sc_dev, "i/o error %d\n", cmd->c_error); 1135 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1136 MMC_READ(sc, SUNXI_MMC_GCTRL) | 1137 SUNXI_MMC_GCTRL_DMARESET | SUNXI_MMC_GCTRL_FIFORESET); 1138 for (retry = 0; retry < 1000; retry++) { 1139 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 1140 break; 1141 delay(10); 1142 } 1143 sunxi_mmc_update_clock(sc); 1144 } 1145 1146 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1147 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_FIFORESET); 1148 } 1149 1150 static void 1151 sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1152 { 1153 struct sunxi_mmc_softc *sc = sch; 1154 uint32_t imask; 1155 1156 imask = MMC_READ(sc, SUNXI_MMC_IMASK); 1157 if (enable) 1158 imask |= SUNXI_MMC_INT_SDIO_INT; 1159 else 1160 imask &= ~SUNXI_MMC_INT_SDIO_INT; 1161 MMC_WRITE(sc, SUNXI_MMC_IMASK, imask); 1162 } 1163 1164 static void 1165 sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 1166 { 1167 struct sunxi_mmc_softc *sc = sch; 1168 1169 MMC_WRITE(sc, SUNXI_MMC_RINT, SUNXI_MMC_INT_SDIO_INT); 1170 } 1171
Indexes created Tue Sep 30 17:09:57 GMT 2025