sunxi_mmc.c revision 1.2
1 /* $NetBSD: sunxi_mmc.c,v 1.2 2017/07/16 17:12:18 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.2 2017/07/16 17:12:18 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/gpio.h> 39 40 #include <dev/sdmmc/sdmmcvar.h> 41 #include <dev/sdmmc/sdmmcchip.h> 42 #include <dev/sdmmc/sdmmc_ioreg.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/sunxi/sunxi_mmc.h> 47 48 #define SUNXI_MMC_NDESC 16 49 #define SUNXI_MMC_DMA_XFERLEN 0x10000 50 #define SUNXI_MMC_DMA_FTRGLEVEL 0x20070008 51 52 struct sunxi_mmc_softc; 53 54 static int sunxi_mmc_match(device_t, cfdata_t, void *); 55 static void sunxi_mmc_attach(device_t, device_t, void *); 56 static void sunxi_mmc_attach_i(device_t); 57 58 static int sunxi_mmc_intr(void *); 59 static int sunxi_mmc_idma_setup(struct sunxi_mmc_softc *); 60 61 static int sunxi_mmc_host_reset(sdmmc_chipset_handle_t); 62 static uint32_t sunxi_mmc_host_ocr(sdmmc_chipset_handle_t); 63 static int sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t); 64 static int sunxi_mmc_card_detect(sdmmc_chipset_handle_t); 65 static int sunxi_mmc_write_protect(sdmmc_chipset_handle_t); 66 static int sunxi_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 67 static int sunxi_mmc_bus_clock(sdmmc_chipset_handle_t, int); 68 static int sunxi_mmc_bus_width(sdmmc_chipset_handle_t, int); 69 static int sunxi_mmc_bus_rod(sdmmc_chipset_handle_t, int); 70 static void sunxi_mmc_exec_command(sdmmc_chipset_handle_t, 71 struct sdmmc_command *); 72 static void sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 73 static void sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t); 74 75 static struct sdmmc_chip_functions sunxi_mmc_chip_functions = { 76 .host_reset = sunxi_mmc_host_reset, 77 .host_ocr = sunxi_mmc_host_ocr, 78 .host_maxblklen = sunxi_mmc_host_maxblklen, 79 .card_detect = sunxi_mmc_card_detect, 80 .write_protect = sunxi_mmc_write_protect, 81 .bus_power = sunxi_mmc_bus_power, 82 .bus_clock = sunxi_mmc_bus_clock, 83 .bus_width = sunxi_mmc_bus_width, 84 .bus_rod = sunxi_mmc_bus_rod, 85 .exec_command = sunxi_mmc_exec_command, 86 .card_enable_intr = sunxi_mmc_card_enable_intr, 87 .card_intr_ack = sunxi_mmc_card_intr_ack, 88 }; 89 90 struct sunxi_mmc_softc { 91 device_t sc_dev; 92 bus_space_tag_t sc_bst; 93 bus_space_handle_t sc_bsh; 94 bus_dma_tag_t sc_dmat; 95 int sc_phandle; 96 97 void *sc_ih; 98 kmutex_t sc_intr_lock; 99 kcondvar_t sc_intr_cv; 100 kcondvar_t sc_idst_cv; 101 102 int sc_mmc_width; 103 int sc_mmc_present; 104 105 device_t sc_sdmmc_dev; 106 107 uint32_t sc_dma_ftrglevel; 108 109 uint32_t sc_idma_xferlen; 110 bus_dma_segment_t sc_idma_segs[1]; 111 int sc_idma_nsegs; 112 bus_size_t sc_idma_size; 113 bus_dmamap_t sc_idma_map; 114 int sc_idma_ndesc; 115 void *sc_idma_desc; 116 117 uint32_t sc_intr_rint; 118 uint32_t sc_intr_mint; 119 uint32_t sc_idma_idst; 120 121 struct clk *sc_clk_ahb; 122 struct clk *sc_clk_mmc; 123 struct clk *sc_clk_output; 124 struct clk *sc_clk_sample; 125 126 struct fdtbus_reset *sc_rst_ahb; 127 128 struct fdtbus_gpio_pin *sc_gpio_cd; 129 int sc_gpio_cd_inverted; 130 struct fdtbus_gpio_pin *sc_gpio_wp; 131 int sc_gpio_wp_inverted; 132 }; 133 134 CFATTACH_DECL_NEW(sunxi_mmc, sizeof(struct sunxi_mmc_softc), 135 sunxi_mmc_match, sunxi_mmc_attach, NULL, NULL); 136 137 #define MMC_WRITE(sc, reg, val) \ 138 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 139 #define MMC_READ(sc, reg) \ 140 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 141 142 static const char * const compatible[] = { 143 "allwinner,sun7i-a20-mmc", 144 NULL 145 }; 146 147 static int 148 sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux) 149 { 150 struct fdt_attach_args * const faa = aux; 151 152 return of_match_compatible(faa->faa_phandle, compatible); 153 } 154 155 static void 156 sunxi_mmc_attach(device_t parent, device_t self, void *aux) 157 { 158 struct sunxi_mmc_softc * const sc = device_private(self); 159 struct fdt_attach_args * const faa = aux; 160 const int phandle = faa->faa_phandle; 161 char intrstr[128]; 162 bus_addr_t addr; 163 bus_size_t size; 164 165 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 166 aprint_error(": couldn't get registers\n"); 167 return; 168 } 169 170 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 171 sc->sc_clk_mmc = fdtbus_clock_get(phandle, "mmc"); 172 sc->sc_clk_output = fdtbus_clock_get(phandle, "output"); 173 sc->sc_clk_sample = fdtbus_clock_get(phandle, "sample"); 174 175 #if notyet 176 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL || 177 sc->sc_clk_output == NULL || sc->sc_clk_sample == NULL) { 178 #else 179 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL) { 180 #endif 181 aprint_error(": couldn't get clocks\n"); 182 return; 183 } 184 185 sc->sc_rst_ahb = fdtbus_reset_get(phandle, "ahb"); 186 if (sc->sc_rst_ahb == NULL) { 187 aprint_error(": couldn't get resets\n"); 188 return; 189 } 190 191 if (clk_enable(sc->sc_clk_ahb) != 0 || 192 clk_enable(sc->sc_clk_mmc) != 0) { 193 aprint_error(": couldn't enable clocks\n"); 194 return; 195 } 196 197 if (fdtbus_reset_deassert(sc->sc_rst_ahb) != 0) { 198 aprint_error(": couldn't de-assert resets\n"); 199 return; 200 } 201 202 sc->sc_dev = self; 203 sc->sc_phandle = phandle; 204 sc->sc_bst = faa->faa_bst; 205 sc->sc_dmat = faa->faa_dmat; 206 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 207 cv_init(&sc->sc_intr_cv, "awinmmcirq"); 208 cv_init(&sc->sc_idst_cv, "awinmmcdma"); 209 210 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 211 aprint_error(": couldn't map registers\n"); 212 return; 213 } 214 215 aprint_naive("\n"); 216 aprint_normal(": SD/MMC controller\n"); 217 218 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 219 GPIO_PIN_INPUT); 220 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 221 GPIO_PIN_INPUT); 222 223 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 0 : 1; 224 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 0 : 1; 225 226 sc->sc_dma_ftrglevel = SUNXI_MMC_DMA_FTRGLEVEL; 227 228 if (sunxi_mmc_idma_setup(sc) != 0) { 229 aprint_error_dev(self, "failed to setup DMA\n"); 230 return; 231 } 232 233 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 234 aprint_error_dev(self, "failed to decode interrupt\n"); 235 return; 236 } 237 238 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, FDT_INTR_MPSAFE, 239 sunxi_mmc_intr, sc); 240 if (sc->sc_ih == NULL) { 241 aprint_error_dev(self, "failed to establish interrupt on %s\n", 242 intrstr); 243 return; 244 } 245 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 246 247 config_interrupts(self, sunxi_mmc_attach_i); 248 } 249 250 static int 251 sunxi_mmc_idma_setup(struct sunxi_mmc_softc *sc) 252 { 253 int error; 254 255 sc->sc_idma_xferlen = SUNXI_MMC_DMA_XFERLEN; 256 257 sc->sc_idma_ndesc = SUNXI_MMC_NDESC; 258 sc->sc_idma_size = sizeof(struct sunxi_mmc_idma_descriptor) * 259 sc->sc_idma_ndesc; 260 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 0, 261 sc->sc_idma_size, sc->sc_idma_segs, 1, 262 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 263 if (error) 264 return error; 265 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 266 sc->sc_idma_nsegs, sc->sc_idma_size, 267 &sc->sc_idma_desc, BUS_DMA_WAITOK); 268 if (error) 269 goto free; 270 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 271 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 272 if (error) 273 goto unmap; 274 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 275 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 276 if (error) 277 goto destroy; 278 return 0; 279 280 destroy: 281 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 282 unmap: 283 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 284 free: 285 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 286 return error; 287 } 288 289 static int 290 sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq) 291 { 292 return clk_set_rate(sc->sc_clk_mmc, freq * 1000); 293 } 294 295 static void 296 sunxi_mmc_attach_i(device_t self) 297 { 298 struct sunxi_mmc_softc *sc = device_private(self); 299 struct sdmmcbus_attach_args saa; 300 uint32_t width; 301 302 sunxi_mmc_host_reset(sc); 303 sunxi_mmc_bus_width(sc, 1); 304 sunxi_mmc_set_clock(sc, 400); 305 306 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 307 width = 4; 308 309 memset(&saa, 0, sizeof(saa)); 310 saa.saa_busname = "sdmmc"; 311 saa.saa_sct = &sunxi_mmc_chip_functions; 312 saa.saa_sch = sc; 313 saa.saa_dmat = sc->sc_dmat; 314 saa.saa_clkmin = 400; 315 saa.saa_clkmax = 52000; 316 saa.saa_caps = SMC_CAPS_DMA | 317 SMC_CAPS_MULTI_SEG_DMA | 318 SMC_CAPS_AUTO_STOP | 319 SMC_CAPS_SD_HIGHSPEED | 320 SMC_CAPS_MMC_HIGHSPEED | 321 SMC_CAPS_POLLING; 322 if (width == 4) 323 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 324 if (width == 8) 325 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 326 327 if (sc->sc_gpio_cd) 328 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 329 330 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 331 } 332 333 static int 334 sunxi_mmc_intr(void *priv) 335 { 336 struct sunxi_mmc_softc *sc = priv; 337 uint32_t idst, rint, mint; 338 339 mutex_enter(&sc->sc_intr_lock); 340 idst = MMC_READ(sc, SUNXI_MMC_IDST); 341 rint = MMC_READ(sc, SUNXI_MMC_RINT); 342 mint = MMC_READ(sc, SUNXI_MMC_MINT); 343 if (!idst && !rint && !mint) { 344 mutex_exit(&sc->sc_intr_lock); 345 return 0; 346 } 347 MMC_WRITE(sc, SUNXI_MMC_IDST, idst); 348 MMC_WRITE(sc, SUNXI_MMC_RINT, rint); 349 MMC_WRITE(sc, SUNXI_MMC_MINT, mint); 350 351 #ifdef SUNXI_MMC_DEBUG 352 device_printf(sc->sc_dev, "mmc intr idst=%08X rint=%08X mint=%08X\n", 353 idst, rint, mint); 354 #endif 355 356 if (idst) { 357 sc->sc_idma_idst |= idst; 358 cv_broadcast(&sc->sc_idst_cv); 359 } 360 361 if (rint) { 362 sc->sc_intr_rint |= rint; 363 cv_broadcast(&sc->sc_intr_cv); 364 } 365 366 mutex_exit(&sc->sc_intr_lock); 367 368 return 1; 369 } 370 371 static int 372 sunxi_mmc_wait_rint(struct sunxi_mmc_softc *sc, uint32_t mask, 373 int timeout, bool poll) 374 { 375 int retry; 376 int error; 377 378 KASSERT(mutex_owned(&sc->sc_intr_lock)); 379 380 if (sc->sc_intr_rint & mask) 381 return 0; 382 383 if (poll) 384 retry = timeout / hz * 1000; 385 else 386 retry = timeout / hz; 387 388 while (retry > 0) { 389 if (poll) { 390 sc->sc_intr_rint |= MMC_READ(sc, SUNXI_MMC_RINT); 391 } else { 392 error = cv_timedwait(&sc->sc_intr_cv, 393 &sc->sc_intr_lock, hz); 394 if (error && error != EWOULDBLOCK) 395 return error; 396 } 397 if (sc->sc_intr_rint & mask) 398 return 0; 399 if (poll) 400 delay(1000); 401 --retry; 402 } 403 404 return ETIMEDOUT; 405 } 406 407 static int 408 sunxi_mmc_host_reset(sdmmc_chipset_handle_t sch) 409 { 410 struct sunxi_mmc_softc *sc = sch; 411 int retry = 1000; 412 413 #ifdef SUNXI_MMC_DEBUG 414 aprint_normal_dev(sc->sc_dev, "host reset\n"); 415 #endif 416 417 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 418 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_RESET); 419 while (--retry > 0) { 420 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 421 break; 422 delay(100); 423 } 424 425 MMC_WRITE(sc, SUNXI_MMC_TIMEOUT, 0xffffffff); 426 427 MMC_WRITE(sc, SUNXI_MMC_IMASK, 428 SUNXI_MMC_INT_CMD_DONE | SUNXI_MMC_INT_ERROR | 429 SUNXI_MMC_INT_DATA_OVER | SUNXI_MMC_INT_AUTO_CMD_DONE); 430 431 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 432 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_INTEN); 433 434 return 0; 435 } 436 437 static uint32_t 438 sunxi_mmc_host_ocr(sdmmc_chipset_handle_t sch) 439 { 440 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 441 } 442 443 static int 444 sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 445 { 446 return 8192; 447 } 448 449 static int 450 sunxi_mmc_card_detect(sdmmc_chipset_handle_t sch) 451 { 452 struct sunxi_mmc_softc *sc = sch; 453 454 if (sc->sc_gpio_cd == NULL) { 455 return 1; /* no card detect pin, assume present */ 456 } else { 457 int v = 0, i; 458 for (i = 0; i < 5; i++) { 459 v += (fdtbus_gpio_read(sc->sc_gpio_cd) ^ 460 sc->sc_gpio_cd_inverted); 461 delay(1000); 462 } 463 if (v == 5) 464 sc->sc_mmc_present = 0; 465 else if (v == 0) 466 sc->sc_mmc_present = 1; 467 return sc->sc_mmc_present; 468 } 469 } 470 471 static int 472 sunxi_mmc_write_protect(sdmmc_chipset_handle_t sch) 473 { 474 struct sunxi_mmc_softc *sc = sch; 475 476 if (sc->sc_gpio_wp == NULL) { 477 return 0; /* no write protect pin, assume rw */ 478 } else { 479 return fdtbus_gpio_read(sc->sc_gpio_wp) ^ 480 sc->sc_gpio_wp_inverted; 481 } 482 } 483 484 static int 485 sunxi_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 486 { 487 return 0; 488 } 489 490 static int 491 sunxi_mmc_update_clock(struct sunxi_mmc_softc *sc) 492 { 493 uint32_t cmd; 494 int retry; 495 496 #ifdef SUNXI_MMC_DEBUG 497 aprint_normal_dev(sc->sc_dev, "update clock\n"); 498 #endif 499 500 cmd = SUNXI_MMC_CMD_START | 501 SUNXI_MMC_CMD_UPCLK_ONLY | 502 SUNXI_MMC_CMD_WAIT_PRE_OVER; 503 MMC_WRITE(sc, SUNXI_MMC_CMD, cmd); 504 retry = 0xfffff; 505 while (--retry > 0) { 506 if (!(MMC_READ(sc, SUNXI_MMC_CMD) & SUNXI_MMC_CMD_START)) 507 break; 508 delay(10); 509 } 510 511 if (retry == 0) { 512 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 513 #ifdef SUNXI_MMC_DEBUG 514 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 515 MMC_READ(sc, SUNXI_MMC_GCTRL)); 516 device_printf(sc->sc_dev, "CLKCR: 0x%08x\n", 517 MMC_READ(sc, SUNXI_MMC_CLKCR)); 518 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 519 MMC_READ(sc, SUNXI_MMC_TIMEOUT)); 520 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 521 MMC_READ(sc, SUNXI_MMC_WIDTH)); 522 device_printf(sc->sc_dev, "CMD: 0x%08x\n", 523 MMC_READ(sc, SUNXI_MMC_CMD)); 524 device_printf(sc->sc_dev, "MINT: 0x%08x\n", 525 MMC_READ(sc, SUNXI_MMC_MINT)); 526 device_printf(sc->sc_dev, "RINT: 0x%08x\n", 527 MMC_READ(sc, SUNXI_MMC_RINT)); 528 device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 529 MMC_READ(sc, SUNXI_MMC_STATUS)); 530 #endif 531 return ETIMEDOUT; 532 } 533 534 return 0; 535 } 536 537 static int 538 sunxi_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 539 { 540 struct sunxi_mmc_softc *sc = sch; 541 uint32_t clkcr; 542 543 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 544 if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) { 545 clkcr &= ~SUNXI_MMC_CLKCR_CARDCLKON; 546 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 547 if (sunxi_mmc_update_clock(sc) != 0) 548 return 1; 549 } 550 551 if (freq) { 552 553 clkcr &= ~SUNXI_MMC_CLKCR_DIV; 554 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 555 if (sunxi_mmc_update_clock(sc) != 0) 556 return 1; 557 558 if (sunxi_mmc_set_clock(sc, freq) != 0) 559 return 1; 560 561 clkcr |= SUNXI_MMC_CLKCR_CARDCLKON; 562 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 563 if (sunxi_mmc_update_clock(sc) != 0) 564 return 1; 565 } 566 567 return 0; 568 } 569 570 static int 571 sunxi_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 572 { 573 struct sunxi_mmc_softc *sc = sch; 574 575 #ifdef SUNXI_MMC_DEBUG 576 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 577 #endif 578 579 switch (width) { 580 case 1: 581 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_1); 582 break; 583 case 4: 584 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_4); 585 break; 586 case 8: 587 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_8); 588 break; 589 default: 590 return 1; 591 } 592 593 sc->sc_mmc_width = width; 594 595 return 0; 596 } 597 598 static int 599 sunxi_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 600 { 601 return -1; 602 } 603 604 static int 605 sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 606 { 607 struct sunxi_mmc_idma_descriptor *dma = sc->sc_idma_desc; 608 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 609 bus_size_t off; 610 int desc, resid, seg; 611 uint32_t val; 612 613 desc = 0; 614 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 615 bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr; 616 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 617 resid = min(len, cmd->c_resid); 618 off = 0; 619 while (resid > 0) { 620 if (desc == sc->sc_idma_ndesc) 621 break; 622 len = min(sc->sc_idma_xferlen, resid); 623 dma[desc].dma_buf_size = htole32(len); 624 dma[desc].dma_buf_addr = htole32(paddr + off); 625 dma[desc].dma_config = htole32(SUNXI_MMC_IDMA_CONFIG_CH | 626 SUNXI_MMC_IDMA_CONFIG_OWN); 627 cmd->c_resid -= len; 628 resid -= len; 629 off += len; 630 if (desc == 0) { 631 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_FD); 632 } 633 if (cmd->c_resid == 0) { 634 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_LD); 635 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_ER); 636 dma[desc].dma_next = 0; 637 } else { 638 dma[desc].dma_config |= 639 htole32(SUNXI_MMC_IDMA_CONFIG_DIC); 640 dma[desc].dma_next = htole32( 641 desc_paddr + ((desc+1) * 642 sizeof(struct sunxi_mmc_idma_descriptor))); 643 } 644 ++desc; 645 } 646 } 647 if (desc == sc->sc_idma_ndesc) { 648 aprint_error_dev(sc->sc_dev, 649 "not enough descriptors for %d byte transfer!\n", 650 cmd->c_datalen); 651 return EIO; 652 } 653 654 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 655 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 656 657 sc->sc_idma_idst = 0; 658 659 val = MMC_READ(sc, SUNXI_MMC_GCTRL); 660 val |= SUNXI_MMC_GCTRL_DMAEN; 661 val |= SUNXI_MMC_GCTRL_INTEN; 662 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 663 val |= SUNXI_MMC_GCTRL_DMARESET; 664 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 665 MMC_WRITE(sc, SUNXI_MMC_DMAC, SUNXI_MMC_DMAC_SOFTRESET); 666 MMC_WRITE(sc, SUNXI_MMC_DMAC, 667 SUNXI_MMC_DMAC_IDMA_ON|SUNXI_MMC_DMAC_FIX_BURST); 668 val = MMC_READ(sc, SUNXI_MMC_IDIE); 669 val &= ~(SUNXI_MMC_IDST_RECEIVE_INT|SUNXI_MMC_IDST_TRANSMIT_INT); 670 if (cmd->c_flags & SCF_CMD_READ) 671 val |= SUNXI_MMC_IDST_RECEIVE_INT; 672 else 673 val |= SUNXI_MMC_IDST_TRANSMIT_INT; 674 MMC_WRITE(sc, SUNXI_MMC_IDIE, val); 675 MMC_WRITE(sc, SUNXI_MMC_DLBA, desc_paddr); 676 MMC_WRITE(sc, SUNXI_MMC_FTRGLEVEL, sc->sc_dma_ftrglevel); 677 678 return 0; 679 } 680 681 static void 682 sunxi_mmc_dma_complete(struct sunxi_mmc_softc *sc) 683 { 684 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 685 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 686 } 687 688 static void 689 sunxi_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 690 { 691 struct sunxi_mmc_softc *sc = sch; 692 uint32_t cmdval = SUNXI_MMC_CMD_START; 693 const bool poll = (cmd->c_flags & SCF_POLL) != 0; 694 int retry; 695 696 #ifdef SUNXI_MMC_DEBUG 697 aprint_normal_dev(sc->sc_dev, 698 "opcode %d flags 0x%x data %p datalen %d blklen %d poll %d\n", 699 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 700 cmd->c_blklen, poll); 701 #endif 702 703 mutex_enter(&sc->sc_intr_lock); 704 705 if (cmd->c_opcode == 0) 706 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 707 if (cmd->c_flags & SCF_RSP_PRESENT) 708 cmdval |= SUNXI_MMC_CMD_RSP_EXP; 709 if (cmd->c_flags & SCF_RSP_136) 710 cmdval |= SUNXI_MMC_CMD_LONG_RSP; 711 if (cmd->c_flags & SCF_RSP_CRC) 712 cmdval |= SUNXI_MMC_CMD_CHECK_RSP_CRC; 713 714 if (cmd->c_datalen > 0) { 715 unsigned int nblks; 716 717 cmdval |= SUNXI_MMC_CMD_DATA_EXP | SUNXI_MMC_CMD_WAIT_PRE_OVER; 718 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 719 cmdval |= SUNXI_MMC_CMD_WRITE; 720 } 721 722 nblks = cmd->c_datalen / cmd->c_blklen; 723 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 724 ++nblks; 725 726 if (nblks > 1) { 727 cmdval |= SUNXI_MMC_CMD_SEND_AUTO_STOP; 728 } 729 730 MMC_WRITE(sc, SUNXI_MMC_BLKSZ, cmd->c_blklen); 731 MMC_WRITE(sc, SUNXI_MMC_BYTECNT, nblks * cmd->c_blklen); 732 } 733 734 sc->sc_intr_rint = 0; 735 736 MMC_WRITE(sc, SUNXI_MMC_A12A, 737 (cmdval & SUNXI_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff); 738 739 MMC_WRITE(sc, SUNXI_MMC_ARG, cmd->c_arg); 740 741 #ifdef SUNXI_MMC_DEBUG 742 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 743 #endif 744 745 if (cmd->c_datalen == 0) { 746 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 747 } else { 748 cmd->c_resid = cmd->c_datalen; 749 cmd->c_error = sunxi_mmc_dma_prepare(sc, cmd); 750 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 751 if (cmd->c_error == 0) { 752 const uint32_t idst_mask = 753 SUNXI_MMC_IDST_ERROR | SUNXI_MMC_IDST_COMPLETE; 754 retry = 10; 755 while ((sc->sc_idma_idst & idst_mask) == 0) { 756 if (retry-- == 0) { 757 cmd->c_error = ETIMEDOUT; 758 break; 759 } 760 cv_timedwait(&sc->sc_idst_cv, 761 &sc->sc_intr_lock, hz); 762 } 763 } 764 sunxi_mmc_dma_complete(sc); 765 if (sc->sc_idma_idst & SUNXI_MMC_IDST_ERROR) { 766 cmd->c_error = EIO; 767 } else if (!(sc->sc_idma_idst & SUNXI_MMC_IDST_COMPLETE)) { 768 cmd->c_error = ETIMEDOUT; 769 } 770 if (cmd->c_error) { 771 #ifdef SUNXI_MMC_DEBUG 772 aprint_error_dev(sc->sc_dev, 773 "xfer failed, error %d\n", cmd->c_error); 774 #endif 775 goto done; 776 } 777 } 778 779 cmd->c_error = sunxi_mmc_wait_rint(sc, 780 SUNXI_MMC_INT_ERROR|SUNXI_MMC_INT_CMD_DONE, hz * 10, poll); 781 if (cmd->c_error == 0 && (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 782 if (sc->sc_intr_rint & SUNXI_MMC_INT_RESP_TIMEOUT) { 783 cmd->c_error = ETIMEDOUT; 784 } else { 785 cmd->c_error = EIO; 786 } 787 } 788 if (cmd->c_error) { 789 #ifdef SUNXI_MMC_DEBUG 790 aprint_error_dev(sc->sc_dev, 791 "cmd failed, error %d\n", cmd->c_error); 792 #endif 793 goto done; 794 } 795 796 if (cmd->c_datalen > 0) { 797 cmd->c_error = sunxi_mmc_wait_rint(sc, 798 SUNXI_MMC_INT_ERROR| 799 SUNXI_MMC_INT_AUTO_CMD_DONE| 800 SUNXI_MMC_INT_DATA_OVER, 801 hz*10, poll); 802 if (cmd->c_error == 0 && 803 (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 804 cmd->c_error = ETIMEDOUT; 805 } 806 if (cmd->c_error) { 807 #ifdef SUNXI_MMC_DEBUG 808 aprint_error_dev(sc->sc_dev, 809 "data timeout, rint = %08x\n", 810 sc->sc_intr_rint); 811 #endif 812 cmd->c_error = ETIMEDOUT; 813 goto done; 814 } 815 } 816 817 if (cmd->c_flags & SCF_RSP_PRESENT) { 818 if (cmd->c_flags & SCF_RSP_136) { 819 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 820 cmd->c_resp[1] = MMC_READ(sc, SUNXI_MMC_RESP1); 821 cmd->c_resp[2] = MMC_READ(sc, SUNXI_MMC_RESP2); 822 cmd->c_resp[3] = MMC_READ(sc, SUNXI_MMC_RESP3); 823 if (cmd->c_flags & SCF_RSP_CRC) { 824 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 825 (cmd->c_resp[1] << 24); 826 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 827 (cmd->c_resp[2] << 24); 828 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 829 (cmd->c_resp[3] << 24); 830 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 831 } 832 } else { 833 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 834 } 835 } 836 837 done: 838 cmd->c_flags |= SCF_ITSDONE; 839 mutex_exit(&sc->sc_intr_lock); 840 841 if (cmd->c_error) { 842 #ifdef SUNXI_MMC_DEBUG 843 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 844 #endif 845 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 846 MMC_READ(sc, SUNXI_MMC_GCTRL) | 847 SUNXI_MMC_GCTRL_DMARESET | SUNXI_MMC_GCTRL_FIFORESET); 848 for (retry = 0; retry < 1000; retry++) { 849 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 850 break; 851 delay(10); 852 } 853 sunxi_mmc_update_clock(sc); 854 } 855 856 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 857 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_FIFORESET); 858 } 859 860 static void 861 sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 862 { 863 } 864 865 static void 866 sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 867 { 868 } 869
Indexes created Tue Sep 30 20:09:53 GMT 2025