sunxi_mmc.c revision 1.3
1 /* $NetBSD: sunxi_mmc.c,v 1.3 2017/07/17 23:31:05 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.3 2017/07/17 23:31:05 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/gpio.h> 39 40 #include <dev/sdmmc/sdmmcvar.h> 41 #include <dev/sdmmc/sdmmcchip.h> 42 #include <dev/sdmmc/sdmmc_ioreg.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/sunxi/sunxi_mmc.h> 47 48 enum sunxi_mmc_timing { 49 SUNXI_MMC_TIMING_400K, 50 SUNXI_MMC_TIMING_25M, 51 SUNXI_MMC_TIMING_50M, 52 SUNXI_MMC_TIMING_50M_DDR, 53 SUNXI_MMC_TIMING_50M_DDR_8BIT, 54 }; 55 56 struct sunxi_mmc_delay { 57 u_int output_phase; 58 u_int sample_phase; 59 }; 60 61 static const struct sunxi_mmc_delay sunxi_mmc_delays[] = { 62 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 63 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 64 [SUNXI_MMC_TIMING_50M] = { 90, 120 }, 65 [SUNXI_MMC_TIMING_50M_DDR] = { 60, 120 }, 66 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 90, 180 }, 67 }; 68 69 #define SUNXI_MMC_NDESC 16 70 #define SUNXI_MMC_DMA_XFERLEN 0x10000 71 #define SUNXI_MMC_DMA_FTRGLEVEL 0x20070008 72 73 struct sunxi_mmc_softc; 74 75 static int sunxi_mmc_match(device_t, cfdata_t, void *); 76 static void sunxi_mmc_attach(device_t, device_t, void *); 77 static void sunxi_mmc_attach_i(device_t); 78 79 static int sunxi_mmc_intr(void *); 80 static int sunxi_mmc_idma_setup(struct sunxi_mmc_softc *); 81 82 static int sunxi_mmc_host_reset(sdmmc_chipset_handle_t); 83 static uint32_t sunxi_mmc_host_ocr(sdmmc_chipset_handle_t); 84 static int sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t); 85 static int sunxi_mmc_card_detect(sdmmc_chipset_handle_t); 86 static int sunxi_mmc_write_protect(sdmmc_chipset_handle_t); 87 static int sunxi_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 88 static int sunxi_mmc_bus_clock(sdmmc_chipset_handle_t, int, bool); 89 static int sunxi_mmc_bus_width(sdmmc_chipset_handle_t, int); 90 static int sunxi_mmc_bus_rod(sdmmc_chipset_handle_t, int); 91 static int sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 92 static void sunxi_mmc_exec_command(sdmmc_chipset_handle_t, 93 struct sdmmc_command *); 94 static void sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 95 static void sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t); 96 97 static struct sdmmc_chip_functions sunxi_mmc_chip_functions = { 98 .host_reset = sunxi_mmc_host_reset, 99 .host_ocr = sunxi_mmc_host_ocr, 100 .host_maxblklen = sunxi_mmc_host_maxblklen, 101 .card_detect = sunxi_mmc_card_detect, 102 .write_protect = sunxi_mmc_write_protect, 103 .bus_power = sunxi_mmc_bus_power, 104 .bus_clock_ddr = sunxi_mmc_bus_clock, 105 .bus_width = sunxi_mmc_bus_width, 106 .bus_rod = sunxi_mmc_bus_rod, 107 .signal_voltage = sunxi_mmc_signal_voltage, 108 .exec_command = sunxi_mmc_exec_command, 109 .card_enable_intr = sunxi_mmc_card_enable_intr, 110 .card_intr_ack = sunxi_mmc_card_intr_ack, 111 }; 112 113 struct sunxi_mmc_softc { 114 device_t sc_dev; 115 bus_space_tag_t sc_bst; 116 bus_space_handle_t sc_bsh; 117 bus_dma_tag_t sc_dmat; 118 int sc_phandle; 119 120 void *sc_ih; 121 kmutex_t sc_intr_lock; 122 kcondvar_t sc_intr_cv; 123 kcondvar_t sc_idst_cv; 124 125 int sc_mmc_width; 126 int sc_mmc_present; 127 128 device_t sc_sdmmc_dev; 129 130 uint32_t sc_dma_ftrglevel; 131 132 uint32_t sc_idma_xferlen; 133 bus_dma_segment_t sc_idma_segs[1]; 134 int sc_idma_nsegs; 135 bus_size_t sc_idma_size; 136 bus_dmamap_t sc_idma_map; 137 int sc_idma_ndesc; 138 void *sc_idma_desc; 139 140 uint32_t sc_intr_rint; 141 uint32_t sc_intr_mint; 142 uint32_t sc_idma_idst; 143 144 struct clk *sc_clk_ahb; 145 struct clk *sc_clk_mmc; 146 struct clk *sc_clk_output; 147 struct clk *sc_clk_sample; 148 149 struct fdtbus_reset *sc_rst_ahb; 150 151 struct fdtbus_gpio_pin *sc_gpio_cd; 152 int sc_gpio_cd_inverted; 153 struct fdtbus_gpio_pin *sc_gpio_wp; 154 int sc_gpio_wp_inverted; 155 156 struct fdtbus_regulator *sc_reg_vqmmc; 157 }; 158 159 CFATTACH_DECL_NEW(sunxi_mmc, sizeof(struct sunxi_mmc_softc), 160 sunxi_mmc_match, sunxi_mmc_attach, NULL, NULL); 161 162 #define MMC_WRITE(sc, reg, val) \ 163 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 164 #define MMC_READ(sc, reg) \ 165 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 166 167 static const char * const compatible[] = { 168 "allwinner,sun7i-a20-mmc", 169 NULL 170 }; 171 172 static int 173 sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux) 174 { 175 struct fdt_attach_args * const faa = aux; 176 177 return of_match_compatible(faa->faa_phandle, compatible); 178 } 179 180 static void 181 sunxi_mmc_attach(device_t parent, device_t self, void *aux) 182 { 183 struct sunxi_mmc_softc * const sc = device_private(self); 184 struct fdt_attach_args * const faa = aux; 185 const int phandle = faa->faa_phandle; 186 char intrstr[128]; 187 bus_addr_t addr; 188 bus_size_t size; 189 190 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 191 aprint_error(": couldn't get registers\n"); 192 return; 193 } 194 195 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 196 sc->sc_clk_mmc = fdtbus_clock_get(phandle, "mmc"); 197 sc->sc_clk_output = fdtbus_clock_get(phandle, "output"); 198 sc->sc_clk_sample = fdtbus_clock_get(phandle, "sample"); 199 200 #if notyet 201 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL || 202 sc->sc_clk_output == NULL || sc->sc_clk_sample == NULL) { 203 #else 204 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL) { 205 #endif 206 aprint_error(": couldn't get clocks\n"); 207 return; 208 } 209 210 sc->sc_rst_ahb = fdtbus_reset_get(phandle, "ahb"); 211 if (sc->sc_rst_ahb == NULL) { 212 aprint_error(": couldn't get resets\n"); 213 return; 214 } 215 216 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(phandle, "vqmmc-supply"); 217 218 if (clk_enable(sc->sc_clk_ahb) != 0 || 219 clk_enable(sc->sc_clk_mmc) != 0) { 220 aprint_error(": couldn't enable clocks\n"); 221 return; 222 } 223 224 if (fdtbus_reset_deassert(sc->sc_rst_ahb) != 0) { 225 aprint_error(": couldn't de-assert resets\n"); 226 return; 227 } 228 229 sc->sc_dev = self; 230 sc->sc_phandle = phandle; 231 sc->sc_bst = faa->faa_bst; 232 sc->sc_dmat = faa->faa_dmat; 233 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 234 cv_init(&sc->sc_intr_cv, "awinmmcirq"); 235 cv_init(&sc->sc_idst_cv, "awinmmcdma"); 236 237 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 238 aprint_error(": couldn't map registers\n"); 239 return; 240 } 241 242 aprint_naive("\n"); 243 aprint_normal(": SD/MMC controller\n"); 244 245 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 246 GPIO_PIN_INPUT); 247 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 248 GPIO_PIN_INPUT); 249 250 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 0 : 1; 251 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 0 : 1; 252 253 sc->sc_dma_ftrglevel = SUNXI_MMC_DMA_FTRGLEVEL; 254 255 if (sunxi_mmc_idma_setup(sc) != 0) { 256 aprint_error_dev(self, "failed to setup DMA\n"); 257 return; 258 } 259 260 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 261 aprint_error_dev(self, "failed to decode interrupt\n"); 262 return; 263 } 264 265 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, FDT_INTR_MPSAFE, 266 sunxi_mmc_intr, sc); 267 if (sc->sc_ih == NULL) { 268 aprint_error_dev(self, "failed to establish interrupt on %s\n", 269 intrstr); 270 return; 271 } 272 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 273 274 config_interrupts(self, sunxi_mmc_attach_i); 275 } 276 277 static int 278 sunxi_mmc_idma_setup(struct sunxi_mmc_softc *sc) 279 { 280 int error; 281 282 sc->sc_idma_xferlen = SUNXI_MMC_DMA_XFERLEN; 283 284 sc->sc_idma_ndesc = SUNXI_MMC_NDESC; 285 sc->sc_idma_size = sizeof(struct sunxi_mmc_idma_descriptor) * 286 sc->sc_idma_ndesc; 287 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 0, 288 sc->sc_idma_size, sc->sc_idma_segs, 1, 289 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 290 if (error) 291 return error; 292 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 293 sc->sc_idma_nsegs, sc->sc_idma_size, 294 &sc->sc_idma_desc, BUS_DMA_WAITOK); 295 if (error) 296 goto free; 297 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 298 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 299 if (error) 300 goto unmap; 301 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 302 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 303 if (error) 304 goto destroy; 305 return 0; 306 307 destroy: 308 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 309 unmap: 310 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 311 free: 312 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 313 return error; 314 } 315 316 static int 317 sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr) 318 { 319 const struct sunxi_mmc_delay *delays; 320 int error, timing; 321 322 if (freq <= 400) { 323 timing = SUNXI_MMC_TIMING_400K; 324 } else if (freq <= 25000) { 325 timing = SUNXI_MMC_TIMING_25M; 326 } else if (freq <= 52000) { 327 if (ddr) { 328 timing = sc->sc_mmc_width == 8 ? 329 SUNXI_MMC_TIMING_50M_DDR_8BIT : 330 SUNXI_MMC_TIMING_50M_DDR; 331 } else { 332 timing = SUNXI_MMC_TIMING_50M; 333 } 334 } else 335 return EINVAL; 336 337 delays = &sunxi_mmc_delays[timing]; 338 339 error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << ddr); 340 if (error != 0) 341 return error; 342 343 if (sc->sc_clk_sample) { 344 error = clk_set_rate(sc->sc_clk_sample, delays->sample_phase); 345 if (error != 0) 346 return error; 347 } 348 if (sc->sc_clk_output) { 349 error = clk_set_rate(sc->sc_clk_output, delays->output_phase); 350 if (error != 0) 351 return error; 352 } 353 354 return 0; 355 } 356 357 static void 358 sunxi_mmc_attach_i(device_t self) 359 { 360 struct sunxi_mmc_softc *sc = device_private(self); 361 struct sdmmcbus_attach_args saa; 362 uint32_t width; 363 364 sunxi_mmc_host_reset(sc); 365 sunxi_mmc_bus_width(sc, 1); 366 sunxi_mmc_set_clock(sc, 400, false); 367 368 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 369 width = 4; 370 371 memset(&saa, 0, sizeof(saa)); 372 saa.saa_busname = "sdmmc"; 373 saa.saa_sct = &sunxi_mmc_chip_functions; 374 saa.saa_sch = sc; 375 saa.saa_dmat = sc->sc_dmat; 376 saa.saa_clkmin = 400; 377 saa.saa_clkmax = 52000; 378 saa.saa_caps = SMC_CAPS_DMA | 379 SMC_CAPS_MULTI_SEG_DMA | 380 SMC_CAPS_AUTO_STOP | 381 SMC_CAPS_SD_HIGHSPEED | 382 SMC_CAPS_MMC_HIGHSPEED | 383 SMC_CAPS_MMC_DDR52 | 384 SMC_CAPS_POLLING; 385 if (width == 4) 386 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 387 if (width == 8) 388 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 389 390 if (sc->sc_gpio_cd) 391 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 392 393 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 394 } 395 396 static int 397 sunxi_mmc_intr(void *priv) 398 { 399 struct sunxi_mmc_softc *sc = priv; 400 uint32_t idst, rint, mint; 401 402 mutex_enter(&sc->sc_intr_lock); 403 idst = MMC_READ(sc, SUNXI_MMC_IDST); 404 rint = MMC_READ(sc, SUNXI_MMC_RINT); 405 mint = MMC_READ(sc, SUNXI_MMC_MINT); 406 if (!idst && !rint && !mint) { 407 mutex_exit(&sc->sc_intr_lock); 408 return 0; 409 } 410 MMC_WRITE(sc, SUNXI_MMC_IDST, idst); 411 MMC_WRITE(sc, SUNXI_MMC_RINT, rint); 412 MMC_WRITE(sc, SUNXI_MMC_MINT, mint); 413 414 #ifdef SUNXI_MMC_DEBUG 415 device_printf(sc->sc_dev, "mmc intr idst=%08X rint=%08X mint=%08X\n", 416 idst, rint, mint); 417 #endif 418 419 if (idst) { 420 sc->sc_idma_idst |= idst; 421 cv_broadcast(&sc->sc_idst_cv); 422 } 423 424 if (rint) { 425 sc->sc_intr_rint |= rint; 426 cv_broadcast(&sc->sc_intr_cv); 427 } 428 429 mutex_exit(&sc->sc_intr_lock); 430 431 return 1; 432 } 433 434 static int 435 sunxi_mmc_wait_rint(struct sunxi_mmc_softc *sc, uint32_t mask, 436 int timeout, bool poll) 437 { 438 int retry; 439 int error; 440 441 KASSERT(mutex_owned(&sc->sc_intr_lock)); 442 443 if (sc->sc_intr_rint & mask) 444 return 0; 445 446 if (poll) 447 retry = timeout / hz * 1000; 448 else 449 retry = timeout / hz; 450 451 while (retry > 0) { 452 if (poll) { 453 sc->sc_intr_rint |= MMC_READ(sc, SUNXI_MMC_RINT); 454 } else { 455 error = cv_timedwait(&sc->sc_intr_cv, 456 &sc->sc_intr_lock, hz); 457 if (error && error != EWOULDBLOCK) 458 return error; 459 } 460 if (sc->sc_intr_rint & mask) 461 return 0; 462 if (poll) 463 delay(1000); 464 --retry; 465 } 466 467 return ETIMEDOUT; 468 } 469 470 static int 471 sunxi_mmc_host_reset(sdmmc_chipset_handle_t sch) 472 { 473 struct sunxi_mmc_softc *sc = sch; 474 int retry = 1000; 475 476 #ifdef SUNXI_MMC_DEBUG 477 aprint_normal_dev(sc->sc_dev, "host reset\n"); 478 #endif 479 480 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 481 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_RESET); 482 while (--retry > 0) { 483 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 484 break; 485 delay(100); 486 } 487 488 MMC_WRITE(sc, SUNXI_MMC_TIMEOUT, 0xffffffff); 489 490 MMC_WRITE(sc, SUNXI_MMC_IMASK, 491 SUNXI_MMC_INT_CMD_DONE | SUNXI_MMC_INT_ERROR | 492 SUNXI_MMC_INT_DATA_OVER | SUNXI_MMC_INT_AUTO_CMD_DONE); 493 494 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 495 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_INTEN); 496 497 return 0; 498 } 499 500 static uint32_t 501 sunxi_mmc_host_ocr(sdmmc_chipset_handle_t sch) 502 { 503 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 504 } 505 506 static int 507 sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 508 { 509 return 8192; 510 } 511 512 static int 513 sunxi_mmc_card_detect(sdmmc_chipset_handle_t sch) 514 { 515 struct sunxi_mmc_softc *sc = sch; 516 517 if (sc->sc_gpio_cd == NULL) { 518 return 1; /* no card detect pin, assume present */ 519 } else { 520 int v = 0, i; 521 for (i = 0; i < 5; i++) { 522 v += (fdtbus_gpio_read(sc->sc_gpio_cd) ^ 523 sc->sc_gpio_cd_inverted); 524 delay(1000); 525 } 526 if (v == 5) 527 sc->sc_mmc_present = 0; 528 else if (v == 0) 529 sc->sc_mmc_present = 1; 530 return sc->sc_mmc_present; 531 } 532 } 533 534 static int 535 sunxi_mmc_write_protect(sdmmc_chipset_handle_t sch) 536 { 537 struct sunxi_mmc_softc *sc = sch; 538 539 if (sc->sc_gpio_wp == NULL) { 540 return 0; /* no write protect pin, assume rw */ 541 } else { 542 return fdtbus_gpio_read(sc->sc_gpio_wp) ^ 543 sc->sc_gpio_wp_inverted; 544 } 545 } 546 547 static int 548 sunxi_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 549 { 550 return 0; 551 } 552 553 static int 554 sunxi_mmc_update_clock(struct sunxi_mmc_softc *sc) 555 { 556 uint32_t cmd; 557 int retry; 558 559 #ifdef SUNXI_MMC_DEBUG 560 aprint_normal_dev(sc->sc_dev, "update clock\n"); 561 #endif 562 563 cmd = SUNXI_MMC_CMD_START | 564 SUNXI_MMC_CMD_UPCLK_ONLY | 565 SUNXI_MMC_CMD_WAIT_PRE_OVER; 566 MMC_WRITE(sc, SUNXI_MMC_CMD, cmd); 567 retry = 0xfffff; 568 while (--retry > 0) { 569 if (!(MMC_READ(sc, SUNXI_MMC_CMD) & SUNXI_MMC_CMD_START)) 570 break; 571 delay(10); 572 } 573 574 if (retry == 0) { 575 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 576 #ifdef SUNXI_MMC_DEBUG 577 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 578 MMC_READ(sc, SUNXI_MMC_GCTRL)); 579 device_printf(sc->sc_dev, "CLKCR: 0x%08x\n", 580 MMC_READ(sc, SUNXI_MMC_CLKCR)); 581 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 582 MMC_READ(sc, SUNXI_MMC_TIMEOUT)); 583 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 584 MMC_READ(sc, SUNXI_MMC_WIDTH)); 585 device_printf(sc->sc_dev, "CMD: 0x%08x\n", 586 MMC_READ(sc, SUNXI_MMC_CMD)); 587 device_printf(sc->sc_dev, "MINT: 0x%08x\n", 588 MMC_READ(sc, SUNXI_MMC_MINT)); 589 device_printf(sc->sc_dev, "RINT: 0x%08x\n", 590 MMC_READ(sc, SUNXI_MMC_RINT)); 591 device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 592 MMC_READ(sc, SUNXI_MMC_STATUS)); 593 #endif 594 return ETIMEDOUT; 595 } 596 597 return 0; 598 } 599 600 static int 601 sunxi_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 602 { 603 struct sunxi_mmc_softc *sc = sch; 604 uint32_t clkcr, gctrl; 605 606 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 607 if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) { 608 clkcr &= ~SUNXI_MMC_CLKCR_CARDCLKON; 609 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 610 if (sunxi_mmc_update_clock(sc) != 0) 611 return 1; 612 } 613 614 if (freq) { 615 616 clkcr &= ~SUNXI_MMC_CLKCR_DIV; 617 clkcr |= __SHIFTIN(ddr, SUNXI_MMC_CLKCR_DIV); 618 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 619 if (sunxi_mmc_update_clock(sc) != 0) 620 return 1; 621 622 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 623 if (ddr) 624 gctrl |= SUNXI_MMC_GCTRL_DDR_MODE; 625 else 626 gctrl &= ~SUNXI_MMC_GCTRL_DDR_MODE; 627 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 628 629 if (sunxi_mmc_set_clock(sc, freq, ddr) != 0) 630 return 1; 631 632 clkcr |= SUNXI_MMC_CLKCR_CARDCLKON; 633 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 634 if (sunxi_mmc_update_clock(sc) != 0) 635 return 1; 636 } 637 638 return 0; 639 } 640 641 static int 642 sunxi_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 643 { 644 struct sunxi_mmc_softc *sc = sch; 645 646 #ifdef SUNXI_MMC_DEBUG 647 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 648 #endif 649 650 switch (width) { 651 case 1: 652 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_1); 653 break; 654 case 4: 655 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_4); 656 break; 657 case 8: 658 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_8); 659 break; 660 default: 661 return 1; 662 } 663 664 sc->sc_mmc_width = width; 665 666 return 0; 667 } 668 669 static int 670 sunxi_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 671 { 672 return -1; 673 } 674 675 static int 676 sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 677 { 678 struct sunxi_mmc_softc *sc = sch; 679 u_int uvol; 680 int error; 681 682 if (sc->sc_reg_vqmmc == NULL) 683 return 0; 684 685 switch (signal_voltage) { 686 case SDMMC_SIGNAL_VOLTAGE_330: 687 uvol = 3300000; 688 break; 689 case SDMMC_SIGNAL_VOLTAGE_180: 690 uvol = 1800000; 691 break; 692 default: 693 return EINVAL; 694 } 695 696 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 697 if (error != 0) 698 return error; 699 700 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 701 } 702 703 static int 704 sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 705 { 706 struct sunxi_mmc_idma_descriptor *dma = sc->sc_idma_desc; 707 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 708 bus_size_t off; 709 int desc, resid, seg; 710 uint32_t val; 711 712 desc = 0; 713 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 714 bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr; 715 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 716 resid = min(len, cmd->c_resid); 717 off = 0; 718 while (resid > 0) { 719 if (desc == sc->sc_idma_ndesc) 720 break; 721 len = min(sc->sc_idma_xferlen, resid); 722 dma[desc].dma_buf_size = htole32(len); 723 dma[desc].dma_buf_addr = htole32(paddr + off); 724 dma[desc].dma_config = htole32(SUNXI_MMC_IDMA_CONFIG_CH | 725 SUNXI_MMC_IDMA_CONFIG_OWN); 726 cmd->c_resid -= len; 727 resid -= len; 728 off += len; 729 if (desc == 0) { 730 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_FD); 731 } 732 if (cmd->c_resid == 0) { 733 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_LD); 734 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_ER); 735 dma[desc].dma_next = 0; 736 } else { 737 dma[desc].dma_config |= 738 htole32(SUNXI_MMC_IDMA_CONFIG_DIC); 739 dma[desc].dma_next = htole32( 740 desc_paddr + ((desc+1) * 741 sizeof(struct sunxi_mmc_idma_descriptor))); 742 } 743 ++desc; 744 } 745 } 746 if (desc == sc->sc_idma_ndesc) { 747 aprint_error_dev(sc->sc_dev, 748 "not enough descriptors for %d byte transfer!\n", 749 cmd->c_datalen); 750 return EIO; 751 } 752 753 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 754 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 755 756 sc->sc_idma_idst = 0; 757 758 val = MMC_READ(sc, SUNXI_MMC_GCTRL); 759 val |= SUNXI_MMC_GCTRL_DMAEN; 760 val |= SUNXI_MMC_GCTRL_INTEN; 761 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 762 val |= SUNXI_MMC_GCTRL_DMARESET; 763 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 764 MMC_WRITE(sc, SUNXI_MMC_DMAC, SUNXI_MMC_DMAC_SOFTRESET); 765 MMC_WRITE(sc, SUNXI_MMC_DMAC, 766 SUNXI_MMC_DMAC_IDMA_ON|SUNXI_MMC_DMAC_FIX_BURST); 767 val = MMC_READ(sc, SUNXI_MMC_IDIE); 768 val &= ~(SUNXI_MMC_IDST_RECEIVE_INT|SUNXI_MMC_IDST_TRANSMIT_INT); 769 if (cmd->c_flags & SCF_CMD_READ) 770 val |= SUNXI_MMC_IDST_RECEIVE_INT; 771 else 772 val |= SUNXI_MMC_IDST_TRANSMIT_INT; 773 MMC_WRITE(sc, SUNXI_MMC_IDIE, val); 774 MMC_WRITE(sc, SUNXI_MMC_DLBA, desc_paddr); 775 MMC_WRITE(sc, SUNXI_MMC_FTRGLEVEL, sc->sc_dma_ftrglevel); 776 777 return 0; 778 } 779 780 static void 781 sunxi_mmc_dma_complete(struct sunxi_mmc_softc *sc) 782 { 783 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 784 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 785 } 786 787 static void 788 sunxi_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 789 { 790 struct sunxi_mmc_softc *sc = sch; 791 uint32_t cmdval = SUNXI_MMC_CMD_START; 792 const bool poll = (cmd->c_flags & SCF_POLL) != 0; 793 int retry; 794 795 #ifdef SUNXI_MMC_DEBUG 796 aprint_normal_dev(sc->sc_dev, 797 "opcode %d flags 0x%x data %p datalen %d blklen %d poll %d\n", 798 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 799 cmd->c_blklen, poll); 800 #endif 801 802 mutex_enter(&sc->sc_intr_lock); 803 804 if (cmd->c_opcode == 0) 805 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 806 if (cmd->c_flags & SCF_RSP_PRESENT) 807 cmdval |= SUNXI_MMC_CMD_RSP_EXP; 808 if (cmd->c_flags & SCF_RSP_136) 809 cmdval |= SUNXI_MMC_CMD_LONG_RSP; 810 if (cmd->c_flags & SCF_RSP_CRC) 811 cmdval |= SUNXI_MMC_CMD_CHECK_RSP_CRC; 812 813 if (cmd->c_datalen > 0) { 814 unsigned int nblks; 815 816 cmdval |= SUNXI_MMC_CMD_DATA_EXP | SUNXI_MMC_CMD_WAIT_PRE_OVER; 817 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 818 cmdval |= SUNXI_MMC_CMD_WRITE; 819 } 820 821 nblks = cmd->c_datalen / cmd->c_blklen; 822 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 823 ++nblks; 824 825 if (nblks > 1) { 826 cmdval |= SUNXI_MMC_CMD_SEND_AUTO_STOP; 827 } 828 829 MMC_WRITE(sc, SUNXI_MMC_BLKSZ, cmd->c_blklen); 830 MMC_WRITE(sc, SUNXI_MMC_BYTECNT, nblks * cmd->c_blklen); 831 } 832 833 sc->sc_intr_rint = 0; 834 835 MMC_WRITE(sc, SUNXI_MMC_A12A, 836 (cmdval & SUNXI_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff); 837 838 MMC_WRITE(sc, SUNXI_MMC_ARG, cmd->c_arg); 839 840 #ifdef SUNXI_MMC_DEBUG 841 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 842 #endif 843 844 if (cmd->c_datalen == 0) { 845 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 846 } else { 847 cmd->c_resid = cmd->c_datalen; 848 cmd->c_error = sunxi_mmc_dma_prepare(sc, cmd); 849 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 850 if (cmd->c_error == 0) { 851 const uint32_t idst_mask = 852 SUNXI_MMC_IDST_ERROR | SUNXI_MMC_IDST_COMPLETE; 853 retry = 10; 854 while ((sc->sc_idma_idst & idst_mask) == 0) { 855 if (retry-- == 0) { 856 cmd->c_error = ETIMEDOUT; 857 break; 858 } 859 cv_timedwait(&sc->sc_idst_cv, 860 &sc->sc_intr_lock, hz); 861 } 862 } 863 sunxi_mmc_dma_complete(sc); 864 if (sc->sc_idma_idst & SUNXI_MMC_IDST_ERROR) { 865 cmd->c_error = EIO; 866 } else if (!(sc->sc_idma_idst & SUNXI_MMC_IDST_COMPLETE)) { 867 cmd->c_error = ETIMEDOUT; 868 } 869 if (cmd->c_error) { 870 #ifdef SUNXI_MMC_DEBUG 871 aprint_error_dev(sc->sc_dev, 872 "xfer failed, error %d\n", cmd->c_error); 873 #endif 874 goto done; 875 } 876 } 877 878 cmd->c_error = sunxi_mmc_wait_rint(sc, 879 SUNXI_MMC_INT_ERROR|SUNXI_MMC_INT_CMD_DONE, hz * 10, poll); 880 if (cmd->c_error == 0 && (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 881 if (sc->sc_intr_rint & SUNXI_MMC_INT_RESP_TIMEOUT) { 882 cmd->c_error = ETIMEDOUT; 883 } else { 884 cmd->c_error = EIO; 885 } 886 } 887 if (cmd->c_error) { 888 #ifdef SUNXI_MMC_DEBUG 889 aprint_error_dev(sc->sc_dev, 890 "cmd failed, error %d\n", cmd->c_error); 891 #endif 892 goto done; 893 } 894 895 if (cmd->c_datalen > 0) { 896 cmd->c_error = sunxi_mmc_wait_rint(sc, 897 SUNXI_MMC_INT_ERROR| 898 SUNXI_MMC_INT_AUTO_CMD_DONE| 899 SUNXI_MMC_INT_DATA_OVER, 900 hz*10, poll); 901 if (cmd->c_error == 0 && 902 (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 903 cmd->c_error = ETIMEDOUT; 904 } 905 if (cmd->c_error) { 906 #ifdef SUNXI_MMC_DEBUG 907 aprint_error_dev(sc->sc_dev, 908 "data timeout, rint = %08x\n", 909 sc->sc_intr_rint); 910 #endif 911 cmd->c_error = ETIMEDOUT; 912 goto done; 913 } 914 } 915 916 if (cmd->c_flags & SCF_RSP_PRESENT) { 917 if (cmd->c_flags & SCF_RSP_136) { 918 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 919 cmd->c_resp[1] = MMC_READ(sc, SUNXI_MMC_RESP1); 920 cmd->c_resp[2] = MMC_READ(sc, SUNXI_MMC_RESP2); 921 cmd->c_resp[3] = MMC_READ(sc, SUNXI_MMC_RESP3); 922 if (cmd->c_flags & SCF_RSP_CRC) { 923 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 924 (cmd->c_resp[1] << 24); 925 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 926 (cmd->c_resp[2] << 24); 927 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 928 (cmd->c_resp[3] << 24); 929 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 930 } 931 } else { 932 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 933 } 934 } 935 936 done: 937 cmd->c_flags |= SCF_ITSDONE; 938 mutex_exit(&sc->sc_intr_lock); 939 940 if (cmd->c_error) { 941 #ifdef SUNXI_MMC_DEBUG 942 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 943 #endif 944 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 945 MMC_READ(sc, SUNXI_MMC_GCTRL) | 946 SUNXI_MMC_GCTRL_DMARESET | SUNXI_MMC_GCTRL_FIFORESET); 947 for (retry = 0; retry < 1000; retry++) { 948 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 949 break; 950 delay(10); 951 } 952 sunxi_mmc_update_clock(sc); 953 } 954 955 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 956 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_FIFORESET); 957 } 958 959 static void 960 sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 961 { 962 } 963 964 static void 965 sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 966 { 967 } 968
Indexes created Tue Sep 30 11:09:46 GMT 2025