sunxi_mmc.c revision 1.3.4.2
1 /* $NetBSD: sunxi_mmc.c,v 1.3.4.2 2017/07/18 19:13:08 snj Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.3.4.2 2017/07/18 19:13:08 snj Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/gpio.h> 39 40 #include <dev/sdmmc/sdmmcvar.h> 41 #include <dev/sdmmc/sdmmcchip.h> 42 #include <dev/sdmmc/sdmmc_ioreg.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/sunxi/sunxi_mmc.h> 47 48 #define SUNXI_MMC_NDESC 16 49 #define SUNXI_MMC_DMA_XFERLEN 0x10000 50 #define SUNXI_MMC_DMA_FTRGLEVEL 0x20070008 51 52 struct sunxi_mmc_softc; 53 54 static int sunxi_mmc_match(device_t, cfdata_t, void *); 55 static void sunxi_mmc_attach(device_t, device_t, void *); 56 static void sunxi_mmc_attach_i(device_t); 57 58 static int sunxi_mmc_intr(void *); 59 static int sunxi_mmc_idma_setup(struct sunxi_mmc_softc *); 60 61 static int sunxi_mmc_host_reset(sdmmc_chipset_handle_t); 62 static uint32_t sunxi_mmc_host_ocr(sdmmc_chipset_handle_t); 63 static int sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t); 64 static int sunxi_mmc_card_detect(sdmmc_chipset_handle_t); 65 static int sunxi_mmc_write_protect(sdmmc_chipset_handle_t); 66 static int sunxi_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 67 static int sunxi_mmc_bus_clock(sdmmc_chipset_handle_t, int); 68 static int sunxi_mmc_bus_width(sdmmc_chipset_handle_t, int); 69 static int sunxi_mmc_bus_rod(sdmmc_chipset_handle_t, int); 70 static void sunxi_mmc_exec_command(sdmmc_chipset_handle_t, 71 struct sdmmc_command *); 72 static void sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 73 static void sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t); 74 75 static struct sdmmc_chip_functions sunxi_mmc_chip_functions = { 76 .host_reset = sunxi_mmc_host_reset, 77 .host_ocr = sunxi_mmc_host_ocr, 78 .host_maxblklen = sunxi_mmc_host_maxblklen, 79 .card_detect = sunxi_mmc_card_detect, 80 .write_protect = sunxi_mmc_write_protect, 81 .bus_power = sunxi_mmc_bus_power, 82 .bus_clock = sunxi_mmc_bus_clock, 83 .bus_width = sunxi_mmc_bus_width, 84 .bus_rod = sunxi_mmc_bus_rod, 85 .exec_command = sunxi_mmc_exec_command, 86 .card_enable_intr = sunxi_mmc_card_enable_intr, 87 .card_intr_ack = sunxi_mmc_card_intr_ack, 88 }; 89 90 struct sunxi_mmc_softc { 91 device_t sc_dev; 92 bus_space_tag_t sc_bst; 93 bus_space_handle_t sc_bsh; 94 bus_dma_tag_t sc_dmat; 95 int sc_phandle; 96 97 void *sc_ih; 98 kmutex_t sc_intr_lock; 99 kcondvar_t sc_intr_cv; 100 kcondvar_t sc_idst_cv; 101 102 int sc_mmc_width; 103 int sc_mmc_present; 104 105 device_t sc_sdmmc_dev; 106 107 uint32_t sc_dma_ftrglevel; 108 109 uint32_t sc_idma_xferlen; 110 bus_dma_segment_t sc_idma_segs[1]; 111 int sc_idma_nsegs; 112 bus_size_t sc_idma_size; 113 bus_dmamap_t sc_idma_map; 114 int sc_idma_ndesc; 115 void *sc_idma_desc; 116 117 uint32_t sc_intr_rint; 118 uint32_t sc_intr_mint; 119 uint32_t sc_idma_idst; 120 121 struct clk *sc_clk_ahb; 122 struct clk *sc_clk_mmc; 123 struct clk *sc_clk_output; 124 struct clk *sc_clk_sample; 125 126 struct fdtbus_reset *sc_rst_ahb; 127 128 struct fdtbus_gpio_pin *sc_gpio_cd; 129 int sc_gpio_cd_inverted; 130 struct fdtbus_gpio_pin *sc_gpio_wp; 131 int sc_gpio_wp_inverted; 132 }; 133 134 CFATTACH_DECL_NEW(sunxi_mmc, sizeof(struct sunxi_mmc_softc), 135 sunxi_mmc_match, sunxi_mmc_attach, NULL, NULL); 136 137 #define MMC_WRITE(sc, reg, val) \ 138 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 139 #define MMC_READ(sc, reg) \ 140 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 141 142 static const char * const compatible[] = { 143 "allwinner,sun7i-a20-mmc", 144 NULL 145 }; 146 147 static int 148 sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux) 149 { 150 struct fdt_attach_args * const faa = aux; 151 152 return of_match_compatible(faa->faa_phandle, compatible); 153 } 154 155 static void 156 sunxi_mmc_attach(device_t parent, device_t self, void *aux) 157 { 158 struct sunxi_mmc_softc * const sc = device_private(self); 159 struct fdt_attach_args * const faa = aux; 160 const int phandle = faa->faa_phandle; 161 char intrstr[128]; 162 bus_addr_t addr; 163 bus_size_t size; 164 165 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 166 aprint_error(": couldn't get registers\n"); 167 return; 168 } 169 170 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 171 sc->sc_clk_mmc = fdtbus_clock_get(phandle, "mmc"); 172 sc->sc_clk_output = fdtbus_clock_get(phandle, "output"); 173 sc->sc_clk_sample = fdtbus_clock_get(phandle, "sample"); 174 175 #if notyet 176 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL || 177 sc->sc_clk_output == NULL || sc->sc_clk_sample == NULL) { 178 #else 179 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL) { 180 #endif 181 aprint_error(": couldn't get clocks\n"); 182 return; 183 } 184 185 sc->sc_rst_ahb = fdtbus_reset_get(phandle, "ahb"); 186 if (sc->sc_rst_ahb == NULL) { 187 aprint_error(": couldn't get resets\n"); 188 return; 189 } 190 191 if (clk_enable(sc->sc_clk_ahb) != 0 || 192 clk_enable(sc->sc_clk_mmc) != 0) { 193 aprint_error(": couldn't enable clocks\n"); 194 return; 195 } 196 197 if (fdtbus_reset_deassert(sc->sc_rst_ahb) != 0) { 198 aprint_error(": couldn't de-assert resets\n"); 199 return; 200 } 201 202 sc->sc_dev = self; 203 sc->sc_phandle = phandle; 204 sc->sc_bst = faa->faa_bst; 205 sc->sc_dmat = faa->faa_dmat; 206 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 207 cv_init(&sc->sc_intr_cv, "awinmmcirq"); 208 cv_init(&sc->sc_idst_cv, "awinmmcdma"); 209 210 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 211 aprint_error(": couldn't map registers\n"); 212 return; 213 } 214 215 aprint_naive("\n"); 216 aprint_normal(": SD/MMC controller\n"); 217 218 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 219 GPIO_PIN_INPUT); 220 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 221 GPIO_PIN_INPUT); 222 223 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 0 : 1; 224 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 0 : 1; 225 226 sc->sc_dma_ftrglevel = SUNXI_MMC_DMA_FTRGLEVEL; 227 228 if (sunxi_mmc_idma_setup(sc) != 0) { 229 aprint_error_dev(self, "failed to setup DMA\n"); 230 return; 231 } 232 233 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 234 aprint_error_dev(self, "failed to decode interrupt\n"); 235 return; 236 } 237 238 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, FDT_INTR_MPSAFE, 239 sunxi_mmc_intr, sc); 240 if (sc->sc_ih == NULL) { 241 aprint_error_dev(self, "failed to establish interrupt on %s\n", 242 intrstr); 243 return; 244 } 245 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 246 247 config_interrupts(self, sunxi_mmc_attach_i); 248 } 249 250 static int 251 sunxi_mmc_idma_setup(struct sunxi_mmc_softc *sc) 252 { 253 int error; 254 255 sc->sc_idma_xferlen = SUNXI_MMC_DMA_XFERLEN; 256 257 sc->sc_idma_ndesc = SUNXI_MMC_NDESC; 258 sc->sc_idma_size = sizeof(struct sunxi_mmc_idma_descriptor) * 259 sc->sc_idma_ndesc; 260 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 0, 261 sc->sc_idma_size, sc->sc_idma_segs, 1, 262 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 263 if (error) 264 return error; 265 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 266 sc->sc_idma_nsegs, sc->sc_idma_size, 267 &sc->sc_idma_desc, BUS_DMA_WAITOK); 268 if (error) 269 goto free; 270 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 271 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 272 if (error) 273 goto unmap; 274 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 275 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 276 if (error) 277 goto destroy; 278 return 0; 279 280 destroy: 281 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 282 unmap: 283 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 284 free: 285 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 286 return error; 287 } 288 289 static int 290 sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq) 291 { 292 return clk_set_rate(sc->sc_clk_mmc, freq * 1000); 293 } 294 295 static void 296 sunxi_mmc_attach_i(device_t self) 297 { 298 struct sunxi_mmc_softc *sc = device_private(self); 299 struct sdmmcbus_attach_args saa; 300 uint32_t width; 301 302 sunxi_mmc_host_reset(sc); 303 sunxi_mmc_bus_width(sc, 1); 304 sunxi_mmc_set_clock(sc, 400); 305 306 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 307 width = 4; 308 309 memset(&saa, 0, sizeof(saa)); 310 saa.saa_busname = "sdmmc"; 311 saa.saa_sct = &sunxi_mmc_chip_functions; 312 saa.saa_sch = sc; 313 saa.saa_dmat = sc->sc_dmat; 314 saa.saa_clkmin = 400; 315 saa.saa_clkmax = 52000; 316 saa.saa_caps = SMC_CAPS_DMA | 317 SMC_CAPS_MULTI_SEG_DMA | 318 SMC_CAPS_AUTO_STOP | 319 SMC_CAPS_SD_HIGHSPEED | 320 SMC_CAPS_MMC_HIGHSPEED; 321 if (width == 4) 322 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 323 if (width == 8) 324 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 325 326 if (sc->sc_gpio_cd) 327 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 328 329 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 330 } 331 332 static int 333 sunxi_mmc_intr(void *priv) 334 { 335 struct sunxi_mmc_softc *sc = priv; 336 uint32_t idst, rint, mint; 337 338 mutex_enter(&sc->sc_intr_lock); 339 idst = MMC_READ(sc, SUNXI_MMC_IDST); 340 rint = MMC_READ(sc, SUNXI_MMC_RINT); 341 mint = MMC_READ(sc, SUNXI_MMC_MINT); 342 if (!idst && !rint && !mint) { 343 mutex_exit(&sc->sc_intr_lock); 344 return 0; 345 } 346 MMC_WRITE(sc, SUNXI_MMC_IDST, idst); 347 MMC_WRITE(sc, SUNXI_MMC_RINT, rint); 348 MMC_WRITE(sc, SUNXI_MMC_MINT, mint); 349 350 #ifdef SUNXI_MMC_DEBUG 351 device_printf(sc->sc_dev, "mmc intr idst=%08X rint=%08X mint=%08X\n", 352 idst, rint, mint); 353 #endif 354 355 if (idst) { 356 sc->sc_idma_idst |= idst; 357 cv_broadcast(&sc->sc_idst_cv); 358 } 359 360 if (rint) { 361 sc->sc_intr_rint |= rint; 362 cv_broadcast(&sc->sc_intr_cv); 363 } 364 365 mutex_exit(&sc->sc_intr_lock); 366 367 return 1; 368 } 369 370 static int 371 sunxi_mmc_wait_rint(struct sunxi_mmc_softc *sc, uint32_t mask, int timeout) 372 { 373 int retry; 374 int error; 375 376 KASSERT(mutex_owned(&sc->sc_intr_lock)); 377 378 if (sc->sc_intr_rint & mask) 379 return 0; 380 381 retry = timeout / hz; 382 383 while (retry > 0) { 384 error = cv_timedwait(&sc->sc_intr_cv, 385 &sc->sc_intr_lock, hz); 386 if (error && error != EWOULDBLOCK) 387 return error; 388 if (sc->sc_intr_rint & mask) 389 return 0; 390 --retry; 391 } 392 393 return ETIMEDOUT; 394 } 395 396 static int 397 sunxi_mmc_host_reset(sdmmc_chipset_handle_t sch) 398 { 399 struct sunxi_mmc_softc *sc = sch; 400 int retry = 1000; 401 402 #ifdef SUNXI_MMC_DEBUG 403 aprint_normal_dev(sc->sc_dev, "host reset\n"); 404 #endif 405 406 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 407 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_RESET); 408 while (--retry > 0) { 409 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 410 break; 411 delay(100); 412 } 413 414 MMC_WRITE(sc, SUNXI_MMC_TIMEOUT, 0xffffffff); 415 416 MMC_WRITE(sc, SUNXI_MMC_IMASK, 417 SUNXI_MMC_INT_CMD_DONE | SUNXI_MMC_INT_ERROR | 418 SUNXI_MMC_INT_DATA_OVER | SUNXI_MMC_INT_AUTO_CMD_DONE); 419 420 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 421 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_INTEN); 422 423 424 return 0; 425 } 426 427 static uint32_t 428 sunxi_mmc_host_ocr(sdmmc_chipset_handle_t sch) 429 { 430 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 431 } 432 433 static int 434 sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 435 { 436 return 8192; 437 } 438 439 static int 440 sunxi_mmc_card_detect(sdmmc_chipset_handle_t sch) 441 { 442 struct sunxi_mmc_softc *sc = sch; 443 444 if (sc->sc_gpio_cd == NULL) { 445 return 1; /* no card detect pin, assume present */ 446 } else { 447 int v = 0, i; 448 for (i = 0; i < 5; i++) { 449 v += (fdtbus_gpio_read(sc->sc_gpio_cd) ^ 450 sc->sc_gpio_cd_inverted); 451 delay(1000); 452 } 453 if (v == 5) 454 sc->sc_mmc_present = 0; 455 else if (v == 0) 456 sc->sc_mmc_present = 1; 457 return sc->sc_mmc_present; 458 } 459 } 460 461 static int 462 sunxi_mmc_write_protect(sdmmc_chipset_handle_t sch) 463 { 464 struct sunxi_mmc_softc *sc = sch; 465 466 if (sc->sc_gpio_wp == NULL) { 467 return 0; /* no write protect pin, assume rw */ 468 } else { 469 return fdtbus_gpio_read(sc->sc_gpio_wp) ^ 470 sc->sc_gpio_wp_inverted; 471 } 472 } 473 474 static int 475 sunxi_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 476 { 477 return 0; 478 } 479 480 static int 481 sunxi_mmc_update_clock(struct sunxi_mmc_softc *sc) 482 { 483 uint32_t cmd; 484 int retry; 485 486 #ifdef SUNXI_MMC_DEBUG 487 aprint_normal_dev(sc->sc_dev, "update clock\n"); 488 #endif 489 490 cmd = SUNXI_MMC_CMD_START | 491 SUNXI_MMC_CMD_UPCLK_ONLY | 492 SUNXI_MMC_CMD_WAIT_PRE_OVER; 493 MMC_WRITE(sc, SUNXI_MMC_CMD, cmd); 494 retry = 0xfffff; 495 while (--retry > 0) { 496 if (!(MMC_READ(sc, SUNXI_MMC_CMD) & SUNXI_MMC_CMD_START)) 497 break; 498 delay(10); 499 } 500 501 if (retry == 0) { 502 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 503 #ifdef SUNXI_MMC_DEBUG 504 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 505 MMC_READ(sc, SUNXI_MMC_GCTRL)); 506 device_printf(sc->sc_dev, "CLKCR: 0x%08x\n", 507 MMC_READ(sc, SUNXI_MMC_CLKCR)); 508 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 509 MMC_READ(sc, SUNXI_MMC_TIMEOUT)); 510 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 511 MMC_READ(sc, SUNXI_MMC_WIDTH)); 512 device_printf(sc->sc_dev, "CMD: 0x%08x\n", 513 MMC_READ(sc, SUNXI_MMC_CMD)); 514 device_printf(sc->sc_dev, "MINT: 0x%08x\n", 515 MMC_READ(sc, SUNXI_MMC_MINT)); 516 device_printf(sc->sc_dev, "RINT: 0x%08x\n", 517 MMC_READ(sc, SUNXI_MMC_RINT)); 518 device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 519 MMC_READ(sc, SUNXI_MMC_STATUS)); 520 #endif 521 return ETIMEDOUT; 522 } 523 524 return 0; 525 } 526 527 static int 528 sunxi_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq) 529 { 530 struct sunxi_mmc_softc *sc = sch; 531 uint32_t clkcr; 532 533 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 534 if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) { 535 clkcr &= ~SUNXI_MMC_CLKCR_CARDCLKON; 536 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 537 if (sunxi_mmc_update_clock(sc) != 0) 538 return 1; 539 } 540 541 if (freq) { 542 543 clkcr &= ~SUNXI_MMC_CLKCR_DIV; 544 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 545 if (sunxi_mmc_update_clock(sc) != 0) 546 return 1; 547 548 if (sunxi_mmc_set_clock(sc, freq) != 0) 549 return 1; 550 551 clkcr |= SUNXI_MMC_CLKCR_CARDCLKON; 552 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 553 if (sunxi_mmc_update_clock(sc) != 0) 554 return 1; 555 } 556 557 return 0; 558 } 559 560 static int 561 sunxi_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 562 { 563 struct sunxi_mmc_softc *sc = sch; 564 565 #ifdef SUNXI_MMC_DEBUG 566 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 567 #endif 568 569 switch (width) { 570 case 1: 571 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_1); 572 break; 573 case 4: 574 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_4); 575 break; 576 case 8: 577 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_8); 578 break; 579 default: 580 return 1; 581 } 582 583 sc->sc_mmc_width = width; 584 585 return 0; 586 } 587 588 static int 589 sunxi_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 590 { 591 return -1; 592 } 593 594 static int 595 sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 596 { 597 struct sunxi_mmc_idma_descriptor *dma = sc->sc_idma_desc; 598 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 599 bus_size_t off; 600 int desc, resid, seg; 601 uint32_t val; 602 603 desc = 0; 604 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 605 bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr; 606 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 607 resid = min(len, cmd->c_resid); 608 off = 0; 609 while (resid > 0) { 610 if (desc == sc->sc_idma_ndesc) 611 break; 612 len = min(sc->sc_idma_xferlen, resid); 613 dma[desc].dma_buf_size = htole32(len); 614 dma[desc].dma_buf_addr = htole32(paddr + off); 615 dma[desc].dma_config = htole32(SUNXI_MMC_IDMA_CONFIG_CH | 616 SUNXI_MMC_IDMA_CONFIG_OWN); 617 cmd->c_resid -= len; 618 resid -= len; 619 off += len; 620 if (desc == 0) { 621 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_FD); 622 } 623 if (cmd->c_resid == 0) { 624 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_LD); 625 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_ER); 626 dma[desc].dma_next = 0; 627 } else { 628 dma[desc].dma_config |= 629 htole32(SUNXI_MMC_IDMA_CONFIG_DIC); 630 dma[desc].dma_next = htole32( 631 desc_paddr + ((desc+1) * 632 sizeof(struct sunxi_mmc_idma_descriptor))); 633 } 634 ++desc; 635 } 636 } 637 if (desc == sc->sc_idma_ndesc) { 638 aprint_error_dev(sc->sc_dev, 639 "not enough descriptors for %d byte transfer!\n", 640 cmd->c_datalen); 641 return EIO; 642 } 643 644 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 645 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 646 647 sc->sc_idma_idst = 0; 648 649 val = MMC_READ(sc, SUNXI_MMC_GCTRL); 650 val |= SUNXI_MMC_GCTRL_DMAEN; 651 val |= SUNXI_MMC_GCTRL_INTEN; 652 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 653 val |= SUNXI_MMC_GCTRL_DMARESET; 654 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 655 MMC_WRITE(sc, SUNXI_MMC_DMAC, SUNXI_MMC_DMAC_SOFTRESET); 656 MMC_WRITE(sc, SUNXI_MMC_DMAC, 657 SUNXI_MMC_DMAC_IDMA_ON|SUNXI_MMC_DMAC_FIX_BURST); 658 val = MMC_READ(sc, SUNXI_MMC_IDIE); 659 val &= ~(SUNXI_MMC_IDST_RECEIVE_INT|SUNXI_MMC_IDST_TRANSMIT_INT); 660 if (cmd->c_flags & SCF_CMD_READ) 661 val |= SUNXI_MMC_IDST_RECEIVE_INT; 662 else 663 val |= SUNXI_MMC_IDST_TRANSMIT_INT; 664 MMC_WRITE(sc, SUNXI_MMC_IDIE, val); 665 MMC_WRITE(sc, SUNXI_MMC_DLBA, desc_paddr); 666 MMC_WRITE(sc, SUNXI_MMC_FTRGLEVEL, sc->sc_dma_ftrglevel); 667 668 return 0; 669 } 670 671 static void 672 sunxi_mmc_dma_complete(struct sunxi_mmc_softc *sc) 673 { 674 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 675 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 676 } 677 678 static void 679 sunxi_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 680 { 681 struct sunxi_mmc_softc *sc = sch; 682 uint32_t cmdval = SUNXI_MMC_CMD_START; 683 int retry; 684 685 #ifdef SUNXI_MMC_DEBUG 686 aprint_normal_dev(sc->sc_dev, 687 "opcode %d flags 0x%x data %p datalen %d blklen %d\n", 688 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 689 cmd->c_blklen); 690 #endif 691 692 mutex_enter(&sc->sc_intr_lock); 693 694 if (cmd->c_opcode == 0) 695 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 696 if (cmd->c_flags & SCF_RSP_PRESENT) 697 cmdval |= SUNXI_MMC_CMD_RSP_EXP; 698 if (cmd->c_flags & SCF_RSP_136) 699 cmdval |= SUNXI_MMC_CMD_LONG_RSP; 700 if (cmd->c_flags & SCF_RSP_CRC) 701 cmdval |= SUNXI_MMC_CMD_CHECK_RSP_CRC; 702 703 if (cmd->c_datalen > 0) { 704 unsigned int nblks; 705 706 cmdval |= SUNXI_MMC_CMD_DATA_EXP | SUNXI_MMC_CMD_WAIT_PRE_OVER; 707 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 708 cmdval |= SUNXI_MMC_CMD_WRITE; 709 } 710 711 nblks = cmd->c_datalen / cmd->c_blklen; 712 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 713 ++nblks; 714 715 if (nblks > 1) { 716 cmdval |= SUNXI_MMC_CMD_SEND_AUTO_STOP; 717 } 718 719 MMC_WRITE(sc, SUNXI_MMC_BLKSZ, cmd->c_blklen); 720 MMC_WRITE(sc, SUNXI_MMC_BYTECNT, nblks * cmd->c_blklen); 721 } 722 723 sc->sc_intr_rint = 0; 724 725 MMC_WRITE(sc, SUNXI_MMC_A12A, 726 (cmdval & SUNXI_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff); 727 728 MMC_WRITE(sc, SUNXI_MMC_ARG, cmd->c_arg); 729 730 #ifdef SUNXI_MMC_DEBUG 731 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 732 #endif 733 734 if (cmd->c_datalen == 0) { 735 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 736 } else { 737 cmd->c_resid = cmd->c_datalen; 738 cmd->c_error = sunxi_mmc_dma_prepare(sc, cmd); 739 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 740 if (cmd->c_error == 0) { 741 const uint32_t idst_mask = 742 SUNXI_MMC_IDST_ERROR | SUNXI_MMC_IDST_COMPLETE; 743 retry = 10; 744 while ((sc->sc_idma_idst & idst_mask) == 0) { 745 if (retry-- == 0) { 746 cmd->c_error = ETIMEDOUT; 747 break; 748 } 749 cv_timedwait(&sc->sc_idst_cv, 750 &sc->sc_intr_lock, hz); 751 } 752 } 753 sunxi_mmc_dma_complete(sc); 754 if (sc->sc_idma_idst & SUNXI_MMC_IDST_ERROR) { 755 cmd->c_error = EIO; 756 } else if (!(sc->sc_idma_idst & SUNXI_MMC_IDST_COMPLETE)) { 757 cmd->c_error = ETIMEDOUT; 758 } 759 if (cmd->c_error) { 760 #ifdef SUNXI_MMC_DEBUG 761 aprint_error_dev(sc->sc_dev, 762 "xfer failed, error %d\n", cmd->c_error); 763 #endif 764 goto done; 765 } 766 } 767 768 cmd->c_error = sunxi_mmc_wait_rint(sc, 769 SUNXI_MMC_INT_ERROR|SUNXI_MMC_INT_CMD_DONE, hz * 10); 770 if (cmd->c_error == 0 && (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 771 if (sc->sc_intr_rint & SUNXI_MMC_INT_RESP_TIMEOUT) { 772 cmd->c_error = ETIMEDOUT; 773 } else { 774 cmd->c_error = EIO; 775 } 776 } 777 if (cmd->c_error) { 778 #ifdef SUNXI_MMC_DEBUG 779 aprint_error_dev(sc->sc_dev, 780 "cmd failed, error %d\n", cmd->c_error); 781 #endif 782 goto done; 783 } 784 785 if (cmd->c_datalen > 0) { 786 cmd->c_error = sunxi_mmc_wait_rint(sc, 787 SUNXI_MMC_INT_ERROR| 788 SUNXI_MMC_INT_AUTO_CMD_DONE| 789 SUNXI_MMC_INT_DATA_OVER, 790 hz*10); 791 if (cmd->c_error == 0 && 792 (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 793 cmd->c_error = ETIMEDOUT; 794 } 795 if (cmd->c_error) { 796 #ifdef SUNXI_MMC_DEBUG 797 aprint_error_dev(sc->sc_dev, 798 "data timeout, rint = %08x\n", 799 sc->sc_intr_rint); 800 #endif 801 cmd->c_error = ETIMEDOUT; 802 goto done; 803 } 804 } 805 806 if (cmd->c_flags & SCF_RSP_PRESENT) { 807 if (cmd->c_flags & SCF_RSP_136) { 808 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 809 cmd->c_resp[1] = MMC_READ(sc, SUNXI_MMC_RESP1); 810 cmd->c_resp[2] = MMC_READ(sc, SUNXI_MMC_RESP2); 811 cmd->c_resp[3] = MMC_READ(sc, SUNXI_MMC_RESP3); 812 if (cmd->c_flags & SCF_RSP_CRC) { 813 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 814 (cmd->c_resp[1] << 24); 815 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 816 (cmd->c_resp[2] << 24); 817 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 818 (cmd->c_resp[3] << 24); 819 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 820 } 821 } else { 822 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 823 } 824 } 825 826 done: 827 cmd->c_flags |= SCF_ITSDONE; 828 mutex_exit(&sc->sc_intr_lock); 829 830 if (cmd->c_error) { 831 #ifdef SUNXI_MMC_DEBUG 832 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 833 #endif 834 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 835 MMC_READ(sc, SUNXI_MMC_GCTRL) | 836 SUNXI_MMC_GCTRL_DMARESET | SUNXI_MMC_GCTRL_FIFORESET); 837 for (retry = 0; retry < 1000; retry++) { 838 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 839 break; 840 delay(10); 841 } 842 sunxi_mmc_update_clock(sc); 843 } 844 845 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 846 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_FIFORESET); 847 } 848 849 static void 850 sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 851 { 852 } 853 854 static void 855 sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 856 { 857 } 858
Indexes created Sat Nov 01 05:10:12 GMT 2025