sunxi_mmc.c revision 1.32
1 /* $NetBSD: sunxi_mmc.c,v 1.32 2019/01/03 15:34:41 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_sunximmc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.32 2019/01/03 15:34:41 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/gpio.h> 41 42 #include <dev/sdmmc/sdmmcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmc_ioreg.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #include <arm/sunxi/sunxi_mmc.h> 49 50 #ifdef SUNXI_MMC_DEBUG 51 static int sunxi_mmc_debug = SUNXI_MMC_DEBUG; 52 #define DPRINTF(dev, fmt, ...) \ 53 do { \ 54 if (sunxi_mmc_debug & __BIT(device_unit(dev))) \ 55 device_printf((dev), fmt, ##__VA_ARGS__); \ 56 } while (0) 57 #else 58 #define DPRINTF(dev, fmt, ...) ((void)0) 59 #endif 60 61 enum sunxi_mmc_timing { 62 SUNXI_MMC_TIMING_400K, 63 SUNXI_MMC_TIMING_25M, 64 SUNXI_MMC_TIMING_50M, 65 SUNXI_MMC_TIMING_50M_DDR, 66 SUNXI_MMC_TIMING_50M_DDR_8BIT, 67 }; 68 69 struct sunxi_mmc_delay { 70 u_int output_phase; 71 u_int sample_phase; 72 }; 73 74 static const struct sunxi_mmc_delay sun7i_mmc_delays[] = { 75 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 76 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 77 [SUNXI_MMC_TIMING_50M] = { 90, 120 }, 78 [SUNXI_MMC_TIMING_50M_DDR] = { 60, 120 }, 79 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 90, 180 }, 80 }; 81 82 static const struct sunxi_mmc_delay sun9i_mmc_delays[] = { 83 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 84 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 85 [SUNXI_MMC_TIMING_50M] = { 150, 120 }, 86 [SUNXI_MMC_TIMING_50M_DDR] = { 54, 36 }, 87 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 72, 72 }, 88 }; 89 90 #define SUNXI_MMC_NDESC 64 91 92 struct sunxi_mmc_softc; 93 94 static int sunxi_mmc_match(device_t, cfdata_t, void *); 95 static void sunxi_mmc_attach(device_t, device_t, void *); 96 static void sunxi_mmc_attach_i(device_t); 97 98 static int sunxi_mmc_intr(void *); 99 static int sunxi_mmc_dmabounce_setup(struct sunxi_mmc_softc *); 100 static int sunxi_mmc_idma_setup(struct sunxi_mmc_softc *); 101 102 static int sunxi_mmc_host_reset(sdmmc_chipset_handle_t); 103 static uint32_t sunxi_mmc_host_ocr(sdmmc_chipset_handle_t); 104 static int sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t); 105 static int sunxi_mmc_card_detect(sdmmc_chipset_handle_t); 106 static int sunxi_mmc_write_protect(sdmmc_chipset_handle_t); 107 static int sunxi_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 108 static int sunxi_mmc_bus_clock(sdmmc_chipset_handle_t, int, bool); 109 static int sunxi_mmc_bus_width(sdmmc_chipset_handle_t, int); 110 static int sunxi_mmc_bus_rod(sdmmc_chipset_handle_t, int); 111 static int sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 112 static int sunxi_mmc_execute_tuning(sdmmc_chipset_handle_t, int); 113 static void sunxi_mmc_exec_command(sdmmc_chipset_handle_t, 114 struct sdmmc_command *); 115 static void sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 116 static void sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t); 117 118 static struct sdmmc_chip_functions sunxi_mmc_chip_functions = { 119 .host_reset = sunxi_mmc_host_reset, 120 .host_ocr = sunxi_mmc_host_ocr, 121 .host_maxblklen = sunxi_mmc_host_maxblklen, 122 .card_detect = sunxi_mmc_card_detect, 123 .write_protect = sunxi_mmc_write_protect, 124 .bus_power = sunxi_mmc_bus_power, 125 .bus_clock_ddr = sunxi_mmc_bus_clock, 126 .bus_width = sunxi_mmc_bus_width, 127 .bus_rod = sunxi_mmc_bus_rod, 128 .signal_voltage = sunxi_mmc_signal_voltage, 129 .execute_tuning = sunxi_mmc_execute_tuning, 130 .exec_command = sunxi_mmc_exec_command, 131 .card_enable_intr = sunxi_mmc_card_enable_intr, 132 .card_intr_ack = sunxi_mmc_card_intr_ack, 133 }; 134 135 struct sunxi_mmc_config { 136 u_int idma_xferlen; 137 u_int flags; 138 #define SUNXI_MMC_FLAG_CALIB_REG 0x01 139 #define SUNXI_MMC_FLAG_NEW_TIMINGS 0x02 140 #define SUNXI_MMC_FLAG_MASK_DATA0 0x04 141 #define SUNXI_MMC_FLAG_HS200 0x08 142 const struct sunxi_mmc_delay *delays; 143 uint32_t dma_ftrglevel; 144 }; 145 146 struct sunxi_mmc_softc { 147 device_t sc_dev; 148 bus_space_tag_t sc_bst; 149 bus_space_handle_t sc_bsh; 150 bus_dma_tag_t sc_dmat; 151 int sc_phandle; 152 153 void *sc_ih; 154 kmutex_t sc_intr_lock; 155 kcondvar_t sc_intr_cv; 156 kcondvar_t sc_idst_cv; 157 158 int sc_mmc_width; 159 int sc_mmc_present; 160 161 u_int sc_max_frequency; 162 163 device_t sc_sdmmc_dev; 164 165 struct sunxi_mmc_config *sc_config; 166 167 bus_dma_segment_t sc_idma_segs[1]; 168 int sc_idma_nsegs; 169 bus_size_t sc_idma_size; 170 bus_dmamap_t sc_idma_map; 171 int sc_idma_ndesc; 172 void *sc_idma_desc; 173 174 bus_dmamap_t sc_dmabounce_map; 175 void *sc_dmabounce_buf; 176 size_t sc_dmabounce_buflen; 177 178 uint32_t sc_intr_rint; 179 uint32_t sc_idma_idst; 180 181 struct clk *sc_clk_ahb; 182 struct clk *sc_clk_mmc; 183 struct clk *sc_clk_output; 184 struct clk *sc_clk_sample; 185 186 struct fdtbus_reset *sc_rst_ahb; 187 188 struct fdtbus_gpio_pin *sc_gpio_cd; 189 int sc_gpio_cd_inverted; 190 struct fdtbus_gpio_pin *sc_gpio_wp; 191 int sc_gpio_wp_inverted; 192 193 struct fdtbus_regulator *sc_reg_vmmc; 194 struct fdtbus_regulator *sc_reg_vqmmc; 195 196 struct fdtbus_mmc_pwrseq *sc_pwrseq; 197 198 bool sc_non_removable; 199 bool sc_broken_cd; 200 }; 201 202 CFATTACH_DECL_NEW(sunxi_mmc, sizeof(struct sunxi_mmc_softc), 203 sunxi_mmc_match, sunxi_mmc_attach, NULL, NULL); 204 205 #define MMC_WRITE(sc, reg, val) \ 206 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 207 #define MMC_READ(sc, reg) \ 208 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 209 210 static const struct sunxi_mmc_config sun4i_a10_mmc_config = { 211 .idma_xferlen = 0x2000, 212 .dma_ftrglevel = 0x20070008, 213 .delays = NULL, 214 .flags = 0, 215 }; 216 217 static const struct sunxi_mmc_config sun5i_a13_mmc_config = { 218 .idma_xferlen = 0x10000, 219 .dma_ftrglevel = 0x20070008, 220 .delays = NULL, 221 .flags = 0, 222 }; 223 224 static const struct sunxi_mmc_config sun7i_a20_mmc_config = { 225 .idma_xferlen = 0x2000, 226 .dma_ftrglevel = 0x20070008, 227 .delays = sun7i_mmc_delays, 228 .flags = 0, 229 }; 230 231 static const struct sunxi_mmc_config sun8i_a83t_emmc_config = { 232 .idma_xferlen = 0x10000, 233 .dma_ftrglevel = 0x20070008, 234 .delays = NULL, 235 .flags = SUNXI_MMC_FLAG_NEW_TIMINGS, 236 }; 237 238 static const struct sunxi_mmc_config sun9i_a80_mmc_config = { 239 .idma_xferlen = 0x10000, 240 .dma_ftrglevel = 0x200f0010, 241 .delays = sun9i_mmc_delays, 242 .flags = 0, 243 }; 244 245 static const struct sunxi_mmc_config sun50i_a64_mmc_config = { 246 .idma_xferlen = 0x10000, 247 .dma_ftrglevel = 0x20070008, 248 .delays = NULL, 249 .flags = SUNXI_MMC_FLAG_CALIB_REG | 250 SUNXI_MMC_FLAG_NEW_TIMINGS | 251 SUNXI_MMC_FLAG_MASK_DATA0, 252 }; 253 254 static const struct sunxi_mmc_config sun50i_a64_emmc_config = { 255 .idma_xferlen = 0x2000, 256 .dma_ftrglevel = 0x20070008, 257 .delays = NULL, 258 .flags = SUNXI_MMC_FLAG_CALIB_REG | 259 SUNXI_MMC_FLAG_NEW_TIMINGS | 260 SUNXI_MMC_FLAG_HS200, 261 }; 262 263 static const struct sunxi_mmc_config sun50i_h6_mmc_config = { 264 .idma_xferlen = 0x10000, 265 .dma_ftrglevel = 0x20070008, 266 .delays = NULL, 267 .flags = SUNXI_MMC_FLAG_CALIB_REG | 268 SUNXI_MMC_FLAG_NEW_TIMINGS | 269 SUNXI_MMC_FLAG_MASK_DATA0, 270 }; 271 272 static const struct sunxi_mmc_config sun50i_h6_emmc_config = { 273 .idma_xferlen = 0x2000, 274 .dma_ftrglevel = 0x20070008, 275 .delays = NULL, 276 .flags = SUNXI_MMC_FLAG_CALIB_REG, 277 }; 278 279 static const struct of_compat_data compat_data[] = { 280 { "allwinner,sun4i-a10-mmc", (uintptr_t)&sun4i_a10_mmc_config }, 281 { "allwinner,sun5i-a13-mmc", (uintptr_t)&sun5i_a13_mmc_config }, 282 { "allwinner,sun7i-a20-mmc", (uintptr_t)&sun7i_a20_mmc_config }, 283 { "allwinner,sun8i-a83t-emmc", (uintptr_t)&sun8i_a83t_emmc_config }, 284 { "allwinner,sun9i-a80-mmc", (uintptr_t)&sun9i_a80_mmc_config }, 285 { "allwinner,sun50i-a64-mmc", (uintptr_t)&sun50i_a64_mmc_config }, 286 { "allwinner,sun50i-a64-emmc", (uintptr_t)&sun50i_a64_emmc_config }, 287 { "allwinner,sun50i-h6-mmc", (uintptr_t)&sun50i_h6_mmc_config }, 288 { "allwinner,sun50i-h6-emmc", (uintptr_t)&sun50i_h6_emmc_config }, 289 { NULL } 290 }; 291 292 static int 293 sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux) 294 { 295 struct fdt_attach_args * const faa = aux; 296 297 return of_match_compat_data(faa->faa_phandle, compat_data); 298 } 299 300 static void 301 sunxi_mmc_attach(device_t parent, device_t self, void *aux) 302 { 303 struct sunxi_mmc_softc * const sc = device_private(self); 304 struct fdt_attach_args * const faa = aux; 305 const int phandle = faa->faa_phandle; 306 char intrstr[128]; 307 bus_addr_t addr; 308 bus_size_t size; 309 310 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 311 aprint_error(": couldn't get registers\n"); 312 return; 313 } 314 315 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 316 sc->sc_clk_mmc = fdtbus_clock_get(phandle, "mmc"); 317 sc->sc_clk_output = fdtbus_clock_get(phandle, "output"); 318 sc->sc_clk_sample = fdtbus_clock_get(phandle, "sample"); 319 320 #if notyet 321 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL || 322 sc->sc_clk_output == NULL || sc->sc_clk_sample == NULL) { 323 #else 324 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL) { 325 #endif 326 aprint_error(": couldn't get clocks\n"); 327 return; 328 } 329 330 sc->sc_rst_ahb = fdtbus_reset_get(phandle, "ahb"); 331 332 sc->sc_pwrseq = fdtbus_mmc_pwrseq_get(phandle); 333 334 if (clk_enable(sc->sc_clk_ahb) != 0 || 335 clk_enable(sc->sc_clk_mmc) != 0) { 336 aprint_error(": couldn't enable clocks\n"); 337 return; 338 } 339 340 if (sc->sc_rst_ahb != NULL) { 341 if (fdtbus_reset_deassert(sc->sc_rst_ahb) != 0) { 342 aprint_error(": couldn't de-assert resets\n"); 343 return; 344 } 345 } 346 347 sc->sc_dev = self; 348 sc->sc_phandle = phandle; 349 sc->sc_config = (void *)of_search_compatible(phandle, compat_data)->data; 350 sc->sc_bst = faa->faa_bst; 351 sc->sc_dmat = faa->faa_dmat; 352 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 353 cv_init(&sc->sc_intr_cv, "awinmmcirq"); 354 cv_init(&sc->sc_idst_cv, "awinmmcdma"); 355 356 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 357 aprint_error(": couldn't map registers\n"); 358 return; 359 } 360 361 aprint_naive("\n"); 362 aprint_normal(": SD/MMC controller\n"); 363 364 sc->sc_reg_vmmc = fdtbus_regulator_acquire(phandle, "vmmc-supply"); 365 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(phandle, "vqmmc-supply"); 366 367 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 368 GPIO_PIN_INPUT); 369 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 370 GPIO_PIN_INPUT); 371 372 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 0 : 1; 373 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 0 : 1; 374 375 sc->sc_non_removable = of_hasprop(phandle, "non-removable"); 376 sc->sc_broken_cd = of_hasprop(phandle, "broken-cd"); 377 378 if (of_getprop_uint32(phandle, "max-frequency", &sc->sc_max_frequency)) 379 sc->sc_max_frequency = 52000000; 380 381 if (sunxi_mmc_dmabounce_setup(sc) != 0 || 382 sunxi_mmc_idma_setup(sc) != 0) { 383 aprint_error_dev(self, "failed to setup DMA\n"); 384 return; 385 } 386 387 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 388 aprint_error_dev(self, "failed to decode interrupt\n"); 389 return; 390 } 391 392 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, FDT_INTR_MPSAFE, 393 sunxi_mmc_intr, sc); 394 if (sc->sc_ih == NULL) { 395 aprint_error_dev(self, "failed to establish interrupt on %s\n", 396 intrstr); 397 return; 398 } 399 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 400 401 config_interrupts(self, sunxi_mmc_attach_i); 402 } 403 404 static int 405 sunxi_mmc_dmabounce_setup(struct sunxi_mmc_softc *sc) 406 { 407 bus_dma_segment_t ds[1]; 408 int error, rseg; 409 410 sc->sc_dmabounce_buflen = sunxi_mmc_host_maxblklen(sc); 411 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_dmabounce_buflen, 0, 412 sc->sc_dmabounce_buflen, ds, 1, &rseg, BUS_DMA_WAITOK); 413 if (error) 414 return error; 415 error = bus_dmamem_map(sc->sc_dmat, ds, 1, sc->sc_dmabounce_buflen, 416 &sc->sc_dmabounce_buf, BUS_DMA_WAITOK); 417 if (error) 418 goto free; 419 error = bus_dmamap_create(sc->sc_dmat, sc->sc_dmabounce_buflen, 1, 420 sc->sc_dmabounce_buflen, 0, BUS_DMA_WAITOK, &sc->sc_dmabounce_map); 421 if (error) 422 goto unmap; 423 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmabounce_map, 424 sc->sc_dmabounce_buf, sc->sc_dmabounce_buflen, NULL, 425 BUS_DMA_WAITOK); 426 if (error) 427 goto destroy; 428 return 0; 429 430 destroy: 431 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmabounce_map); 432 unmap: 433 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dmabounce_buf, 434 sc->sc_dmabounce_buflen); 435 free: 436 bus_dmamem_free(sc->sc_dmat, ds, rseg); 437 return error; 438 } 439 440 static int 441 sunxi_mmc_idma_setup(struct sunxi_mmc_softc *sc) 442 { 443 int error; 444 445 sc->sc_idma_ndesc = SUNXI_MMC_NDESC; 446 sc->sc_idma_size = sizeof(struct sunxi_mmc_idma_descriptor) * 447 sc->sc_idma_ndesc; 448 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 0, 449 sc->sc_idma_size, sc->sc_idma_segs, 1, 450 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 451 if (error) 452 return error; 453 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 454 sc->sc_idma_nsegs, sc->sc_idma_size, 455 &sc->sc_idma_desc, BUS_DMA_WAITOK); 456 if (error) 457 goto free; 458 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 459 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 460 if (error) 461 goto unmap; 462 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 463 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 464 if (error) 465 goto destroy; 466 return 0; 467 468 destroy: 469 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 470 unmap: 471 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 472 free: 473 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 474 return error; 475 } 476 477 static int 478 sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr) 479 { 480 const struct sunxi_mmc_delay *delays; 481 int error, timing = SUNXI_MMC_TIMING_400K; 482 483 if (sc->sc_config->delays) { 484 if (freq <= 400) { 485 timing = SUNXI_MMC_TIMING_400K; 486 } else if (freq <= 25000) { 487 timing = SUNXI_MMC_TIMING_25M; 488 } else if (freq <= 52000) { 489 if (ddr) { 490 timing = sc->sc_mmc_width == 8 ? 491 SUNXI_MMC_TIMING_50M_DDR_8BIT : 492 SUNXI_MMC_TIMING_50M_DDR; 493 } else { 494 timing = SUNXI_MMC_TIMING_50M; 495 } 496 } else 497 return EINVAL; 498 } 499 if (sc->sc_max_frequency) { 500 if (freq * 1000 > sc->sc_max_frequency) 501 return EINVAL; 502 } 503 504 error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << ddr); 505 if (error != 0) 506 return error; 507 508 if (sc->sc_config->delays == NULL) 509 return 0; 510 511 delays = &sc->sc_config->delays[timing]; 512 513 if (sc->sc_clk_sample) { 514 error = clk_set_rate(sc->sc_clk_sample, delays->sample_phase); 515 if (error != 0) 516 return error; 517 } 518 if (sc->sc_clk_output) { 519 error = clk_set_rate(sc->sc_clk_output, delays->output_phase); 520 if (error != 0) 521 return error; 522 } 523 524 return 0; 525 } 526 527 static void 528 sunxi_mmc_hw_reset(struct sunxi_mmc_softc *sc) 529 { 530 MMC_WRITE(sc, SUNXI_MMC_HWRST, 0); 531 delay(1000); 532 MMC_WRITE(sc, SUNXI_MMC_HWRST, 1); 533 delay(1000); 534 } 535 536 static void 537 sunxi_mmc_attach_i(device_t self) 538 { 539 struct sunxi_mmc_softc *sc = device_private(self); 540 const u_int flags = sc->sc_config->flags; 541 struct sdmmcbus_attach_args saa; 542 uint32_t width; 543 544 if (sc->sc_pwrseq) 545 fdtbus_mmc_pwrseq_pre_power_on(sc->sc_pwrseq); 546 547 if (of_hasprop(sc->sc_phandle, "cap-mmc-hw-reset")) 548 sunxi_mmc_hw_reset(sc); 549 550 sunxi_mmc_host_reset(sc); 551 sunxi_mmc_bus_width(sc, 1); 552 sunxi_mmc_set_clock(sc, 400, false); 553 554 if (sc->sc_pwrseq) 555 fdtbus_mmc_pwrseq_post_power_on(sc->sc_pwrseq); 556 557 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 558 width = 4; 559 560 memset(&saa, 0, sizeof(saa)); 561 saa.saa_busname = "sdmmc"; 562 saa.saa_sct = &sunxi_mmc_chip_functions; 563 saa.saa_sch = sc; 564 saa.saa_dmat = sc->sc_dmat; 565 saa.saa_clkmin = 400; 566 saa.saa_clkmax = sc->sc_max_frequency / 1000; 567 saa.saa_caps = SMC_CAPS_DMA | 568 SMC_CAPS_MULTI_SEG_DMA | 569 SMC_CAPS_AUTO_STOP | 570 SMC_CAPS_SD_HIGHSPEED | 571 SMC_CAPS_MMC_HIGHSPEED | 572 SMC_CAPS_POLLING; 573 574 if (sc->sc_config->delays || (flags & SUNXI_MMC_FLAG_NEW_TIMINGS)) 575 saa.saa_caps |= SMC_CAPS_MMC_DDR52; 576 577 if (flags & SUNXI_MMC_FLAG_HS200) 578 saa.saa_caps |= SMC_CAPS_MMC_HS200; 579 580 if (width == 4) 581 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 582 if (width == 8) 583 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 584 585 if (sc->sc_gpio_cd) 586 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 587 588 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 589 } 590 591 static int 592 sunxi_mmc_intr(void *priv) 593 { 594 struct sunxi_mmc_softc *sc = priv; 595 uint32_t idst, rint, imask; 596 597 mutex_enter(&sc->sc_intr_lock); 598 idst = MMC_READ(sc, SUNXI_MMC_IDST); 599 rint = MMC_READ(sc, SUNXI_MMC_RINT); 600 if (!idst && !rint) { 601 mutex_exit(&sc->sc_intr_lock); 602 return 0; 603 } 604 MMC_WRITE(sc, SUNXI_MMC_IDST, idst); 605 MMC_WRITE(sc, SUNXI_MMC_RINT, rint & ~SUNXI_MMC_INT_SDIO_INT); 606 607 DPRINTF(sc->sc_dev, "mmc intr idst=%08X rint=%08X\n", 608 idst, rint); 609 610 if (idst != 0) { 611 MMC_WRITE(sc, SUNXI_MMC_IDIE, 0); 612 sc->sc_idma_idst |= idst; 613 cv_broadcast(&sc->sc_idst_cv); 614 } 615 616 if ((rint & ~SUNXI_MMC_INT_SDIO_INT) != 0) { 617 imask = MMC_READ(sc, SUNXI_MMC_IMASK); 618 MMC_WRITE(sc, SUNXI_MMC_IMASK, imask & ~SUNXI_MMC_INT_SDIO_INT); 619 sc->sc_intr_rint |= (rint & ~SUNXI_MMC_INT_SDIO_INT); 620 cv_broadcast(&sc->sc_intr_cv); 621 } 622 623 if ((rint & SUNXI_MMC_INT_SDIO_INT) != 0) { 624 sdmmc_card_intr(sc->sc_sdmmc_dev); 625 } 626 627 mutex_exit(&sc->sc_intr_lock); 628 629 return 1; 630 } 631 632 static int 633 sunxi_mmc_wait_rint(struct sunxi_mmc_softc *sc, uint32_t mask, 634 int timeout, bool poll) 635 { 636 int retry; 637 int error; 638 639 KASSERT(mutex_owned(&sc->sc_intr_lock)); 640 641 if (sc->sc_intr_rint & mask) 642 return 0; 643 644 if (poll) 645 retry = timeout / hz * 1000; 646 else 647 retry = timeout / hz; 648 649 while (retry > 0) { 650 if (poll) { 651 sc->sc_intr_rint |= MMC_READ(sc, SUNXI_MMC_RINT); 652 } else { 653 error = cv_timedwait(&sc->sc_intr_cv, 654 &sc->sc_intr_lock, hz); 655 if (error && error != EWOULDBLOCK) 656 return error; 657 } 658 if (sc->sc_intr_rint & mask) 659 return 0; 660 if (poll) 661 delay(1000); 662 --retry; 663 } 664 665 return ETIMEDOUT; 666 } 667 668 static int 669 sunxi_mmc_host_reset(sdmmc_chipset_handle_t sch) 670 { 671 struct sunxi_mmc_softc *sc = sch; 672 uint32_t gctrl; 673 int retry = 1000; 674 675 DPRINTF(sc->sc_dev, "host reset\n"); 676 677 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 678 gctrl |= SUNXI_MMC_GCTRL_RESET; 679 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 680 while (--retry > 0) { 681 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 682 break; 683 delay(100); 684 } 685 686 MMC_WRITE(sc, SUNXI_MMC_TIMEOUT, 0xffffffff); 687 688 MMC_WRITE(sc, SUNXI_MMC_IMASK, 0); 689 690 MMC_WRITE(sc, SUNXI_MMC_RINT, 0xffffffff); 691 692 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 693 gctrl |= SUNXI_MMC_GCTRL_INTEN; 694 gctrl &= ~SUNXI_MMC_GCTRL_WAIT_MEM_ACCESS_DONE; 695 gctrl &= ~SUNXI_MMC_GCTRL_ACCESS_BY_AHB; 696 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 697 698 return 0; 699 } 700 701 static uint32_t 702 sunxi_mmc_host_ocr(sdmmc_chipset_handle_t sch) 703 { 704 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 705 } 706 707 static int 708 sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 709 { 710 return 8192; 711 } 712 713 static int 714 sunxi_mmc_card_detect(sdmmc_chipset_handle_t sch) 715 { 716 struct sunxi_mmc_softc *sc = sch; 717 718 if (sc->sc_non_removable || sc->sc_broken_cd) { 719 /* 720 * Non-removable or broken card detect flag set in 721 * DT, assume always present 722 */ 723 return 1; 724 } else if (sc->sc_gpio_cd != NULL) { 725 /* Use card detect GPIO */ 726 int v = 0, i; 727 for (i = 0; i < 5; i++) { 728 v += (fdtbus_gpio_read(sc->sc_gpio_cd) ^ 729 sc->sc_gpio_cd_inverted); 730 delay(1000); 731 } 732 if (v == 5) 733 sc->sc_mmc_present = 0; 734 else if (v == 0) 735 sc->sc_mmc_present = 1; 736 return sc->sc_mmc_present; 737 } else { 738 /* Use CARD_PRESENT field of SD_STATUS register */ 739 const uint32_t present = MMC_READ(sc, SUNXI_MMC_STATUS) & 740 SUNXI_MMC_STATUS_CARD_PRESENT; 741 return present != 0; 742 } 743 } 744 745 static int 746 sunxi_mmc_write_protect(sdmmc_chipset_handle_t sch) 747 { 748 struct sunxi_mmc_softc *sc = sch; 749 750 if (sc->sc_gpio_wp == NULL) { 751 return 0; /* no write protect pin, assume rw */ 752 } else { 753 return fdtbus_gpio_read(sc->sc_gpio_wp) ^ 754 sc->sc_gpio_wp_inverted; 755 } 756 } 757 758 static int 759 sunxi_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 760 { 761 return 0; 762 } 763 764 static int 765 sunxi_mmc_update_clock(struct sunxi_mmc_softc *sc) 766 { 767 uint32_t cmd; 768 int retry; 769 770 DPRINTF(sc->sc_dev, "update clock\n"); 771 772 cmd = SUNXI_MMC_CMD_START | 773 SUNXI_MMC_CMD_UPCLK_ONLY | 774 SUNXI_MMC_CMD_WAIT_PRE_OVER; 775 MMC_WRITE(sc, SUNXI_MMC_CMD, cmd); 776 retry = 100000; 777 while (--retry > 0) { 778 if (!(MMC_READ(sc, SUNXI_MMC_CMD) & SUNXI_MMC_CMD_START)) 779 break; 780 delay(10); 781 } 782 783 if (retry == 0) { 784 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 785 DPRINTF(sc->sc_dev, "GCTRL: 0x%08x\n", 786 MMC_READ(sc, SUNXI_MMC_GCTRL)); 787 DPRINTF(sc->sc_dev, "CLKCR: 0x%08x\n", 788 MMC_READ(sc, SUNXI_MMC_CLKCR)); 789 DPRINTF(sc->sc_dev, "TIMEOUT: 0x%08x\n", 790 MMC_READ(sc, SUNXI_MMC_TIMEOUT)); 791 DPRINTF(sc->sc_dev, "WIDTH: 0x%08x\n", 792 MMC_READ(sc, SUNXI_MMC_WIDTH)); 793 DPRINTF(sc->sc_dev, "CMD: 0x%08x\n", 794 MMC_READ(sc, SUNXI_MMC_CMD)); 795 DPRINTF(sc->sc_dev, "MINT: 0x%08x\n", 796 MMC_READ(sc, SUNXI_MMC_MINT)); 797 DPRINTF(sc->sc_dev, "RINT: 0x%08x\n", 798 MMC_READ(sc, SUNXI_MMC_RINT)); 799 DPRINTF(sc->sc_dev, "STATUS: 0x%08x\n", 800 MMC_READ(sc, SUNXI_MMC_STATUS)); 801 return ETIMEDOUT; 802 } 803 804 return 0; 805 } 806 807 static int 808 sunxi_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 809 { 810 struct sunxi_mmc_softc *sc = sch; 811 uint32_t clkcr, gctrl, ntsr; 812 const u_int flags = sc->sc_config->flags; 813 814 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 815 if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) { 816 clkcr &= ~SUNXI_MMC_CLKCR_CARDCLKON; 817 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 818 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 819 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 820 if (sunxi_mmc_update_clock(sc) != 0) 821 return 1; 822 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 823 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 824 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 825 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 826 } 827 } 828 829 if (freq) { 830 831 clkcr &= ~SUNXI_MMC_CLKCR_DIV; 832 clkcr |= __SHIFTIN(ddr, SUNXI_MMC_CLKCR_DIV); 833 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 834 835 if (flags & SUNXI_MMC_FLAG_NEW_TIMINGS) { 836 ntsr = MMC_READ(sc, SUNXI_MMC_NTSR); 837 ntsr |= SUNXI_MMC_NTSR_MODE_SELECT; 838 MMC_WRITE(sc, SUNXI_MMC_NTSR, ntsr); 839 } 840 841 if (flags & SUNXI_MMC_FLAG_CALIB_REG) 842 MMC_WRITE(sc, SUNXI_MMC_SAMP_DL, SUNXI_MMC_SAMP_DL_SW_EN); 843 844 if (sunxi_mmc_update_clock(sc) != 0) 845 return 1; 846 847 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 848 if (ddr) 849 gctrl |= SUNXI_MMC_GCTRL_DDR_MODE; 850 else 851 gctrl &= ~SUNXI_MMC_GCTRL_DDR_MODE; 852 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 853 854 if (sunxi_mmc_set_clock(sc, freq, ddr) != 0) 855 return 1; 856 857 clkcr |= SUNXI_MMC_CLKCR_CARDCLKON; 858 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 859 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 860 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 861 if (sunxi_mmc_update_clock(sc) != 0) 862 return 1; 863 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 864 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 865 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 866 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 867 } 868 } 869 870 return 0; 871 } 872 873 static int 874 sunxi_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 875 { 876 struct sunxi_mmc_softc *sc = sch; 877 878 DPRINTF(sc->sc_dev, "width = %d\n", width); 879 880 switch (width) { 881 case 1: 882 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_1); 883 break; 884 case 4: 885 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_4); 886 break; 887 case 8: 888 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_8); 889 break; 890 default: 891 return 1; 892 } 893 894 sc->sc_mmc_width = width; 895 896 return 0; 897 } 898 899 static int 900 sunxi_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 901 { 902 return -1; 903 } 904 905 static int 906 sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 907 { 908 struct sunxi_mmc_softc *sc = sch; 909 u_int uvol; 910 int error; 911 912 if (sc->sc_reg_vqmmc == NULL) 913 return 0; 914 915 switch (signal_voltage) { 916 case SDMMC_SIGNAL_VOLTAGE_330: 917 uvol = 3300000; 918 break; 919 case SDMMC_SIGNAL_VOLTAGE_180: 920 uvol = 1800000; 921 break; 922 default: 923 return EINVAL; 924 } 925 926 error = fdtbus_regulator_supports_voltage(sc->sc_reg_vqmmc, uvol, uvol); 927 if (error != 0) 928 return 0; 929 930 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 931 if (error != 0) 932 return error; 933 934 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 935 } 936 937 static int 938 sunxi_mmc_execute_tuning(sdmmc_chipset_handle_t sch, int timing) 939 { 940 switch (timing) { 941 case SDMMC_TIMING_MMC_HS200: 942 break; 943 default: 944 return EINVAL; 945 } 946 947 return 0; 948 } 949 950 static int 951 sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 952 { 953 struct sunxi_mmc_idma_descriptor *dma = sc->sc_idma_desc; 954 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 955 bus_dmamap_t map; 956 bus_size_t off; 957 int desc, resid, seg; 958 uint32_t val; 959 960 /* 961 * If the command includes a dma map use it, otherwise we need to 962 * bounce. This can happen for SDIO IO_RW_EXTENDED (CMD53) commands. 963 */ 964 if (cmd->c_dmamap) { 965 map = cmd->c_dmamap; 966 } else { 967 if (cmd->c_datalen > sc->sc_dmabounce_buflen) 968 return E2BIG; 969 map = sc->sc_dmabounce_map; 970 971 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 972 memset(sc->sc_dmabounce_buf, 0, cmd->c_datalen); 973 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 974 0, cmd->c_datalen, BUS_DMASYNC_PREREAD); 975 } else { 976 memcpy(sc->sc_dmabounce_buf, cmd->c_data, 977 cmd->c_datalen); 978 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 979 0, cmd->c_datalen, BUS_DMASYNC_PREWRITE); 980 } 981 } 982 983 desc = 0; 984 for (seg = 0; seg < map->dm_nsegs; seg++) { 985 bus_addr_t paddr = map->dm_segs[seg].ds_addr; 986 bus_size_t len = map->dm_segs[seg].ds_len; 987 resid = uimin(len, cmd->c_resid); 988 off = 0; 989 while (resid > 0) { 990 if (desc == sc->sc_idma_ndesc) 991 break; 992 len = uimin(sc->sc_config->idma_xferlen, resid); 993 dma[desc].dma_buf_size = htole32(len); 994 dma[desc].dma_buf_addr = htole32(paddr + off); 995 dma[desc].dma_config = htole32(SUNXI_MMC_IDMA_CONFIG_CH | 996 SUNXI_MMC_IDMA_CONFIG_OWN); 997 cmd->c_resid -= len; 998 resid -= len; 999 off += len; 1000 if (desc == 0) { 1001 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_FD); 1002 } 1003 if (cmd->c_resid == 0) { 1004 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_LD); 1005 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_ER); 1006 dma[desc].dma_next = 0; 1007 } else { 1008 dma[desc].dma_config |= 1009 htole32(SUNXI_MMC_IDMA_CONFIG_DIC); 1010 dma[desc].dma_next = htole32( 1011 desc_paddr + ((desc+1) * 1012 sizeof(struct sunxi_mmc_idma_descriptor))); 1013 } 1014 ++desc; 1015 } 1016 } 1017 if (desc == sc->sc_idma_ndesc) { 1018 aprint_error_dev(sc->sc_dev, 1019 "not enough descriptors for %d byte transfer! " 1020 "there are %u segments with a max xfer length of %u\n", 1021 cmd->c_datalen, map->dm_nsegs, sc->sc_config->idma_xferlen); 1022 return EIO; 1023 } 1024 1025 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 1026 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 1027 1028 sc->sc_idma_idst = 0; 1029 1030 MMC_WRITE(sc, SUNXI_MMC_DLBA, desc_paddr); 1031 MMC_WRITE(sc, SUNXI_MMC_FTRGLEVEL, sc->sc_config->dma_ftrglevel); 1032 1033 val = MMC_READ(sc, SUNXI_MMC_GCTRL); 1034 val |= SUNXI_MMC_GCTRL_DMAEN; 1035 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 1036 val |= SUNXI_MMC_GCTRL_DMARESET; 1037 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 1038 1039 MMC_WRITE(sc, SUNXI_MMC_DMAC, SUNXI_MMC_DMAC_SOFTRESET); 1040 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1041 val = SUNXI_MMC_IDST_RECEIVE_INT; 1042 else 1043 val = 0; 1044 MMC_WRITE(sc, SUNXI_MMC_IDIE, val); 1045 MMC_WRITE(sc, SUNXI_MMC_DMAC, 1046 SUNXI_MMC_DMAC_IDMA_ON|SUNXI_MMC_DMAC_FIX_BURST); 1047 1048 return 0; 1049 } 1050 1051 static void 1052 sunxi_mmc_dma_complete(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 1053 { 1054 MMC_WRITE(sc, SUNXI_MMC_DMAC, 0); 1055 1056 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 1057 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 1058 1059 if (cmd->c_dmamap == NULL) { 1060 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1061 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 1062 0, cmd->c_datalen, BUS_DMASYNC_POSTREAD); 1063 memcpy(cmd->c_data, sc->sc_dmabounce_buf, 1064 cmd->c_datalen); 1065 } else { 1066 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 1067 0, cmd->c_datalen, BUS_DMASYNC_POSTWRITE); 1068 } 1069 } 1070 } 1071 1072 static void 1073 sunxi_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1074 { 1075 struct sunxi_mmc_softc *sc = sch; 1076 uint32_t cmdval = SUNXI_MMC_CMD_START; 1077 uint32_t imask, oimask; 1078 const bool poll = (cmd->c_flags & SCF_POLL) != 0; 1079 int retry; 1080 1081 DPRINTF(sc->sc_dev, 1082 "opcode %d flags 0x%x data %p datalen %d blklen %d poll %d\n", 1083 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 1084 cmd->c_blklen, poll); 1085 1086 mutex_enter(&sc->sc_intr_lock); 1087 1088 if (cmd->c_opcode == 0) 1089 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 1090 if (cmd->c_flags & SCF_RSP_PRESENT) 1091 cmdval |= SUNXI_MMC_CMD_RSP_EXP; 1092 if (cmd->c_flags & SCF_RSP_136) 1093 cmdval |= SUNXI_MMC_CMD_LONG_RSP; 1094 if (cmd->c_flags & SCF_RSP_CRC) 1095 cmdval |= SUNXI_MMC_CMD_CHECK_RSP_CRC; 1096 1097 imask = oimask = MMC_READ(sc, SUNXI_MMC_IMASK); 1098 imask |= SUNXI_MMC_INT_ERROR; 1099 1100 if (cmd->c_datalen > 0) { 1101 unsigned int nblks; 1102 1103 cmdval |= SUNXI_MMC_CMD_DATA_EXP | SUNXI_MMC_CMD_WAIT_PRE_OVER; 1104 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 1105 cmdval |= SUNXI_MMC_CMD_WRITE; 1106 } 1107 1108 nblks = cmd->c_datalen / cmd->c_blklen; 1109 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 1110 ++nblks; 1111 1112 if (nblks > 1) { 1113 cmdval |= SUNXI_MMC_CMD_SEND_AUTO_STOP; 1114 imask |= SUNXI_MMC_INT_AUTO_CMD_DONE; 1115 } else { 1116 imask |= SUNXI_MMC_INT_DATA_OVER; 1117 } 1118 1119 MMC_WRITE(sc, SUNXI_MMC_BLKSZ, cmd->c_blklen); 1120 MMC_WRITE(sc, SUNXI_MMC_BYTECNT, nblks * cmd->c_blklen); 1121 } else { 1122 imask |= SUNXI_MMC_INT_CMD_DONE; 1123 } 1124 1125 MMC_WRITE(sc, SUNXI_MMC_IMASK, imask); 1126 MMC_WRITE(sc, SUNXI_MMC_RINT, 0xffff); 1127 1128 sc->sc_intr_rint = 0; 1129 1130 MMC_WRITE(sc, SUNXI_MMC_A12A, 1131 (cmdval & SUNXI_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff); 1132 1133 MMC_WRITE(sc, SUNXI_MMC_ARG, cmd->c_arg); 1134 1135 DPRINTF(sc->sc_dev, "cmdval = %08x\n", cmdval); 1136 1137 if (cmd->c_datalen == 0) { 1138 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 1139 } else { 1140 cmd->c_resid = cmd->c_datalen; 1141 cmd->c_error = sunxi_mmc_dma_prepare(sc, cmd); 1142 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 1143 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_CMD_READ)) { 1144 const uint32_t idst_mask = SUNXI_MMC_IDST_RECEIVE_INT; 1145 1146 retry = 10; 1147 while ((sc->sc_idma_idst & idst_mask) == 0) { 1148 if (retry-- == 0) { 1149 cmd->c_error = ETIMEDOUT; 1150 break; 1151 } 1152 cv_timedwait(&sc->sc_idst_cv, 1153 &sc->sc_intr_lock, hz); 1154 } 1155 } 1156 } 1157 1158 cmd->c_error = sunxi_mmc_wait_rint(sc, 1159 SUNXI_MMC_INT_ERROR|SUNXI_MMC_INT_CMD_DONE, hz * 3, poll); 1160 if (cmd->c_error == 0 && (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 1161 if (sc->sc_intr_rint & SUNXI_MMC_INT_RESP_TIMEOUT) { 1162 cmd->c_error = ETIMEDOUT; 1163 } else { 1164 cmd->c_error = EIO; 1165 } 1166 } 1167 if (cmd->c_error) { 1168 DPRINTF(sc->sc_dev, 1169 "cmd failed, error %d\n", cmd->c_error); 1170 goto done; 1171 } 1172 1173 if (cmd->c_datalen > 0) { 1174 sunxi_mmc_dma_complete(sc, cmd); 1175 1176 cmd->c_error = sunxi_mmc_wait_rint(sc, 1177 SUNXI_MMC_INT_ERROR| 1178 SUNXI_MMC_INT_AUTO_CMD_DONE| 1179 SUNXI_MMC_INT_DATA_OVER, 1180 hz*3, poll); 1181 if (cmd->c_error == 0 && 1182 (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 1183 cmd->c_error = ETIMEDOUT; 1184 } 1185 if (cmd->c_error) { 1186 DPRINTF(sc->sc_dev, 1187 "data timeout, rint = %08x\n", 1188 sc->sc_intr_rint); 1189 cmd->c_error = ETIMEDOUT; 1190 goto done; 1191 } 1192 } 1193 1194 if (cmd->c_flags & SCF_RSP_PRESENT) { 1195 if (cmd->c_flags & SCF_RSP_136) { 1196 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 1197 cmd->c_resp[1] = MMC_READ(sc, SUNXI_MMC_RESP1); 1198 cmd->c_resp[2] = MMC_READ(sc, SUNXI_MMC_RESP2); 1199 cmd->c_resp[3] = MMC_READ(sc, SUNXI_MMC_RESP3); 1200 if (cmd->c_flags & SCF_RSP_CRC) { 1201 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1202 (cmd->c_resp[1] << 24); 1203 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1204 (cmd->c_resp[2] << 24); 1205 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1206 (cmd->c_resp[3] << 24); 1207 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1208 } 1209 } else { 1210 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 1211 } 1212 } 1213 1214 done: 1215 cmd->c_flags |= SCF_ITSDONE; 1216 MMC_WRITE(sc, SUNXI_MMC_IMASK, oimask); 1217 MMC_WRITE(sc, SUNXI_MMC_RINT, 0xffff); 1218 MMC_WRITE(sc, SUNXI_MMC_IDST, 0x337); 1219 mutex_exit(&sc->sc_intr_lock); 1220 1221 if (cmd->c_error) { 1222 DPRINTF(sc->sc_dev, "i/o error %d\n", cmd->c_error); 1223 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1224 MMC_READ(sc, SUNXI_MMC_GCTRL) | 1225 SUNXI_MMC_GCTRL_DMARESET | SUNXI_MMC_GCTRL_FIFORESET); 1226 for (retry = 0; retry < 1000; retry++) { 1227 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 1228 break; 1229 delay(10); 1230 } 1231 sunxi_mmc_update_clock(sc); 1232 } 1233 1234 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1235 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_FIFORESET); 1236 } 1237 1238 static void 1239 sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1240 { 1241 struct sunxi_mmc_softc *sc = sch; 1242 uint32_t imask; 1243 1244 imask = MMC_READ(sc, SUNXI_MMC_IMASK); 1245 if (enable) 1246 imask |= SUNXI_MMC_INT_SDIO_INT; 1247 else 1248 imask &= ~SUNXI_MMC_INT_SDIO_INT; 1249 MMC_WRITE(sc, SUNXI_MMC_IMASK, imask); 1250 } 1251 1252 static void 1253 sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 1254 { 1255 struct sunxi_mmc_softc *sc = sch; 1256 1257 MMC_WRITE(sc, SUNXI_MMC_RINT, SUNXI_MMC_INT_SDIO_INT); 1258 } 1259
Indexes created Tue Sep 30 17:09:57 GMT 2025