sunxi_mmc.c revision 1.37
1 /* $NetBSD: sunxi_mmc.c,v 1.37 2019/09/05 17:25:23 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_sunximmc.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.37 2019/09/05 17:25:23 bouyer Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/gpio.h> 41 42 #include <dev/sdmmc/sdmmcvar.h> 43 #include <dev/sdmmc/sdmmcchip.h> 44 #include <dev/sdmmc/sdmmc_ioreg.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #include <arm/sunxi/sunxi_mmc.h> 49 50 #ifdef SUNXI_MMC_DEBUG 51 static int sunxi_mmc_debug = SUNXI_MMC_DEBUG; 52 #define DPRINTF(dev, fmt, ...) \ 53 do { \ 54 if (sunxi_mmc_debug & __BIT(device_unit(dev))) \ 55 device_printf((dev), fmt, ##__VA_ARGS__); \ 56 } while (0) 57 #else 58 #define DPRINTF(dev, fmt, ...) ((void)0) 59 #endif 60 61 enum sunxi_mmc_timing { 62 SUNXI_MMC_TIMING_400K, 63 SUNXI_MMC_TIMING_25M, 64 SUNXI_MMC_TIMING_50M, 65 SUNXI_MMC_TIMING_50M_DDR, 66 SUNXI_MMC_TIMING_50M_DDR_8BIT, 67 }; 68 69 struct sunxi_mmc_delay { 70 u_int output_phase; 71 u_int sample_phase; 72 }; 73 74 static const struct sunxi_mmc_delay sun7i_mmc_delays[] = { 75 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 76 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 77 [SUNXI_MMC_TIMING_50M] = { 90, 120 }, 78 [SUNXI_MMC_TIMING_50M_DDR] = { 60, 120 }, 79 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 90, 180 }, 80 }; 81 82 static const struct sunxi_mmc_delay sun9i_mmc_delays[] = { 83 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 84 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 85 [SUNXI_MMC_TIMING_50M] = { 150, 120 }, 86 [SUNXI_MMC_TIMING_50M_DDR] = { 54, 36 }, 87 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 72, 72 }, 88 }; 89 90 #define SUNXI_MMC_NDESC 64 91 92 struct sunxi_mmc_softc; 93 94 static int sunxi_mmc_match(device_t, cfdata_t, void *); 95 static void sunxi_mmc_attach(device_t, device_t, void *); 96 static void sunxi_mmc_attach_i(device_t); 97 98 static int sunxi_mmc_intr(void *); 99 static int sunxi_mmc_dmabounce_setup(struct sunxi_mmc_softc *); 100 static int sunxi_mmc_idma_setup(struct sunxi_mmc_softc *); 101 102 static int sunxi_mmc_host_reset(sdmmc_chipset_handle_t); 103 static uint32_t sunxi_mmc_host_ocr(sdmmc_chipset_handle_t); 104 static int sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t); 105 static int sunxi_mmc_card_detect(sdmmc_chipset_handle_t); 106 static int sunxi_mmc_write_protect(sdmmc_chipset_handle_t); 107 static int sunxi_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 108 static int sunxi_mmc_bus_clock(sdmmc_chipset_handle_t, int, bool); 109 static int sunxi_mmc_bus_width(sdmmc_chipset_handle_t, int); 110 static int sunxi_mmc_bus_rod(sdmmc_chipset_handle_t, int); 111 static int sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 112 static int sunxi_mmc_execute_tuning(sdmmc_chipset_handle_t, int); 113 static void sunxi_mmc_exec_command(sdmmc_chipset_handle_t, 114 struct sdmmc_command *); 115 static void sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 116 static void sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t); 117 118 static struct sdmmc_chip_functions sunxi_mmc_chip_functions = { 119 .host_reset = sunxi_mmc_host_reset, 120 .host_ocr = sunxi_mmc_host_ocr, 121 .host_maxblklen = sunxi_mmc_host_maxblklen, 122 .card_detect = sunxi_mmc_card_detect, 123 .write_protect = sunxi_mmc_write_protect, 124 .bus_power = sunxi_mmc_bus_power, 125 .bus_clock_ddr = sunxi_mmc_bus_clock, 126 .bus_width = sunxi_mmc_bus_width, 127 .bus_rod = sunxi_mmc_bus_rod, 128 .signal_voltage = sunxi_mmc_signal_voltage, 129 .execute_tuning = sunxi_mmc_execute_tuning, 130 .exec_command = sunxi_mmc_exec_command, 131 .card_enable_intr = sunxi_mmc_card_enable_intr, 132 .card_intr_ack = sunxi_mmc_card_intr_ack, 133 }; 134 135 struct sunxi_mmc_config { 136 u_int idma_xferlen; 137 u_int flags; 138 #define SUNXI_MMC_FLAG_CALIB_REG 0x01 139 #define SUNXI_MMC_FLAG_NEW_TIMINGS 0x02 140 #define SUNXI_MMC_FLAG_MASK_DATA0 0x04 141 #define SUNXI_MMC_FLAG_HS200 0x08 142 const struct sunxi_mmc_delay *delays; 143 uint32_t dma_ftrglevel; 144 }; 145 146 struct sunxi_mmc_softc { 147 device_t sc_dev; 148 bus_space_tag_t sc_bst; 149 bus_space_handle_t sc_bsh; 150 bus_dma_tag_t sc_dmat; 151 int sc_phandle; 152 153 void *sc_ih; 154 kmutex_t sc_intr_lock; 155 kcondvar_t sc_intr_cv; 156 kcondvar_t sc_idst_cv; 157 158 int sc_mmc_width; 159 int sc_mmc_present; 160 161 u_int sc_max_frequency; 162 163 device_t sc_sdmmc_dev; 164 165 struct sunxi_mmc_config *sc_config; 166 167 bus_dma_segment_t sc_idma_segs[1]; 168 int sc_idma_nsegs; 169 bus_size_t sc_idma_size; 170 bus_dmamap_t sc_idma_map; 171 int sc_idma_ndesc; 172 void *sc_idma_desc; 173 174 bus_dmamap_t sc_dmabounce_map; 175 void *sc_dmabounce_buf; 176 size_t sc_dmabounce_buflen; 177 178 uint32_t sc_intr_rint; 179 uint32_t sc_intr_card; 180 uint32_t sc_idma_idst; 181 182 struct clk *sc_clk_ahb; 183 struct clk *sc_clk_mmc; 184 struct clk *sc_clk_output; 185 struct clk *sc_clk_sample; 186 187 struct fdtbus_reset *sc_rst_ahb; 188 189 struct fdtbus_gpio_pin *sc_gpio_cd; 190 int sc_gpio_cd_inverted; 191 struct fdtbus_gpio_pin *sc_gpio_wp; 192 int sc_gpio_wp_inverted; 193 194 struct fdtbus_regulator *sc_reg_vmmc; 195 struct fdtbus_regulator *sc_reg_vqmmc; 196 197 struct fdtbus_mmc_pwrseq *sc_pwrseq; 198 199 bool sc_non_removable; 200 bool sc_broken_cd; 201 }; 202 203 CFATTACH_DECL_NEW(sunxi_mmc, sizeof(struct sunxi_mmc_softc), 204 sunxi_mmc_match, sunxi_mmc_attach, NULL, NULL); 205 206 #define MMC_WRITE(sc, reg, val) \ 207 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 208 #define MMC_READ(sc, reg) \ 209 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 210 211 static const struct sunxi_mmc_config sun4i_a10_mmc_config = { 212 .idma_xferlen = 0x2000, 213 .dma_ftrglevel = 0x20070008, 214 .delays = NULL, 215 .flags = 0, 216 }; 217 218 static const struct sunxi_mmc_config sun5i_a13_mmc_config = { 219 .idma_xferlen = 0x10000, 220 .dma_ftrglevel = 0x20070008, 221 .delays = NULL, 222 .flags = 0, 223 }; 224 225 static const struct sunxi_mmc_config sun7i_a20_mmc_config = { 226 .idma_xferlen = 0x2000, 227 .dma_ftrglevel = 0x20070008, 228 .delays = sun7i_mmc_delays, 229 .flags = 0, 230 }; 231 232 static const struct sunxi_mmc_config sun8i_a83t_emmc_config = { 233 .idma_xferlen = 0x10000, 234 .dma_ftrglevel = 0x20070008, 235 .delays = NULL, 236 .flags = SUNXI_MMC_FLAG_NEW_TIMINGS, 237 }; 238 239 static const struct sunxi_mmc_config sun9i_a80_mmc_config = { 240 .idma_xferlen = 0x10000, 241 .dma_ftrglevel = 0x200f0010, 242 .delays = sun9i_mmc_delays, 243 .flags = 0, 244 }; 245 246 static const struct sunxi_mmc_config sun50i_a64_mmc_config = { 247 .idma_xferlen = 0x10000, 248 .dma_ftrglevel = 0x20070008, 249 .delays = NULL, 250 .flags = SUNXI_MMC_FLAG_CALIB_REG | 251 SUNXI_MMC_FLAG_NEW_TIMINGS | 252 SUNXI_MMC_FLAG_MASK_DATA0, 253 }; 254 255 static const struct sunxi_mmc_config sun50i_a64_emmc_config = { 256 .idma_xferlen = 0x2000, 257 .dma_ftrglevel = 0x20070008, 258 .delays = NULL, 259 .flags = SUNXI_MMC_FLAG_CALIB_REG | 260 SUNXI_MMC_FLAG_NEW_TIMINGS | 261 SUNXI_MMC_FLAG_HS200, 262 }; 263 264 static const struct sunxi_mmc_config sun50i_h6_mmc_config = { 265 .idma_xferlen = 0x10000, 266 .dma_ftrglevel = 0x20070008, 267 .delays = NULL, 268 .flags = SUNXI_MMC_FLAG_CALIB_REG | 269 SUNXI_MMC_FLAG_NEW_TIMINGS | 270 SUNXI_MMC_FLAG_MASK_DATA0, 271 }; 272 273 static const struct sunxi_mmc_config sun50i_h6_emmc_config = { 274 .idma_xferlen = 0x2000, 275 .dma_ftrglevel = 0x20070008, 276 .delays = NULL, 277 .flags = SUNXI_MMC_FLAG_CALIB_REG, 278 }; 279 280 static const struct of_compat_data compat_data[] = { 281 { "allwinner,sun4i-a10-mmc", (uintptr_t)&sun4i_a10_mmc_config }, 282 { "allwinner,sun5i-a13-mmc", (uintptr_t)&sun5i_a13_mmc_config }, 283 { "allwinner,sun7i-a20-mmc", (uintptr_t)&sun7i_a20_mmc_config }, 284 { "allwinner,sun8i-a83t-emmc", (uintptr_t)&sun8i_a83t_emmc_config }, 285 { "allwinner,sun9i-a80-mmc", (uintptr_t)&sun9i_a80_mmc_config }, 286 { "allwinner,sun50i-a64-mmc", (uintptr_t)&sun50i_a64_mmc_config }, 287 { "allwinner,sun50i-a64-emmc", (uintptr_t)&sun50i_a64_emmc_config }, 288 { "allwinner,sun50i-h6-mmc", (uintptr_t)&sun50i_h6_mmc_config }, 289 { "allwinner,sun50i-h6-emmc", (uintptr_t)&sun50i_h6_emmc_config }, 290 { NULL } 291 }; 292 293 static int 294 sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux) 295 { 296 struct fdt_attach_args * const faa = aux; 297 298 return of_match_compat_data(faa->faa_phandle, compat_data); 299 } 300 301 static void 302 sunxi_mmc_attach(device_t parent, device_t self, void *aux) 303 { 304 struct sunxi_mmc_softc * const sc = device_private(self); 305 struct fdt_attach_args * const faa = aux; 306 const int phandle = faa->faa_phandle; 307 char intrstr[128]; 308 bus_addr_t addr; 309 bus_size_t size; 310 311 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 312 aprint_error(": couldn't get registers\n"); 313 return; 314 } 315 316 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 317 sc->sc_clk_mmc = fdtbus_clock_get(phandle, "mmc"); 318 sc->sc_clk_output = fdtbus_clock_get(phandle, "output"); 319 sc->sc_clk_sample = fdtbus_clock_get(phandle, "sample"); 320 321 #if notyet 322 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL || 323 sc->sc_clk_output == NULL || sc->sc_clk_sample == NULL) { 324 #else 325 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL) { 326 #endif 327 aprint_error(": couldn't get clocks\n"); 328 return; 329 } 330 331 sc->sc_rst_ahb = fdtbus_reset_get(phandle, "ahb"); 332 333 sc->sc_pwrseq = fdtbus_mmc_pwrseq_get(phandle); 334 335 if (clk_enable(sc->sc_clk_ahb) != 0 || 336 clk_enable(sc->sc_clk_mmc) != 0) { 337 aprint_error(": couldn't enable clocks\n"); 338 return; 339 } 340 341 if (sc->sc_rst_ahb != NULL) { 342 if (fdtbus_reset_deassert(sc->sc_rst_ahb) != 0) { 343 aprint_error(": couldn't de-assert resets\n"); 344 return; 345 } 346 } 347 348 sc->sc_dev = self; 349 sc->sc_phandle = phandle; 350 sc->sc_config = (void *)of_search_compatible(phandle, compat_data)->data; 351 sc->sc_bst = faa->faa_bst; 352 sc->sc_dmat = faa->faa_dmat; 353 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 354 cv_init(&sc->sc_intr_cv, "awinmmcirq"); 355 cv_init(&sc->sc_idst_cv, "awinmmcdma"); 356 357 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 358 aprint_error(": couldn't map registers\n"); 359 return; 360 } 361 362 sc->sc_reg_vmmc = fdtbus_regulator_acquire(phandle, "vmmc-supply"); 363 if (sc->sc_reg_vmmc != NULL && fdtbus_regulator_enable(sc->sc_reg_vmmc)) { 364 aprint_error(": couldn't enable vmmc-supply\n"); 365 return; 366 } 367 368 aprint_naive("\n"); 369 aprint_normal(": SD/MMC controller\n"); 370 371 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(phandle, "vqmmc-supply"); 372 373 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 374 GPIO_PIN_INPUT); 375 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 376 GPIO_PIN_INPUT); 377 378 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 0 : 1; 379 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 0 : 1; 380 381 sc->sc_non_removable = of_hasprop(phandle, "non-removable"); 382 sc->sc_broken_cd = of_hasprop(phandle, "broken-cd"); 383 384 if (of_getprop_uint32(phandle, "max-frequency", &sc->sc_max_frequency)) 385 sc->sc_max_frequency = 52000000; 386 387 if (sunxi_mmc_dmabounce_setup(sc) != 0 || 388 sunxi_mmc_idma_setup(sc) != 0) { 389 aprint_error_dev(self, "failed to setup DMA\n"); 390 return; 391 } 392 393 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 394 aprint_error_dev(self, "failed to decode interrupt\n"); 395 return; 396 } 397 398 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, FDT_INTR_MPSAFE, 399 sunxi_mmc_intr, sc); 400 if (sc->sc_ih == NULL) { 401 aprint_error_dev(self, "failed to establish interrupt on %s\n", 402 intrstr); 403 return; 404 } 405 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 406 407 config_interrupts(self, sunxi_mmc_attach_i); 408 } 409 410 static int 411 sunxi_mmc_dmabounce_setup(struct sunxi_mmc_softc *sc) 412 { 413 bus_dma_segment_t ds[1]; 414 int error, rseg; 415 416 sc->sc_dmabounce_buflen = sunxi_mmc_host_maxblklen(sc); 417 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_dmabounce_buflen, 0, 418 sc->sc_dmabounce_buflen, ds, 1, &rseg, BUS_DMA_WAITOK); 419 if (error) 420 return error; 421 error = bus_dmamem_map(sc->sc_dmat, ds, 1, sc->sc_dmabounce_buflen, 422 &sc->sc_dmabounce_buf, BUS_DMA_WAITOK); 423 if (error) 424 goto free; 425 error = bus_dmamap_create(sc->sc_dmat, sc->sc_dmabounce_buflen, 1, 426 sc->sc_dmabounce_buflen, 0, BUS_DMA_WAITOK, &sc->sc_dmabounce_map); 427 if (error) 428 goto unmap; 429 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmabounce_map, 430 sc->sc_dmabounce_buf, sc->sc_dmabounce_buflen, NULL, 431 BUS_DMA_WAITOK); 432 if (error) 433 goto destroy; 434 return 0; 435 436 destroy: 437 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmabounce_map); 438 unmap: 439 bus_dmamem_unmap(sc->sc_dmat, sc->sc_dmabounce_buf, 440 sc->sc_dmabounce_buflen); 441 free: 442 bus_dmamem_free(sc->sc_dmat, ds, rseg); 443 return error; 444 } 445 446 static int 447 sunxi_mmc_idma_setup(struct sunxi_mmc_softc *sc) 448 { 449 int error; 450 451 sc->sc_idma_ndesc = SUNXI_MMC_NDESC; 452 sc->sc_idma_size = sizeof(struct sunxi_mmc_idma_descriptor) * 453 sc->sc_idma_ndesc; 454 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 0, 455 sc->sc_idma_size, sc->sc_idma_segs, 1, 456 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 457 if (error) 458 return error; 459 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 460 sc->sc_idma_nsegs, sc->sc_idma_size, 461 &sc->sc_idma_desc, BUS_DMA_WAITOK); 462 if (error) 463 goto free; 464 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 465 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 466 if (error) 467 goto unmap; 468 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 469 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 470 if (error) 471 goto destroy; 472 return 0; 473 474 destroy: 475 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 476 unmap: 477 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 478 free: 479 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 480 return error; 481 } 482 483 static int 484 sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr, bool dbl) 485 { 486 const struct sunxi_mmc_delay *delays; 487 int error, timing = SUNXI_MMC_TIMING_400K; 488 489 if (sc->sc_config->delays) { 490 if (freq <= 400) { 491 timing = SUNXI_MMC_TIMING_400K; 492 } else if (freq <= 25000) { 493 timing = SUNXI_MMC_TIMING_25M; 494 } else if (freq <= 52000) { 495 if (ddr) { 496 timing = sc->sc_mmc_width == 8 ? 497 SUNXI_MMC_TIMING_50M_DDR_8BIT : 498 SUNXI_MMC_TIMING_50M_DDR; 499 } else { 500 timing = SUNXI_MMC_TIMING_50M; 501 } 502 } else 503 return EINVAL; 504 } 505 if (sc->sc_max_frequency) { 506 if (freq * 1000 > sc->sc_max_frequency) 507 return EINVAL; 508 } 509 510 error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << dbl); 511 if (error != 0) 512 return error; 513 514 if (sc->sc_config->delays == NULL) 515 return 0; 516 517 delays = &sc->sc_config->delays[timing]; 518 519 if (sc->sc_clk_sample) { 520 error = clk_set_rate(sc->sc_clk_sample, delays->sample_phase); 521 if (error != 0) 522 return error; 523 } 524 if (sc->sc_clk_output) { 525 error = clk_set_rate(sc->sc_clk_output, delays->output_phase); 526 if (error != 0) 527 return error; 528 } 529 530 return 0; 531 } 532 533 static void 534 sunxi_mmc_hw_reset(struct sunxi_mmc_softc *sc) 535 { 536 MMC_WRITE(sc, SUNXI_MMC_HWRST, 0); 537 delay(1000); 538 MMC_WRITE(sc, SUNXI_MMC_HWRST, 1); 539 delay(1000); 540 } 541 542 static void 543 sunxi_mmc_attach_i(device_t self) 544 { 545 struct sunxi_mmc_softc *sc = device_private(self); 546 const u_int flags = sc->sc_config->flags; 547 struct sdmmcbus_attach_args saa; 548 uint32_t width; 549 550 if (sc->sc_pwrseq) 551 fdtbus_mmc_pwrseq_pre_power_on(sc->sc_pwrseq); 552 553 if (of_hasprop(sc->sc_phandle, "cap-mmc-hw-reset")) 554 sunxi_mmc_hw_reset(sc); 555 556 sunxi_mmc_host_reset(sc); 557 sunxi_mmc_bus_width(sc, 1); 558 sunxi_mmc_set_clock(sc, 400, false, false); 559 560 if (sc->sc_pwrseq) 561 fdtbus_mmc_pwrseq_post_power_on(sc->sc_pwrseq); 562 563 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 564 width = 4; 565 566 memset(&saa, 0, sizeof(saa)); 567 saa.saa_busname = "sdmmc"; 568 saa.saa_sct = &sunxi_mmc_chip_functions; 569 saa.saa_sch = sc; 570 saa.saa_dmat = sc->sc_dmat; 571 saa.saa_clkmin = 400; 572 saa.saa_clkmax = sc->sc_max_frequency / 1000; 573 saa.saa_caps = SMC_CAPS_DMA | 574 SMC_CAPS_MULTI_SEG_DMA | 575 SMC_CAPS_AUTO_STOP | 576 SMC_CAPS_SD_HIGHSPEED | 577 SMC_CAPS_MMC_HIGHSPEED | 578 SMC_CAPS_POLLING; 579 580 if (sc->sc_config->delays || (flags & SUNXI_MMC_FLAG_NEW_TIMINGS)) 581 saa.saa_caps |= SMC_CAPS_MMC_DDR52; 582 583 if (flags & SUNXI_MMC_FLAG_HS200) 584 saa.saa_caps |= SMC_CAPS_MMC_HS200; 585 586 if (width == 4) 587 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 588 if (width == 8) 589 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 590 591 if (sc->sc_gpio_cd) 592 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 593 594 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 595 } 596 597 static int 598 sunxi_mmc_intr(void *priv) 599 { 600 struct sunxi_mmc_softc *sc = priv; 601 uint32_t idst, rint, imask; 602 603 mutex_enter(&sc->sc_intr_lock); 604 idst = MMC_READ(sc, SUNXI_MMC_IDST); 605 rint = MMC_READ(sc, SUNXI_MMC_RINT); 606 if (!idst && !rint) { 607 mutex_exit(&sc->sc_intr_lock); 608 return 0; 609 } 610 MMC_WRITE(sc, SUNXI_MMC_IDST, idst); 611 MMC_WRITE(sc, SUNXI_MMC_RINT, rint); 612 613 DPRINTF(sc->sc_dev, "mmc intr idst=%08X rint=%08X\n", 614 idst, rint); 615 616 if (idst != 0) { 617 MMC_WRITE(sc, SUNXI_MMC_IDIE, 0); 618 sc->sc_idma_idst |= idst; 619 cv_broadcast(&sc->sc_idst_cv); 620 } 621 622 if ((rint & ~SUNXI_MMC_INT_SDIO_INT) != 0) { 623 imask = MMC_READ(sc, SUNXI_MMC_IMASK); 624 MMC_WRITE(sc, SUNXI_MMC_IMASK, imask & SUNXI_MMC_INT_SDIO_INT); 625 sc->sc_intr_rint |= (rint & ~SUNXI_MMC_INT_SDIO_INT); 626 cv_broadcast(&sc->sc_intr_cv); 627 } 628 629 if ((rint & SUNXI_MMC_INT_SDIO_INT) != 0) { 630 imask = MMC_READ(sc, SUNXI_MMC_IMASK); 631 MMC_WRITE(sc, SUNXI_MMC_IMASK, imask & ~SUNXI_MMC_INT_SDIO_INT); 632 sdmmc_card_intr(sc->sc_sdmmc_dev); 633 } 634 635 mutex_exit(&sc->sc_intr_lock); 636 637 return 1; 638 } 639 640 static int 641 sunxi_mmc_wait_rint(struct sunxi_mmc_softc *sc, uint32_t mask, 642 int secs, bool poll) 643 { 644 int retry; 645 int error; 646 647 KASSERT(mutex_owned(&sc->sc_intr_lock)); 648 649 if (sc->sc_intr_rint & mask) 650 return 0; 651 652 if (poll) { 653 retry = secs * 1000; 654 while (retry > 0) { 655 sc->sc_intr_rint |= MMC_READ(sc, SUNXI_MMC_RINT); 656 if (sc->sc_intr_rint & mask) 657 return 0; 658 delay(1000); 659 --retry; 660 } 661 return ETIMEDOUT; 662 } else { 663 struct bintime timeout = { .sec = secs, .frac = 0 }; 664 const struct bintime epsilon = { .sec = 1, .frac = 0 }; 665 while ((sc->sc_intr_rint & mask) == 0) { 666 error = cv_timedwaitbt(&sc->sc_intr_cv, 667 &sc->sc_intr_lock, &timeout, &epsilon); 668 if (error != 0) 669 return error; 670 } 671 return 0; 672 } 673 } 674 675 static int 676 sunxi_mmc_host_reset(sdmmc_chipset_handle_t sch) 677 { 678 struct sunxi_mmc_softc *sc = sch; 679 uint32_t gctrl; 680 int retry = 1000; 681 682 DPRINTF(sc->sc_dev, "host reset\n"); 683 684 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 685 gctrl |= SUNXI_MMC_GCTRL_RESET; 686 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 687 while (--retry > 0) { 688 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 689 break; 690 delay(100); 691 } 692 693 MMC_WRITE(sc, SUNXI_MMC_TIMEOUT, 0xffffffff); 694 695 MMC_WRITE(sc, SUNXI_MMC_IMASK, 0); 696 697 MMC_WRITE(sc, SUNXI_MMC_RINT, 0xffffffff); 698 699 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 700 gctrl |= SUNXI_MMC_GCTRL_INTEN; 701 gctrl &= ~SUNXI_MMC_GCTRL_WAIT_MEM_ACCESS_DONE; 702 gctrl &= ~SUNXI_MMC_GCTRL_ACCESS_BY_AHB; 703 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 704 705 return 0; 706 } 707 708 static uint32_t 709 sunxi_mmc_host_ocr(sdmmc_chipset_handle_t sch) 710 { 711 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 712 } 713 714 static int 715 sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 716 { 717 return 8192; 718 } 719 720 static int 721 sunxi_mmc_card_detect(sdmmc_chipset_handle_t sch) 722 { 723 struct sunxi_mmc_softc *sc = sch; 724 725 if (sc->sc_non_removable || sc->sc_broken_cd) { 726 /* 727 * Non-removable or broken card detect flag set in 728 * DT, assume always present 729 */ 730 return 1; 731 } else if (sc->sc_gpio_cd != NULL) { 732 /* Use card detect GPIO */ 733 int v = 0, i; 734 for (i = 0; i < 5; i++) { 735 v += (fdtbus_gpio_read(sc->sc_gpio_cd) ^ 736 sc->sc_gpio_cd_inverted); 737 delay(1000); 738 } 739 if (v == 5) 740 sc->sc_mmc_present = 0; 741 else if (v == 0) 742 sc->sc_mmc_present = 1; 743 return sc->sc_mmc_present; 744 } else { 745 /* Use CARD_PRESENT field of SD_STATUS register */ 746 const uint32_t present = MMC_READ(sc, SUNXI_MMC_STATUS) & 747 SUNXI_MMC_STATUS_CARD_PRESENT; 748 return present != 0; 749 } 750 } 751 752 static int 753 sunxi_mmc_write_protect(sdmmc_chipset_handle_t sch) 754 { 755 struct sunxi_mmc_softc *sc = sch; 756 757 if (sc->sc_gpio_wp == NULL) { 758 return 0; /* no write protect pin, assume rw */ 759 } else { 760 return fdtbus_gpio_read(sc->sc_gpio_wp) ^ 761 sc->sc_gpio_wp_inverted; 762 } 763 } 764 765 static int 766 sunxi_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 767 { 768 return 0; 769 } 770 771 static int 772 sunxi_mmc_update_clock(struct sunxi_mmc_softc *sc) 773 { 774 uint32_t cmd; 775 int retry; 776 777 DPRINTF(sc->sc_dev, "update clock\n"); 778 779 cmd = SUNXI_MMC_CMD_START | 780 SUNXI_MMC_CMD_UPCLK_ONLY | 781 SUNXI_MMC_CMD_WAIT_PRE_OVER; 782 MMC_WRITE(sc, SUNXI_MMC_CMD, cmd); 783 retry = 100000; 784 while (--retry > 0) { 785 if (!(MMC_READ(sc, SUNXI_MMC_CMD) & SUNXI_MMC_CMD_START)) 786 break; 787 delay(10); 788 } 789 790 if (retry == 0) { 791 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 792 DPRINTF(sc->sc_dev, "GCTRL: 0x%08x\n", 793 MMC_READ(sc, SUNXI_MMC_GCTRL)); 794 DPRINTF(sc->sc_dev, "CLKCR: 0x%08x\n", 795 MMC_READ(sc, SUNXI_MMC_CLKCR)); 796 DPRINTF(sc->sc_dev, "TIMEOUT: 0x%08x\n", 797 MMC_READ(sc, SUNXI_MMC_TIMEOUT)); 798 DPRINTF(sc->sc_dev, "WIDTH: 0x%08x\n", 799 MMC_READ(sc, SUNXI_MMC_WIDTH)); 800 DPRINTF(sc->sc_dev, "CMD: 0x%08x\n", 801 MMC_READ(sc, SUNXI_MMC_CMD)); 802 DPRINTF(sc->sc_dev, "MINT: 0x%08x\n", 803 MMC_READ(sc, SUNXI_MMC_MINT)); 804 DPRINTF(sc->sc_dev, "RINT: 0x%08x\n", 805 MMC_READ(sc, SUNXI_MMC_RINT)); 806 DPRINTF(sc->sc_dev, "STATUS: 0x%08x\n", 807 MMC_READ(sc, SUNXI_MMC_STATUS)); 808 return ETIMEDOUT; 809 } 810 811 return 0; 812 } 813 814 static int 815 sunxi_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 816 { 817 struct sunxi_mmc_softc *sc = sch; 818 uint32_t clkcr, gctrl, ntsr; 819 const u_int flags = sc->sc_config->flags; 820 bool dbl = 0; 821 822 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 823 if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) { 824 clkcr &= ~SUNXI_MMC_CLKCR_CARDCLKON; 825 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 826 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 827 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 828 if (sunxi_mmc_update_clock(sc) != 0) 829 return 1; 830 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 831 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 832 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 833 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 834 } 835 } 836 837 if (freq) { 838 /* For 8bits ddr in old timing modes, and all ddr in new 839 * timing modes, the module clock has to be 2x the card clock. 840 */ 841 if (ddr && ((flags & SUNXI_MMC_FLAG_NEW_TIMINGS) || 842 sc->sc_mmc_width == 8)) 843 dbl = 1; 844 845 clkcr &= ~SUNXI_MMC_CLKCR_DIV; 846 clkcr |= __SHIFTIN(dbl, SUNXI_MMC_CLKCR_DIV); 847 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 848 849 if (flags & SUNXI_MMC_FLAG_NEW_TIMINGS) { 850 ntsr = MMC_READ(sc, SUNXI_MMC_NTSR); 851 ntsr |= SUNXI_MMC_NTSR_MODE_SELECT; 852 MMC_WRITE(sc, SUNXI_MMC_NTSR, ntsr); 853 } 854 855 if (flags & SUNXI_MMC_FLAG_CALIB_REG) 856 MMC_WRITE(sc, SUNXI_MMC_SAMP_DL, SUNXI_MMC_SAMP_DL_SW_EN); 857 858 if (sunxi_mmc_update_clock(sc) != 0) 859 return 1; 860 861 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 862 if (ddr) 863 gctrl |= SUNXI_MMC_GCTRL_DDR_MODE; 864 else 865 gctrl &= ~SUNXI_MMC_GCTRL_DDR_MODE; 866 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 867 868 if (sunxi_mmc_set_clock(sc, freq, ddr, dbl) != 0) 869 return 1; 870 871 clkcr |= SUNXI_MMC_CLKCR_CARDCLKON; 872 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 873 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 874 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 875 if (sunxi_mmc_update_clock(sc) != 0) 876 return 1; 877 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 878 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 879 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 880 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 881 } 882 } 883 884 return 0; 885 } 886 887 static int 888 sunxi_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 889 { 890 struct sunxi_mmc_softc *sc = sch; 891 892 DPRINTF(sc->sc_dev, "width = %d\n", width); 893 894 switch (width) { 895 case 1: 896 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_1); 897 break; 898 case 4: 899 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_4); 900 break; 901 case 8: 902 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_8); 903 break; 904 default: 905 return 1; 906 } 907 908 sc->sc_mmc_width = width; 909 910 return 0; 911 } 912 913 static int 914 sunxi_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 915 { 916 return -1; 917 } 918 919 static int 920 sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 921 { 922 struct sunxi_mmc_softc *sc = sch; 923 u_int uvol; 924 int error; 925 926 if (sc->sc_reg_vqmmc == NULL) 927 return 0; 928 929 switch (signal_voltage) { 930 case SDMMC_SIGNAL_VOLTAGE_330: 931 uvol = 3300000; 932 break; 933 case SDMMC_SIGNAL_VOLTAGE_180: 934 uvol = 1800000; 935 break; 936 default: 937 return EINVAL; 938 } 939 940 error = fdtbus_regulator_supports_voltage(sc->sc_reg_vqmmc, uvol, uvol); 941 if (error != 0) 942 return 0; 943 944 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 945 if (error != 0) 946 return error; 947 948 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 949 } 950 951 static int 952 sunxi_mmc_execute_tuning(sdmmc_chipset_handle_t sch, int timing) 953 { 954 switch (timing) { 955 case SDMMC_TIMING_MMC_HS200: 956 break; 957 default: 958 return EINVAL; 959 } 960 961 return 0; 962 } 963 964 static int 965 sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 966 { 967 struct sunxi_mmc_idma_descriptor *dma = sc->sc_idma_desc; 968 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 969 bus_dmamap_t map; 970 bus_size_t off; 971 int desc, resid, seg; 972 uint32_t val; 973 974 /* 975 * If the command includes a dma map use it, otherwise we need to 976 * bounce. This can happen for SDIO IO_RW_EXTENDED (CMD53) commands. 977 */ 978 if (cmd->c_dmamap) { 979 map = cmd->c_dmamap; 980 } else { 981 if (cmd->c_datalen > sc->sc_dmabounce_buflen) 982 return E2BIG; 983 map = sc->sc_dmabounce_map; 984 985 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 986 memset(sc->sc_dmabounce_buf, 0, cmd->c_datalen); 987 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 988 0, cmd->c_datalen, BUS_DMASYNC_PREREAD); 989 } else { 990 memcpy(sc->sc_dmabounce_buf, cmd->c_data, 991 cmd->c_datalen); 992 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 993 0, cmd->c_datalen, BUS_DMASYNC_PREWRITE); 994 } 995 } 996 997 desc = 0; 998 for (seg = 0; seg < map->dm_nsegs; seg++) { 999 bus_addr_t paddr = map->dm_segs[seg].ds_addr; 1000 bus_size_t len = map->dm_segs[seg].ds_len; 1001 resid = uimin(len, cmd->c_resid); 1002 off = 0; 1003 while (resid > 0) { 1004 if (desc == sc->sc_idma_ndesc) 1005 break; 1006 len = uimin(sc->sc_config->idma_xferlen, resid); 1007 dma[desc].dma_buf_size = htole32(len); 1008 dma[desc].dma_buf_addr = htole32(paddr + off); 1009 dma[desc].dma_config = htole32(SUNXI_MMC_IDMA_CONFIG_CH | 1010 SUNXI_MMC_IDMA_CONFIG_OWN); 1011 cmd->c_resid -= len; 1012 resid -= len; 1013 off += len; 1014 if (desc == 0) { 1015 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_FD); 1016 } 1017 if (cmd->c_resid == 0) { 1018 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_LD); 1019 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_ER); 1020 dma[desc].dma_next = 0; 1021 } else { 1022 dma[desc].dma_config |= 1023 htole32(SUNXI_MMC_IDMA_CONFIG_DIC); 1024 dma[desc].dma_next = htole32( 1025 desc_paddr + ((desc+1) * 1026 sizeof(struct sunxi_mmc_idma_descriptor))); 1027 } 1028 ++desc; 1029 } 1030 } 1031 if (desc == sc->sc_idma_ndesc) { 1032 aprint_error_dev(sc->sc_dev, 1033 "not enough descriptors for %d byte transfer! " 1034 "there are %u segments with a max xfer length of %u\n", 1035 cmd->c_datalen, map->dm_nsegs, sc->sc_config->idma_xferlen); 1036 return EIO; 1037 } 1038 1039 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 1040 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 1041 1042 sc->sc_idma_idst = 0; 1043 1044 MMC_WRITE(sc, SUNXI_MMC_DLBA, desc_paddr); 1045 MMC_WRITE(sc, SUNXI_MMC_FTRGLEVEL, sc->sc_config->dma_ftrglevel); 1046 1047 val = MMC_READ(sc, SUNXI_MMC_GCTRL); 1048 val |= SUNXI_MMC_GCTRL_DMAEN; 1049 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 1050 val |= SUNXI_MMC_GCTRL_DMARESET; 1051 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 1052 1053 MMC_WRITE(sc, SUNXI_MMC_DMAC, SUNXI_MMC_DMAC_SOFTRESET); 1054 if (ISSET(cmd->c_flags, SCF_CMD_READ)) 1055 val = SUNXI_MMC_IDST_RECEIVE_INT; 1056 else 1057 val = 0; 1058 MMC_WRITE(sc, SUNXI_MMC_IDIE, val); 1059 MMC_WRITE(sc, SUNXI_MMC_DMAC, 1060 SUNXI_MMC_DMAC_IDMA_ON|SUNXI_MMC_DMAC_FIX_BURST); 1061 1062 return 0; 1063 } 1064 1065 static void 1066 sunxi_mmc_dma_complete(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 1067 { 1068 MMC_WRITE(sc, SUNXI_MMC_DMAC, 0); 1069 1070 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 1071 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 1072 1073 if (cmd->c_dmamap == NULL) { 1074 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 1075 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 1076 0, cmd->c_datalen, BUS_DMASYNC_POSTREAD); 1077 memcpy(cmd->c_data, sc->sc_dmabounce_buf, 1078 cmd->c_datalen); 1079 } else { 1080 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmabounce_map, 1081 0, cmd->c_datalen, BUS_DMASYNC_POSTWRITE); 1082 } 1083 } 1084 } 1085 1086 static void 1087 sunxi_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1088 { 1089 struct sunxi_mmc_softc *sc = sch; 1090 uint32_t cmdval = SUNXI_MMC_CMD_START; 1091 uint32_t imask, oimask; 1092 const bool poll = (cmd->c_flags & SCF_POLL) != 0; 1093 int retry; 1094 1095 DPRINTF(sc->sc_dev, 1096 "opcode %d flags 0x%x data %p datalen %d blklen %d poll %d\n", 1097 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 1098 cmd->c_blklen, poll); 1099 1100 mutex_enter(&sc->sc_intr_lock); 1101 1102 if (cmd->c_opcode == 0) 1103 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 1104 if (cmd->c_flags & SCF_RSP_PRESENT) 1105 cmdval |= SUNXI_MMC_CMD_RSP_EXP; 1106 if (cmd->c_flags & SCF_RSP_136) 1107 cmdval |= SUNXI_MMC_CMD_LONG_RSP; 1108 if (cmd->c_flags & SCF_RSP_CRC) 1109 cmdval |= SUNXI_MMC_CMD_CHECK_RSP_CRC; 1110 1111 imask = oimask = MMC_READ(sc, SUNXI_MMC_IMASK); 1112 imask |= SUNXI_MMC_INT_ERROR; 1113 1114 if (cmd->c_datalen > 0) { 1115 unsigned int nblks; 1116 1117 cmdval |= SUNXI_MMC_CMD_DATA_EXP | SUNXI_MMC_CMD_WAIT_PRE_OVER; 1118 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 1119 cmdval |= SUNXI_MMC_CMD_WRITE; 1120 } 1121 1122 nblks = cmd->c_datalen / cmd->c_blklen; 1123 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 1124 ++nblks; 1125 1126 if (nblks > 1) { 1127 cmdval |= SUNXI_MMC_CMD_SEND_AUTO_STOP; 1128 imask |= SUNXI_MMC_INT_AUTO_CMD_DONE; 1129 } else { 1130 imask |= SUNXI_MMC_INT_DATA_OVER; 1131 } 1132 1133 MMC_WRITE(sc, SUNXI_MMC_BLKSZ, cmd->c_blklen); 1134 MMC_WRITE(sc, SUNXI_MMC_BYTECNT, nblks * cmd->c_blklen); 1135 } else { 1136 imask |= SUNXI_MMC_INT_CMD_DONE; 1137 } 1138 1139 MMC_WRITE(sc, SUNXI_MMC_IMASK, imask); 1140 MMC_WRITE(sc, SUNXI_MMC_RINT, 0xffff); 1141 1142 sc->sc_intr_rint = 0; 1143 1144 MMC_WRITE(sc, SUNXI_MMC_A12A, 1145 (cmdval & SUNXI_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff); 1146 1147 MMC_WRITE(sc, SUNXI_MMC_ARG, cmd->c_arg); 1148 1149 DPRINTF(sc->sc_dev, "cmdval = %08x\n", cmdval); 1150 1151 if (cmd->c_datalen == 0) { 1152 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 1153 } else { 1154 cmd->c_resid = cmd->c_datalen; 1155 cmd->c_error = sunxi_mmc_dma_prepare(sc, cmd); 1156 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 1157 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_CMD_READ)) { 1158 const uint32_t idst_mask = SUNXI_MMC_IDST_RECEIVE_INT; 1159 1160 retry = 10; 1161 while ((sc->sc_idma_idst & idst_mask) == 0) { 1162 if (retry-- == 0) { 1163 cmd->c_error = ETIMEDOUT; 1164 break; 1165 } 1166 cv_timedwait(&sc->sc_idst_cv, 1167 &sc->sc_intr_lock, hz); 1168 } 1169 } 1170 } 1171 1172 cmd->c_error = sunxi_mmc_wait_rint(sc, 1173 SUNXI_MMC_INT_ERROR|SUNXI_MMC_INT_CMD_DONE, 5, poll); 1174 if (cmd->c_error == 0 && (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 1175 if (sc->sc_intr_rint & SUNXI_MMC_INT_RESP_TIMEOUT) { 1176 cmd->c_error = ETIMEDOUT; 1177 } else { 1178 cmd->c_error = EIO; 1179 } 1180 } 1181 if (cmd->c_error) { 1182 DPRINTF(sc->sc_dev, 1183 "cmd failed, error %d\n", cmd->c_error); 1184 goto done; 1185 } 1186 1187 if (cmd->c_datalen > 0) { 1188 sunxi_mmc_dma_complete(sc, cmd); 1189 1190 cmd->c_error = sunxi_mmc_wait_rint(sc, 1191 SUNXI_MMC_INT_ERROR| 1192 SUNXI_MMC_INT_AUTO_CMD_DONE| 1193 SUNXI_MMC_INT_DATA_OVER, 1194 5, poll); 1195 if (cmd->c_error == 0 && 1196 (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 1197 cmd->c_error = ETIMEDOUT; 1198 } 1199 if (cmd->c_error) { 1200 DPRINTF(sc->sc_dev, 1201 "data timeout, rint = %08x\n", 1202 sc->sc_intr_rint); 1203 cmd->c_error = ETIMEDOUT; 1204 goto done; 1205 } 1206 } 1207 1208 if (cmd->c_flags & SCF_RSP_PRESENT) { 1209 if (cmd->c_flags & SCF_RSP_136) { 1210 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 1211 cmd->c_resp[1] = MMC_READ(sc, SUNXI_MMC_RESP1); 1212 cmd->c_resp[2] = MMC_READ(sc, SUNXI_MMC_RESP2); 1213 cmd->c_resp[3] = MMC_READ(sc, SUNXI_MMC_RESP3); 1214 if (cmd->c_flags & SCF_RSP_CRC) { 1215 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 1216 (cmd->c_resp[1] << 24); 1217 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 1218 (cmd->c_resp[2] << 24); 1219 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 1220 (cmd->c_resp[3] << 24); 1221 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 1222 } 1223 } else { 1224 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 1225 } 1226 } 1227 1228 done: 1229 cmd->c_flags |= SCF_ITSDONE; 1230 MMC_WRITE(sc, SUNXI_MMC_IMASK, 1231 (oimask & ~SUNXI_MMC_INT_SDIO_INT) | sc->sc_intr_card); 1232 MMC_WRITE(sc, SUNXI_MMC_RINT, 0xffff); 1233 MMC_WRITE(sc, SUNXI_MMC_IDST, 0x337); 1234 mutex_exit(&sc->sc_intr_lock); 1235 1236 if (cmd->c_error) { 1237 DPRINTF(sc->sc_dev, "i/o error %d\n", cmd->c_error); 1238 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1239 MMC_READ(sc, SUNXI_MMC_GCTRL) | 1240 SUNXI_MMC_GCTRL_DMARESET | SUNXI_MMC_GCTRL_FIFORESET); 1241 for (retry = 0; retry < 1000; retry++) { 1242 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 1243 break; 1244 delay(10); 1245 } 1246 sunxi_mmc_update_clock(sc); 1247 } 1248 1249 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1250 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_FIFORESET); 1251 } 1252 1253 static void 1254 sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1255 { 1256 struct sunxi_mmc_softc *sc = sch; 1257 uint32_t imask; 1258 1259 mutex_enter(&sc->sc_intr_lock); 1260 imask = MMC_READ(sc, SUNXI_MMC_IMASK); 1261 if (enable) 1262 imask |= SUNXI_MMC_INT_SDIO_INT; 1263 else 1264 imask &= ~SUNXI_MMC_INT_SDIO_INT; 1265 sc->sc_intr_card = imask & SUNXI_MMC_INT_SDIO_INT; 1266 MMC_WRITE(sc, SUNXI_MMC_IMASK, imask); 1267 mutex_exit(&sc->sc_intr_lock); 1268 } 1269 1270 static void 1271 sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 1272 { 1273 struct sunxi_mmc_softc *sc = sch; 1274 uint32_t imask; 1275 1276 mutex_enter(&sc->sc_intr_lock); 1277 imask = MMC_READ(sc, SUNXI_MMC_IMASK); 1278 MMC_WRITE(sc, SUNXI_MMC_IMASK, imask | sc->sc_intr_card); 1279 mutex_exit(&sc->sc_intr_lock); 1280 } 1281
Indexes created Tue Sep 30 11:09:46 GMT 2025