sunxi_mmc.c revision 1.4
1 /* $NetBSD: sunxi_mmc.c,v 1.4 2017/08/25 00:07:03 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.4 2017/08/25 00:07:03 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/gpio.h> 39 40 #include <dev/sdmmc/sdmmcvar.h> 41 #include <dev/sdmmc/sdmmcchip.h> 42 #include <dev/sdmmc/sdmmc_ioreg.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/sunxi/sunxi_mmc.h> 47 48 enum sunxi_mmc_timing { 49 SUNXI_MMC_TIMING_400K, 50 SUNXI_MMC_TIMING_25M, 51 SUNXI_MMC_TIMING_50M, 52 SUNXI_MMC_TIMING_50M_DDR, 53 SUNXI_MMC_TIMING_50M_DDR_8BIT, 54 }; 55 56 struct sunxi_mmc_delay { 57 u_int output_phase; 58 u_int sample_phase; 59 }; 60 61 static const struct sunxi_mmc_delay sunxi_mmc_delays[] = { 62 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 63 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 64 [SUNXI_MMC_TIMING_50M] = { 90, 120 }, 65 [SUNXI_MMC_TIMING_50M_DDR] = { 60, 120 }, 66 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 90, 180 }, 67 }; 68 69 #define SUNXI_MMC_NDESC 16 70 #define SUNXI_MMC_DMA_XFERLEN 0x10000 71 #define SUNXI_MMC_DMA_FTRGLEVEL 0x20070008 72 73 struct sunxi_mmc_softc; 74 75 static int sunxi_mmc_match(device_t, cfdata_t, void *); 76 static void sunxi_mmc_attach(device_t, device_t, void *); 77 static void sunxi_mmc_attach_i(device_t); 78 79 static int sunxi_mmc_intr(void *); 80 static int sunxi_mmc_idma_setup(struct sunxi_mmc_softc *); 81 82 static int sunxi_mmc_host_reset(sdmmc_chipset_handle_t); 83 static uint32_t sunxi_mmc_host_ocr(sdmmc_chipset_handle_t); 84 static int sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t); 85 static int sunxi_mmc_card_detect(sdmmc_chipset_handle_t); 86 static int sunxi_mmc_write_protect(sdmmc_chipset_handle_t); 87 static int sunxi_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 88 static int sunxi_mmc_bus_clock(sdmmc_chipset_handle_t, int, bool); 89 static int sunxi_mmc_bus_width(sdmmc_chipset_handle_t, int); 90 static int sunxi_mmc_bus_rod(sdmmc_chipset_handle_t, int); 91 static int sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 92 static void sunxi_mmc_exec_command(sdmmc_chipset_handle_t, 93 struct sdmmc_command *); 94 static void sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 95 static void sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t); 96 97 static struct sdmmc_chip_functions sunxi_mmc_chip_functions = { 98 .host_reset = sunxi_mmc_host_reset, 99 .host_ocr = sunxi_mmc_host_ocr, 100 .host_maxblklen = sunxi_mmc_host_maxblklen, 101 .card_detect = sunxi_mmc_card_detect, 102 .write_protect = sunxi_mmc_write_protect, 103 .bus_power = sunxi_mmc_bus_power, 104 .bus_clock_ddr = sunxi_mmc_bus_clock, 105 .bus_width = sunxi_mmc_bus_width, 106 .bus_rod = sunxi_mmc_bus_rod, 107 .signal_voltage = sunxi_mmc_signal_voltage, 108 .exec_command = sunxi_mmc_exec_command, 109 .card_enable_intr = sunxi_mmc_card_enable_intr, 110 .card_intr_ack = sunxi_mmc_card_intr_ack, 111 }; 112 113 struct sunxi_mmc_softc { 114 device_t sc_dev; 115 bus_space_tag_t sc_bst; 116 bus_space_handle_t sc_bsh; 117 bus_dma_tag_t sc_dmat; 118 int sc_phandle; 119 120 void *sc_ih; 121 kmutex_t sc_intr_lock; 122 kcondvar_t sc_intr_cv; 123 kcondvar_t sc_idst_cv; 124 125 int sc_mmc_width; 126 int sc_mmc_present; 127 128 device_t sc_sdmmc_dev; 129 130 uint32_t sc_dma_ftrglevel; 131 132 uint32_t sc_idma_xferlen; 133 bus_dma_segment_t sc_idma_segs[1]; 134 int sc_idma_nsegs; 135 bus_size_t sc_idma_size; 136 bus_dmamap_t sc_idma_map; 137 int sc_idma_ndesc; 138 void *sc_idma_desc; 139 140 uint32_t sc_intr_rint; 141 uint32_t sc_intr_mint; 142 uint32_t sc_idma_idst; 143 144 struct clk *sc_clk_ahb; 145 struct clk *sc_clk_mmc; 146 struct clk *sc_clk_output; 147 struct clk *sc_clk_sample; 148 149 struct fdtbus_reset *sc_rst_ahb; 150 151 struct fdtbus_gpio_pin *sc_gpio_cd; 152 int sc_gpio_cd_inverted; 153 struct fdtbus_gpio_pin *sc_gpio_wp; 154 int sc_gpio_wp_inverted; 155 156 struct fdtbus_regulator *sc_reg_vqmmc; 157 }; 158 159 CFATTACH_DECL_NEW(sunxi_mmc, sizeof(struct sunxi_mmc_softc), 160 sunxi_mmc_match, sunxi_mmc_attach, NULL, NULL); 161 162 #define MMC_WRITE(sc, reg, val) \ 163 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 164 #define MMC_READ(sc, reg) \ 165 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 166 167 static const char * const compatible[] = { 168 "allwinner,sun5i-a13-mmc", 169 "allwinner,sun7i-a20-mmc", 170 NULL 171 }; 172 173 static int 174 sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux) 175 { 176 struct fdt_attach_args * const faa = aux; 177 178 return of_match_compatible(faa->faa_phandle, compatible); 179 } 180 181 static void 182 sunxi_mmc_attach(device_t parent, device_t self, void *aux) 183 { 184 struct sunxi_mmc_softc * const sc = device_private(self); 185 struct fdt_attach_args * const faa = aux; 186 const int phandle = faa->faa_phandle; 187 char intrstr[128]; 188 bus_addr_t addr; 189 bus_size_t size; 190 191 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 192 aprint_error(": couldn't get registers\n"); 193 return; 194 } 195 196 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 197 sc->sc_clk_mmc = fdtbus_clock_get(phandle, "mmc"); 198 sc->sc_clk_output = fdtbus_clock_get(phandle, "output"); 199 sc->sc_clk_sample = fdtbus_clock_get(phandle, "sample"); 200 201 #if notyet 202 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL || 203 sc->sc_clk_output == NULL || sc->sc_clk_sample == NULL) { 204 #else 205 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL) { 206 #endif 207 aprint_error(": couldn't get clocks\n"); 208 return; 209 } 210 211 sc->sc_rst_ahb = fdtbus_reset_get(phandle, "ahb"); 212 if (sc->sc_rst_ahb == NULL) { 213 aprint_error(": couldn't get resets\n"); 214 return; 215 } 216 217 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(phandle, "vqmmc-supply"); 218 219 if (clk_enable(sc->sc_clk_ahb) != 0 || 220 clk_enable(sc->sc_clk_mmc) != 0) { 221 aprint_error(": couldn't enable clocks\n"); 222 return; 223 } 224 225 if (fdtbus_reset_deassert(sc->sc_rst_ahb) != 0) { 226 aprint_error(": couldn't de-assert resets\n"); 227 return; 228 } 229 230 sc->sc_dev = self; 231 sc->sc_phandle = phandle; 232 sc->sc_bst = faa->faa_bst; 233 sc->sc_dmat = faa->faa_dmat; 234 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 235 cv_init(&sc->sc_intr_cv, "awinmmcirq"); 236 cv_init(&sc->sc_idst_cv, "awinmmcdma"); 237 238 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 239 aprint_error(": couldn't map registers\n"); 240 return; 241 } 242 243 aprint_naive("\n"); 244 aprint_normal(": SD/MMC controller\n"); 245 246 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 247 GPIO_PIN_INPUT); 248 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 249 GPIO_PIN_INPUT); 250 251 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 0 : 1; 252 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 0 : 1; 253 254 sc->sc_dma_ftrglevel = SUNXI_MMC_DMA_FTRGLEVEL; 255 256 if (sunxi_mmc_idma_setup(sc) != 0) { 257 aprint_error_dev(self, "failed to setup DMA\n"); 258 return; 259 } 260 261 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 262 aprint_error_dev(self, "failed to decode interrupt\n"); 263 return; 264 } 265 266 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, FDT_INTR_MPSAFE, 267 sunxi_mmc_intr, sc); 268 if (sc->sc_ih == NULL) { 269 aprint_error_dev(self, "failed to establish interrupt on %s\n", 270 intrstr); 271 return; 272 } 273 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 274 275 config_interrupts(self, sunxi_mmc_attach_i); 276 } 277 278 static int 279 sunxi_mmc_idma_setup(struct sunxi_mmc_softc *sc) 280 { 281 int error; 282 283 sc->sc_idma_xferlen = SUNXI_MMC_DMA_XFERLEN; 284 285 sc->sc_idma_ndesc = SUNXI_MMC_NDESC; 286 sc->sc_idma_size = sizeof(struct sunxi_mmc_idma_descriptor) * 287 sc->sc_idma_ndesc; 288 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 0, 289 sc->sc_idma_size, sc->sc_idma_segs, 1, 290 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 291 if (error) 292 return error; 293 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 294 sc->sc_idma_nsegs, sc->sc_idma_size, 295 &sc->sc_idma_desc, BUS_DMA_WAITOK); 296 if (error) 297 goto free; 298 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 299 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 300 if (error) 301 goto unmap; 302 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 303 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 304 if (error) 305 goto destroy; 306 return 0; 307 308 destroy: 309 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 310 unmap: 311 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 312 free: 313 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 314 return error; 315 } 316 317 static int 318 sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr) 319 { 320 const struct sunxi_mmc_delay *delays; 321 int error, timing; 322 323 if (freq <= 400) { 324 timing = SUNXI_MMC_TIMING_400K; 325 } else if (freq <= 25000) { 326 timing = SUNXI_MMC_TIMING_25M; 327 } else if (freq <= 52000) { 328 if (ddr) { 329 timing = sc->sc_mmc_width == 8 ? 330 SUNXI_MMC_TIMING_50M_DDR_8BIT : 331 SUNXI_MMC_TIMING_50M_DDR; 332 } else { 333 timing = SUNXI_MMC_TIMING_50M; 334 } 335 } else 336 return EINVAL; 337 338 delays = &sunxi_mmc_delays[timing]; 339 340 error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << ddr); 341 if (error != 0) 342 return error; 343 344 if (sc->sc_clk_sample) { 345 error = clk_set_rate(sc->sc_clk_sample, delays->sample_phase); 346 if (error != 0) 347 return error; 348 } 349 if (sc->sc_clk_output) { 350 error = clk_set_rate(sc->sc_clk_output, delays->output_phase); 351 if (error != 0) 352 return error; 353 } 354 355 return 0; 356 } 357 358 static void 359 sunxi_mmc_attach_i(device_t self) 360 { 361 struct sunxi_mmc_softc *sc = device_private(self); 362 struct sdmmcbus_attach_args saa; 363 uint32_t width; 364 365 sunxi_mmc_host_reset(sc); 366 sunxi_mmc_bus_width(sc, 1); 367 sunxi_mmc_set_clock(sc, 400, false); 368 369 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 370 width = 4; 371 372 memset(&saa, 0, sizeof(saa)); 373 saa.saa_busname = "sdmmc"; 374 saa.saa_sct = &sunxi_mmc_chip_functions; 375 saa.saa_sch = sc; 376 saa.saa_dmat = sc->sc_dmat; 377 saa.saa_clkmin = 400; 378 saa.saa_clkmax = 52000; 379 saa.saa_caps = SMC_CAPS_DMA | 380 SMC_CAPS_MULTI_SEG_DMA | 381 SMC_CAPS_AUTO_STOP | 382 SMC_CAPS_SD_HIGHSPEED | 383 SMC_CAPS_MMC_HIGHSPEED | 384 SMC_CAPS_MMC_DDR52 | 385 SMC_CAPS_POLLING; 386 if (width == 4) 387 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 388 if (width == 8) 389 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 390 391 if (sc->sc_gpio_cd) 392 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 393 394 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 395 } 396 397 static int 398 sunxi_mmc_intr(void *priv) 399 { 400 struct sunxi_mmc_softc *sc = priv; 401 uint32_t idst, rint, mint; 402 403 mutex_enter(&sc->sc_intr_lock); 404 idst = MMC_READ(sc, SUNXI_MMC_IDST); 405 rint = MMC_READ(sc, SUNXI_MMC_RINT); 406 mint = MMC_READ(sc, SUNXI_MMC_MINT); 407 if (!idst && !rint && !mint) { 408 mutex_exit(&sc->sc_intr_lock); 409 return 0; 410 } 411 MMC_WRITE(sc, SUNXI_MMC_IDST, idst); 412 MMC_WRITE(sc, SUNXI_MMC_RINT, rint); 413 MMC_WRITE(sc, SUNXI_MMC_MINT, mint); 414 415 #ifdef SUNXI_MMC_DEBUG 416 device_printf(sc->sc_dev, "mmc intr idst=%08X rint=%08X mint=%08X\n", 417 idst, rint, mint); 418 #endif 419 420 if (idst) { 421 sc->sc_idma_idst |= idst; 422 cv_broadcast(&sc->sc_idst_cv); 423 } 424 425 if (rint) { 426 sc->sc_intr_rint |= rint; 427 cv_broadcast(&sc->sc_intr_cv); 428 } 429 430 mutex_exit(&sc->sc_intr_lock); 431 432 return 1; 433 } 434 435 static int 436 sunxi_mmc_wait_rint(struct sunxi_mmc_softc *sc, uint32_t mask, 437 int timeout, bool poll) 438 { 439 int retry; 440 int error; 441 442 KASSERT(mutex_owned(&sc->sc_intr_lock)); 443 444 if (sc->sc_intr_rint & mask) 445 return 0; 446 447 if (poll) 448 retry = timeout / hz * 1000; 449 else 450 retry = timeout / hz; 451 452 while (retry > 0) { 453 if (poll) { 454 sc->sc_intr_rint |= MMC_READ(sc, SUNXI_MMC_RINT); 455 } else { 456 error = cv_timedwait(&sc->sc_intr_cv, 457 &sc->sc_intr_lock, hz); 458 if (error && error != EWOULDBLOCK) 459 return error; 460 } 461 if (sc->sc_intr_rint & mask) 462 return 0; 463 if (poll) 464 delay(1000); 465 --retry; 466 } 467 468 return ETIMEDOUT; 469 } 470 471 static int 472 sunxi_mmc_host_reset(sdmmc_chipset_handle_t sch) 473 { 474 struct sunxi_mmc_softc *sc = sch; 475 int retry = 1000; 476 477 #ifdef SUNXI_MMC_DEBUG 478 aprint_normal_dev(sc->sc_dev, "host reset\n"); 479 #endif 480 481 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 482 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_RESET); 483 while (--retry > 0) { 484 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 485 break; 486 delay(100); 487 } 488 489 MMC_WRITE(sc, SUNXI_MMC_TIMEOUT, 0xffffffff); 490 491 MMC_WRITE(sc, SUNXI_MMC_IMASK, 492 SUNXI_MMC_INT_CMD_DONE | SUNXI_MMC_INT_ERROR | 493 SUNXI_MMC_INT_DATA_OVER | SUNXI_MMC_INT_AUTO_CMD_DONE); 494 495 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 496 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_INTEN); 497 498 return 0; 499 } 500 501 static uint32_t 502 sunxi_mmc_host_ocr(sdmmc_chipset_handle_t sch) 503 { 504 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 505 } 506 507 static int 508 sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 509 { 510 return 8192; 511 } 512 513 static int 514 sunxi_mmc_card_detect(sdmmc_chipset_handle_t sch) 515 { 516 struct sunxi_mmc_softc *sc = sch; 517 518 if (sc->sc_gpio_cd == NULL) { 519 return 1; /* no card detect pin, assume present */ 520 } else { 521 int v = 0, i; 522 for (i = 0; i < 5; i++) { 523 v += (fdtbus_gpio_read(sc->sc_gpio_cd) ^ 524 sc->sc_gpio_cd_inverted); 525 delay(1000); 526 } 527 if (v == 5) 528 sc->sc_mmc_present = 0; 529 else if (v == 0) 530 sc->sc_mmc_present = 1; 531 return sc->sc_mmc_present; 532 } 533 } 534 535 static int 536 sunxi_mmc_write_protect(sdmmc_chipset_handle_t sch) 537 { 538 struct sunxi_mmc_softc *sc = sch; 539 540 if (sc->sc_gpio_wp == NULL) { 541 return 0; /* no write protect pin, assume rw */ 542 } else { 543 return fdtbus_gpio_read(sc->sc_gpio_wp) ^ 544 sc->sc_gpio_wp_inverted; 545 } 546 } 547 548 static int 549 sunxi_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 550 { 551 return 0; 552 } 553 554 static int 555 sunxi_mmc_update_clock(struct sunxi_mmc_softc *sc) 556 { 557 uint32_t cmd; 558 int retry; 559 560 #ifdef SUNXI_MMC_DEBUG 561 aprint_normal_dev(sc->sc_dev, "update clock\n"); 562 #endif 563 564 cmd = SUNXI_MMC_CMD_START | 565 SUNXI_MMC_CMD_UPCLK_ONLY | 566 SUNXI_MMC_CMD_WAIT_PRE_OVER; 567 MMC_WRITE(sc, SUNXI_MMC_CMD, cmd); 568 retry = 0xfffff; 569 while (--retry > 0) { 570 if (!(MMC_READ(sc, SUNXI_MMC_CMD) & SUNXI_MMC_CMD_START)) 571 break; 572 delay(10); 573 } 574 575 if (retry == 0) { 576 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 577 #ifdef SUNXI_MMC_DEBUG 578 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 579 MMC_READ(sc, SUNXI_MMC_GCTRL)); 580 device_printf(sc->sc_dev, "CLKCR: 0x%08x\n", 581 MMC_READ(sc, SUNXI_MMC_CLKCR)); 582 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 583 MMC_READ(sc, SUNXI_MMC_TIMEOUT)); 584 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 585 MMC_READ(sc, SUNXI_MMC_WIDTH)); 586 device_printf(sc->sc_dev, "CMD: 0x%08x\n", 587 MMC_READ(sc, SUNXI_MMC_CMD)); 588 device_printf(sc->sc_dev, "MINT: 0x%08x\n", 589 MMC_READ(sc, SUNXI_MMC_MINT)); 590 device_printf(sc->sc_dev, "RINT: 0x%08x\n", 591 MMC_READ(sc, SUNXI_MMC_RINT)); 592 device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 593 MMC_READ(sc, SUNXI_MMC_STATUS)); 594 #endif 595 return ETIMEDOUT; 596 } 597 598 return 0; 599 } 600 601 static int 602 sunxi_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 603 { 604 struct sunxi_mmc_softc *sc = sch; 605 uint32_t clkcr, gctrl; 606 607 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 608 if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) { 609 clkcr &= ~SUNXI_MMC_CLKCR_CARDCLKON; 610 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 611 if (sunxi_mmc_update_clock(sc) != 0) 612 return 1; 613 } 614 615 if (freq) { 616 617 clkcr &= ~SUNXI_MMC_CLKCR_DIV; 618 clkcr |= __SHIFTIN(ddr, SUNXI_MMC_CLKCR_DIV); 619 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 620 if (sunxi_mmc_update_clock(sc) != 0) 621 return 1; 622 623 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 624 if (ddr) 625 gctrl |= SUNXI_MMC_GCTRL_DDR_MODE; 626 else 627 gctrl &= ~SUNXI_MMC_GCTRL_DDR_MODE; 628 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 629 630 if (sunxi_mmc_set_clock(sc, freq, ddr) != 0) 631 return 1; 632 633 clkcr |= SUNXI_MMC_CLKCR_CARDCLKON; 634 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 635 if (sunxi_mmc_update_clock(sc) != 0) 636 return 1; 637 } 638 639 return 0; 640 } 641 642 static int 643 sunxi_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 644 { 645 struct sunxi_mmc_softc *sc = sch; 646 647 #ifdef SUNXI_MMC_DEBUG 648 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 649 #endif 650 651 switch (width) { 652 case 1: 653 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_1); 654 break; 655 case 4: 656 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_4); 657 break; 658 case 8: 659 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_8); 660 break; 661 default: 662 return 1; 663 } 664 665 sc->sc_mmc_width = width; 666 667 return 0; 668 } 669 670 static int 671 sunxi_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 672 { 673 return -1; 674 } 675 676 static int 677 sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 678 { 679 struct sunxi_mmc_softc *sc = sch; 680 u_int uvol; 681 int error; 682 683 if (sc->sc_reg_vqmmc == NULL) 684 return 0; 685 686 switch (signal_voltage) { 687 case SDMMC_SIGNAL_VOLTAGE_330: 688 uvol = 3300000; 689 break; 690 case SDMMC_SIGNAL_VOLTAGE_180: 691 uvol = 1800000; 692 break; 693 default: 694 return EINVAL; 695 } 696 697 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 698 if (error != 0) 699 return error; 700 701 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 702 } 703 704 static int 705 sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 706 { 707 struct sunxi_mmc_idma_descriptor *dma = sc->sc_idma_desc; 708 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 709 bus_size_t off; 710 int desc, resid, seg; 711 uint32_t val; 712 713 desc = 0; 714 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 715 bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr; 716 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 717 resid = min(len, cmd->c_resid); 718 off = 0; 719 while (resid > 0) { 720 if (desc == sc->sc_idma_ndesc) 721 break; 722 len = min(sc->sc_idma_xferlen, resid); 723 dma[desc].dma_buf_size = htole32(len); 724 dma[desc].dma_buf_addr = htole32(paddr + off); 725 dma[desc].dma_config = htole32(SUNXI_MMC_IDMA_CONFIG_CH | 726 SUNXI_MMC_IDMA_CONFIG_OWN); 727 cmd->c_resid -= len; 728 resid -= len; 729 off += len; 730 if (desc == 0) { 731 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_FD); 732 } 733 if (cmd->c_resid == 0) { 734 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_LD); 735 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_ER); 736 dma[desc].dma_next = 0; 737 } else { 738 dma[desc].dma_config |= 739 htole32(SUNXI_MMC_IDMA_CONFIG_DIC); 740 dma[desc].dma_next = htole32( 741 desc_paddr + ((desc+1) * 742 sizeof(struct sunxi_mmc_idma_descriptor))); 743 } 744 ++desc; 745 } 746 } 747 if (desc == sc->sc_idma_ndesc) { 748 aprint_error_dev(sc->sc_dev, 749 "not enough descriptors for %d byte transfer!\n", 750 cmd->c_datalen); 751 return EIO; 752 } 753 754 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 755 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 756 757 sc->sc_idma_idst = 0; 758 759 val = MMC_READ(sc, SUNXI_MMC_GCTRL); 760 val |= SUNXI_MMC_GCTRL_DMAEN; 761 val |= SUNXI_MMC_GCTRL_INTEN; 762 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 763 val |= SUNXI_MMC_GCTRL_DMARESET; 764 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 765 MMC_WRITE(sc, SUNXI_MMC_DMAC, SUNXI_MMC_DMAC_SOFTRESET); 766 MMC_WRITE(sc, SUNXI_MMC_DMAC, 767 SUNXI_MMC_DMAC_IDMA_ON|SUNXI_MMC_DMAC_FIX_BURST); 768 val = MMC_READ(sc, SUNXI_MMC_IDIE); 769 val &= ~(SUNXI_MMC_IDST_RECEIVE_INT|SUNXI_MMC_IDST_TRANSMIT_INT); 770 if (cmd->c_flags & SCF_CMD_READ) 771 val |= SUNXI_MMC_IDST_RECEIVE_INT; 772 else 773 val |= SUNXI_MMC_IDST_TRANSMIT_INT; 774 MMC_WRITE(sc, SUNXI_MMC_IDIE, val); 775 MMC_WRITE(sc, SUNXI_MMC_DLBA, desc_paddr); 776 MMC_WRITE(sc, SUNXI_MMC_FTRGLEVEL, sc->sc_dma_ftrglevel); 777 778 return 0; 779 } 780 781 static void 782 sunxi_mmc_dma_complete(struct sunxi_mmc_softc *sc) 783 { 784 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 785 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 786 } 787 788 static void 789 sunxi_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 790 { 791 struct sunxi_mmc_softc *sc = sch; 792 uint32_t cmdval = SUNXI_MMC_CMD_START; 793 const bool poll = (cmd->c_flags & SCF_POLL) != 0; 794 int retry; 795 796 #ifdef SUNXI_MMC_DEBUG 797 aprint_normal_dev(sc->sc_dev, 798 "opcode %d flags 0x%x data %p datalen %d blklen %d poll %d\n", 799 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 800 cmd->c_blklen, poll); 801 #endif 802 803 mutex_enter(&sc->sc_intr_lock); 804 805 if (cmd->c_opcode == 0) 806 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 807 if (cmd->c_flags & SCF_RSP_PRESENT) 808 cmdval |= SUNXI_MMC_CMD_RSP_EXP; 809 if (cmd->c_flags & SCF_RSP_136) 810 cmdval |= SUNXI_MMC_CMD_LONG_RSP; 811 if (cmd->c_flags & SCF_RSP_CRC) 812 cmdval |= SUNXI_MMC_CMD_CHECK_RSP_CRC; 813 814 if (cmd->c_datalen > 0) { 815 unsigned int nblks; 816 817 cmdval |= SUNXI_MMC_CMD_DATA_EXP | SUNXI_MMC_CMD_WAIT_PRE_OVER; 818 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 819 cmdval |= SUNXI_MMC_CMD_WRITE; 820 } 821 822 nblks = cmd->c_datalen / cmd->c_blklen; 823 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 824 ++nblks; 825 826 if (nblks > 1) { 827 cmdval |= SUNXI_MMC_CMD_SEND_AUTO_STOP; 828 } 829 830 MMC_WRITE(sc, SUNXI_MMC_BLKSZ, cmd->c_blklen); 831 MMC_WRITE(sc, SUNXI_MMC_BYTECNT, nblks * cmd->c_blklen); 832 } 833 834 sc->sc_intr_rint = 0; 835 836 MMC_WRITE(sc, SUNXI_MMC_A12A, 837 (cmdval & SUNXI_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff); 838 839 MMC_WRITE(sc, SUNXI_MMC_ARG, cmd->c_arg); 840 841 #ifdef SUNXI_MMC_DEBUG 842 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 843 #endif 844 845 if (cmd->c_datalen == 0) { 846 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 847 } else { 848 cmd->c_resid = cmd->c_datalen; 849 cmd->c_error = sunxi_mmc_dma_prepare(sc, cmd); 850 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 851 if (cmd->c_error == 0) { 852 const uint32_t idst_mask = 853 SUNXI_MMC_IDST_ERROR | SUNXI_MMC_IDST_COMPLETE; 854 retry = 10; 855 while ((sc->sc_idma_idst & idst_mask) == 0) { 856 if (retry-- == 0) { 857 cmd->c_error = ETIMEDOUT; 858 break; 859 } 860 cv_timedwait(&sc->sc_idst_cv, 861 &sc->sc_intr_lock, hz); 862 } 863 } 864 sunxi_mmc_dma_complete(sc); 865 if (sc->sc_idma_idst & SUNXI_MMC_IDST_ERROR) { 866 cmd->c_error = EIO; 867 } else if (!(sc->sc_idma_idst & SUNXI_MMC_IDST_COMPLETE)) { 868 cmd->c_error = ETIMEDOUT; 869 } 870 if (cmd->c_error) { 871 #ifdef SUNXI_MMC_DEBUG 872 aprint_error_dev(sc->sc_dev, 873 "xfer failed, error %d\n", cmd->c_error); 874 #endif 875 goto done; 876 } 877 } 878 879 cmd->c_error = sunxi_mmc_wait_rint(sc, 880 SUNXI_MMC_INT_ERROR|SUNXI_MMC_INT_CMD_DONE, hz * 10, poll); 881 if (cmd->c_error == 0 && (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 882 if (sc->sc_intr_rint & SUNXI_MMC_INT_RESP_TIMEOUT) { 883 cmd->c_error = ETIMEDOUT; 884 } else { 885 cmd->c_error = EIO; 886 } 887 } 888 if (cmd->c_error) { 889 #ifdef SUNXI_MMC_DEBUG 890 aprint_error_dev(sc->sc_dev, 891 "cmd failed, error %d\n", cmd->c_error); 892 #endif 893 goto done; 894 } 895 896 if (cmd->c_datalen > 0) { 897 cmd->c_error = sunxi_mmc_wait_rint(sc, 898 SUNXI_MMC_INT_ERROR| 899 SUNXI_MMC_INT_AUTO_CMD_DONE| 900 SUNXI_MMC_INT_DATA_OVER, 901 hz*10, poll); 902 if (cmd->c_error == 0 && 903 (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 904 cmd->c_error = ETIMEDOUT; 905 } 906 if (cmd->c_error) { 907 #ifdef SUNXI_MMC_DEBUG 908 aprint_error_dev(sc->sc_dev, 909 "data timeout, rint = %08x\n", 910 sc->sc_intr_rint); 911 #endif 912 cmd->c_error = ETIMEDOUT; 913 goto done; 914 } 915 } 916 917 if (cmd->c_flags & SCF_RSP_PRESENT) { 918 if (cmd->c_flags & SCF_RSP_136) { 919 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 920 cmd->c_resp[1] = MMC_READ(sc, SUNXI_MMC_RESP1); 921 cmd->c_resp[2] = MMC_READ(sc, SUNXI_MMC_RESP2); 922 cmd->c_resp[3] = MMC_READ(sc, SUNXI_MMC_RESP3); 923 if (cmd->c_flags & SCF_RSP_CRC) { 924 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 925 (cmd->c_resp[1] << 24); 926 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 927 (cmd->c_resp[2] << 24); 928 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 929 (cmd->c_resp[3] << 24); 930 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 931 } 932 } else { 933 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 934 } 935 } 936 937 done: 938 cmd->c_flags |= SCF_ITSDONE; 939 mutex_exit(&sc->sc_intr_lock); 940 941 if (cmd->c_error) { 942 #ifdef SUNXI_MMC_DEBUG 943 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 944 #endif 945 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 946 MMC_READ(sc, SUNXI_MMC_GCTRL) | 947 SUNXI_MMC_GCTRL_DMARESET | SUNXI_MMC_GCTRL_FIFORESET); 948 for (retry = 0; retry < 1000; retry++) { 949 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 950 break; 951 delay(10); 952 } 953 sunxi_mmc_update_clock(sc); 954 } 955 956 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 957 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_FIFORESET); 958 } 959 960 static void 961 sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 962 { 963 } 964 965 static void 966 sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 967 { 968 } 969
Indexes created Tue Sep 30 17:09:57 GMT 2025