sunxi_mmc.c revision 1.7
1 /* $NetBSD: sunxi_mmc.c,v 1.7 2017/09/11 22:00:05 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.7 2017/09/11 22:00:05 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/gpio.h> 39 40 #include <dev/sdmmc/sdmmcvar.h> 41 #include <dev/sdmmc/sdmmcchip.h> 42 #include <dev/sdmmc/sdmmc_ioreg.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/sunxi/sunxi_mmc.h> 47 48 enum sunxi_mmc_timing { 49 SUNXI_MMC_TIMING_400K, 50 SUNXI_MMC_TIMING_25M, 51 SUNXI_MMC_TIMING_50M, 52 SUNXI_MMC_TIMING_50M_DDR, 53 SUNXI_MMC_TIMING_50M_DDR_8BIT, 54 }; 55 56 struct sunxi_mmc_delay { 57 u_int output_phase; 58 u_int sample_phase; 59 }; 60 61 static const struct sunxi_mmc_delay sunxi_mmc_delays[] = { 62 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 63 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 64 [SUNXI_MMC_TIMING_50M] = { 90, 120 }, 65 [SUNXI_MMC_TIMING_50M_DDR] = { 60, 120 }, 66 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 90, 180 }, 67 }; 68 69 #define SUNXI_MMC_NDESC 16 70 71 struct sunxi_mmc_softc; 72 73 static int sunxi_mmc_match(device_t, cfdata_t, void *); 74 static void sunxi_mmc_attach(device_t, device_t, void *); 75 static void sunxi_mmc_attach_i(device_t); 76 77 static int sunxi_mmc_intr(void *); 78 static int sunxi_mmc_idma_setup(struct sunxi_mmc_softc *); 79 80 static int sunxi_mmc_host_reset(sdmmc_chipset_handle_t); 81 static uint32_t sunxi_mmc_host_ocr(sdmmc_chipset_handle_t); 82 static int sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t); 83 static int sunxi_mmc_card_detect(sdmmc_chipset_handle_t); 84 static int sunxi_mmc_write_protect(sdmmc_chipset_handle_t); 85 static int sunxi_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 86 static int sunxi_mmc_bus_clock(sdmmc_chipset_handle_t, int, bool); 87 static int sunxi_mmc_bus_width(sdmmc_chipset_handle_t, int); 88 static int sunxi_mmc_bus_rod(sdmmc_chipset_handle_t, int); 89 static int sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 90 static void sunxi_mmc_exec_command(sdmmc_chipset_handle_t, 91 struct sdmmc_command *); 92 static void sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 93 static void sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t); 94 95 static struct sdmmc_chip_functions sunxi_mmc_chip_functions = { 96 .host_reset = sunxi_mmc_host_reset, 97 .host_ocr = sunxi_mmc_host_ocr, 98 .host_maxblklen = sunxi_mmc_host_maxblklen, 99 .card_detect = sunxi_mmc_card_detect, 100 .write_protect = sunxi_mmc_write_protect, 101 .bus_power = sunxi_mmc_bus_power, 102 .bus_clock_ddr = sunxi_mmc_bus_clock, 103 .bus_width = sunxi_mmc_bus_width, 104 .bus_rod = sunxi_mmc_bus_rod, 105 .signal_voltage = sunxi_mmc_signal_voltage, 106 .exec_command = sunxi_mmc_exec_command, 107 .card_enable_intr = sunxi_mmc_card_enable_intr, 108 .card_intr_ack = sunxi_mmc_card_intr_ack, 109 }; 110 111 struct sunxi_mmc_config { 112 u_int idma_xferlen; 113 u_int flags; 114 #define SUNXI_MMC_FLAG_CALIB_REG 0x01 115 #define SUNXI_MMC_FLAG_NEW_TIMINGS 0x02 116 #define SUNXI_MMC_FLAG_MASK_DATA0 0x04 117 const struct sunxi_mmc_delay *delays; 118 uint32_t dma_ftrglevel; 119 }; 120 121 struct sunxi_mmc_softc { 122 device_t sc_dev; 123 bus_space_tag_t sc_bst; 124 bus_space_handle_t sc_bsh; 125 bus_dma_tag_t sc_dmat; 126 int sc_phandle; 127 128 void *sc_ih; 129 kmutex_t sc_intr_lock; 130 kcondvar_t sc_intr_cv; 131 kcondvar_t sc_idst_cv; 132 133 int sc_mmc_width; 134 int sc_mmc_present; 135 136 device_t sc_sdmmc_dev; 137 138 struct sunxi_mmc_config *sc_config; 139 140 bus_dma_segment_t sc_idma_segs[1]; 141 int sc_idma_nsegs; 142 bus_size_t sc_idma_size; 143 bus_dmamap_t sc_idma_map; 144 int sc_idma_ndesc; 145 void *sc_idma_desc; 146 147 uint32_t sc_intr_rint; 148 uint32_t sc_intr_mint; 149 uint32_t sc_idma_idst; 150 151 struct clk *sc_clk_ahb; 152 struct clk *sc_clk_mmc; 153 struct clk *sc_clk_output; 154 struct clk *sc_clk_sample; 155 156 struct fdtbus_reset *sc_rst_ahb; 157 158 struct fdtbus_gpio_pin *sc_gpio_cd; 159 int sc_gpio_cd_inverted; 160 struct fdtbus_gpio_pin *sc_gpio_wp; 161 int sc_gpio_wp_inverted; 162 163 struct fdtbus_regulator *sc_reg_vqmmc; 164 }; 165 166 CFATTACH_DECL_NEW(sunxi_mmc, sizeof(struct sunxi_mmc_softc), 167 sunxi_mmc_match, sunxi_mmc_attach, NULL, NULL); 168 169 #define MMC_WRITE(sc, reg, val) \ 170 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 171 #define MMC_READ(sc, reg) \ 172 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 173 174 static const struct sunxi_mmc_config sun5i_a13_mmc_config = { 175 .idma_xferlen = 0x10000, 176 .dma_ftrglevel = 0x20070008, 177 .delays = NULL, 178 .flags = 0, 179 }; 180 181 static const struct sunxi_mmc_config sun7i_a20_mmc_config = { 182 .idma_xferlen = 0x10000, 183 .dma_ftrglevel = 0x20070008, 184 .delays = sunxi_mmc_delays, 185 .flags = 0, 186 }; 187 188 static const struct sunxi_mmc_config sun50i_a64_mmc_config = { 189 .idma_xferlen = 0x10000, 190 .dma_ftrglevel = 0x20070008, 191 .delays = NULL, 192 .flags = SUNXI_MMC_FLAG_CALIB_REG | 193 SUNXI_MMC_FLAG_NEW_TIMINGS | 194 SUNXI_MMC_FLAG_MASK_DATA0, 195 }; 196 197 static const struct of_compat_data compat_data[] = { 198 { "allwinner,sun5i-a13-mmc", (uintptr_t)&sun5i_a13_mmc_config }, 199 { "allwinner,sun7i-a20-mmc", (uintptr_t)&sun7i_a20_mmc_config }, 200 { "allwinner,sun50i-a64-mmc", (uintptr_t)&sun50i_a64_mmc_config }, 201 { NULL } 202 }; 203 204 static int 205 sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux) 206 { 207 struct fdt_attach_args * const faa = aux; 208 209 return of_match_compat_data(faa->faa_phandle, compat_data); 210 } 211 212 static void 213 sunxi_mmc_attach(device_t parent, device_t self, void *aux) 214 { 215 struct sunxi_mmc_softc * const sc = device_private(self); 216 struct fdt_attach_args * const faa = aux; 217 const int phandle = faa->faa_phandle; 218 char intrstr[128]; 219 bus_addr_t addr; 220 bus_size_t size; 221 222 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 223 aprint_error(": couldn't get registers\n"); 224 return; 225 } 226 227 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 228 sc->sc_clk_mmc = fdtbus_clock_get(phandle, "mmc"); 229 sc->sc_clk_output = fdtbus_clock_get(phandle, "output"); 230 sc->sc_clk_sample = fdtbus_clock_get(phandle, "sample"); 231 232 #if notyet 233 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL || 234 sc->sc_clk_output == NULL || sc->sc_clk_sample == NULL) { 235 #else 236 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL) { 237 #endif 238 aprint_error(": couldn't get clocks\n"); 239 return; 240 } 241 242 sc->sc_rst_ahb = fdtbus_reset_get(phandle, "ahb"); 243 244 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(phandle, "vqmmc-supply"); 245 246 if (clk_enable(sc->sc_clk_ahb) != 0 || 247 clk_enable(sc->sc_clk_mmc) != 0) { 248 aprint_error(": couldn't enable clocks\n"); 249 return; 250 } 251 252 if (sc->sc_rst_ahb != NULL) { 253 if (fdtbus_reset_deassert(sc->sc_rst_ahb) != 0) { 254 aprint_error(": couldn't de-assert resets\n"); 255 return; 256 } 257 } 258 259 sc->sc_dev = self; 260 sc->sc_phandle = phandle; 261 sc->sc_config = (void *)of_search_compatible(phandle, compat_data)->data; 262 sc->sc_bst = faa->faa_bst; 263 sc->sc_dmat = faa->faa_dmat; 264 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 265 cv_init(&sc->sc_intr_cv, "awinmmcirq"); 266 cv_init(&sc->sc_idst_cv, "awinmmcdma"); 267 268 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 269 aprint_error(": couldn't map registers\n"); 270 return; 271 } 272 273 aprint_naive("\n"); 274 aprint_normal(": SD/MMC controller\n"); 275 276 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 277 GPIO_PIN_INPUT); 278 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 279 GPIO_PIN_INPUT); 280 281 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 0 : 1; 282 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 0 : 1; 283 284 if (sunxi_mmc_idma_setup(sc) != 0) { 285 aprint_error_dev(self, "failed to setup DMA\n"); 286 return; 287 } 288 289 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 290 aprint_error_dev(self, "failed to decode interrupt\n"); 291 return; 292 } 293 294 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, FDT_INTR_MPSAFE, 295 sunxi_mmc_intr, sc); 296 if (sc->sc_ih == NULL) { 297 aprint_error_dev(self, "failed to establish interrupt on %s\n", 298 intrstr); 299 return; 300 } 301 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 302 303 config_interrupts(self, sunxi_mmc_attach_i); 304 } 305 306 static int 307 sunxi_mmc_idma_setup(struct sunxi_mmc_softc *sc) 308 { 309 int error; 310 311 sc->sc_idma_ndesc = SUNXI_MMC_NDESC; 312 sc->sc_idma_size = sizeof(struct sunxi_mmc_idma_descriptor) * 313 sc->sc_idma_ndesc; 314 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 0, 315 sc->sc_idma_size, sc->sc_idma_segs, 1, 316 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 317 if (error) 318 return error; 319 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 320 sc->sc_idma_nsegs, sc->sc_idma_size, 321 &sc->sc_idma_desc, BUS_DMA_WAITOK); 322 if (error) 323 goto free; 324 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 325 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 326 if (error) 327 goto unmap; 328 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 329 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 330 if (error) 331 goto destroy; 332 return 0; 333 334 destroy: 335 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 336 unmap: 337 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 338 free: 339 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 340 return error; 341 } 342 343 static int 344 sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr) 345 { 346 const struct sunxi_mmc_delay *delays; 347 int error, timing; 348 349 if (freq <= 400) { 350 timing = SUNXI_MMC_TIMING_400K; 351 } else if (freq <= 25000) { 352 timing = SUNXI_MMC_TIMING_25M; 353 } else if (freq <= 52000) { 354 if (ddr) { 355 timing = sc->sc_mmc_width == 8 ? 356 SUNXI_MMC_TIMING_50M_DDR_8BIT : 357 SUNXI_MMC_TIMING_50M_DDR; 358 } else { 359 timing = SUNXI_MMC_TIMING_50M; 360 } 361 } else 362 return EINVAL; 363 364 error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << ddr); 365 if (error != 0) 366 return error; 367 368 if (sc->sc_config->delays == NULL) 369 return 0; 370 371 delays = &sc->sc_config->delays[timing]; 372 373 if (sc->sc_clk_sample) { 374 error = clk_set_rate(sc->sc_clk_sample, delays->sample_phase); 375 if (error != 0) 376 return error; 377 } 378 if (sc->sc_clk_output) { 379 error = clk_set_rate(sc->sc_clk_output, delays->output_phase); 380 if (error != 0) 381 return error; 382 } 383 384 return 0; 385 } 386 387 static void 388 sunxi_mmc_attach_i(device_t self) 389 { 390 struct sunxi_mmc_softc *sc = device_private(self); 391 struct sdmmcbus_attach_args saa; 392 uint32_t width; 393 394 sunxi_mmc_host_reset(sc); 395 sunxi_mmc_bus_width(sc, 1); 396 sunxi_mmc_set_clock(sc, 400, false); 397 398 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 399 width = 4; 400 401 memset(&saa, 0, sizeof(saa)); 402 saa.saa_busname = "sdmmc"; 403 saa.saa_sct = &sunxi_mmc_chip_functions; 404 saa.saa_sch = sc; 405 saa.saa_dmat = sc->sc_dmat; 406 saa.saa_clkmin = 400; 407 saa.saa_clkmax = 52000; 408 saa.saa_caps = SMC_CAPS_DMA | 409 SMC_CAPS_MULTI_SEG_DMA | 410 SMC_CAPS_AUTO_STOP | 411 SMC_CAPS_SD_HIGHSPEED | 412 SMC_CAPS_MMC_HIGHSPEED | 413 SMC_CAPS_MMC_DDR52 | 414 SMC_CAPS_POLLING; 415 if (width == 4) 416 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 417 if (width == 8) 418 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 419 420 if (sc->sc_gpio_cd) 421 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 422 423 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 424 } 425 426 static int 427 sunxi_mmc_intr(void *priv) 428 { 429 struct sunxi_mmc_softc *sc = priv; 430 uint32_t idst, rint, mint; 431 432 mutex_enter(&sc->sc_intr_lock); 433 idst = MMC_READ(sc, SUNXI_MMC_IDST); 434 rint = MMC_READ(sc, SUNXI_MMC_RINT); 435 mint = MMC_READ(sc, SUNXI_MMC_MINT); 436 if (!idst && !rint && !mint) { 437 mutex_exit(&sc->sc_intr_lock); 438 return 0; 439 } 440 MMC_WRITE(sc, SUNXI_MMC_IDST, idst); 441 MMC_WRITE(sc, SUNXI_MMC_RINT, rint); 442 MMC_WRITE(sc, SUNXI_MMC_MINT, mint); 443 444 #ifdef SUNXI_MMC_DEBUG 445 device_printf(sc->sc_dev, "mmc intr idst=%08X rint=%08X mint=%08X\n", 446 idst, rint, mint); 447 #endif 448 449 if (idst) { 450 sc->sc_idma_idst |= idst; 451 cv_broadcast(&sc->sc_idst_cv); 452 } 453 454 if (rint) { 455 sc->sc_intr_rint |= rint; 456 cv_broadcast(&sc->sc_intr_cv); 457 } 458 459 mutex_exit(&sc->sc_intr_lock); 460 461 return 1; 462 } 463 464 static int 465 sunxi_mmc_wait_rint(struct sunxi_mmc_softc *sc, uint32_t mask, 466 int timeout, bool poll) 467 { 468 int retry; 469 int error; 470 471 KASSERT(mutex_owned(&sc->sc_intr_lock)); 472 473 if (sc->sc_intr_rint & mask) 474 return 0; 475 476 if (poll) 477 retry = timeout / hz * 1000; 478 else 479 retry = timeout / hz; 480 481 while (retry > 0) { 482 if (poll) { 483 sc->sc_intr_rint |= MMC_READ(sc, SUNXI_MMC_RINT); 484 } else { 485 error = cv_timedwait(&sc->sc_intr_cv, 486 &sc->sc_intr_lock, hz); 487 if (error && error != EWOULDBLOCK) 488 return error; 489 } 490 if (sc->sc_intr_rint & mask) 491 return 0; 492 if (poll) 493 delay(1000); 494 --retry; 495 } 496 497 return ETIMEDOUT; 498 } 499 500 static int 501 sunxi_mmc_host_reset(sdmmc_chipset_handle_t sch) 502 { 503 struct sunxi_mmc_softc *sc = sch; 504 int retry = 1000; 505 506 #ifdef SUNXI_MMC_DEBUG 507 aprint_normal_dev(sc->sc_dev, "host reset\n"); 508 #endif 509 510 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 511 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_RESET); 512 while (--retry > 0) { 513 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 514 break; 515 delay(100); 516 } 517 518 MMC_WRITE(sc, SUNXI_MMC_TIMEOUT, 0xffffffff); 519 520 MMC_WRITE(sc, SUNXI_MMC_IMASK, 521 SUNXI_MMC_INT_CMD_DONE | SUNXI_MMC_INT_ERROR | 522 SUNXI_MMC_INT_DATA_OVER | SUNXI_MMC_INT_AUTO_CMD_DONE); 523 524 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 525 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_INTEN); 526 527 return 0; 528 } 529 530 static uint32_t 531 sunxi_mmc_host_ocr(sdmmc_chipset_handle_t sch) 532 { 533 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 534 } 535 536 static int 537 sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 538 { 539 return 8192; 540 } 541 542 static int 543 sunxi_mmc_card_detect(sdmmc_chipset_handle_t sch) 544 { 545 struct sunxi_mmc_softc *sc = sch; 546 547 if (sc->sc_gpio_cd == NULL) { 548 return 1; /* no card detect pin, assume present */ 549 } else { 550 int v = 0, i; 551 for (i = 0; i < 5; i++) { 552 v += (fdtbus_gpio_read(sc->sc_gpio_cd) ^ 553 sc->sc_gpio_cd_inverted); 554 delay(1000); 555 } 556 if (v == 5) 557 sc->sc_mmc_present = 0; 558 else if (v == 0) 559 sc->sc_mmc_present = 1; 560 return sc->sc_mmc_present; 561 } 562 } 563 564 static int 565 sunxi_mmc_write_protect(sdmmc_chipset_handle_t sch) 566 { 567 struct sunxi_mmc_softc *sc = sch; 568 569 if (sc->sc_gpio_wp == NULL) { 570 return 0; /* no write protect pin, assume rw */ 571 } else { 572 return fdtbus_gpio_read(sc->sc_gpio_wp) ^ 573 sc->sc_gpio_wp_inverted; 574 } 575 } 576 577 static int 578 sunxi_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 579 { 580 return 0; 581 } 582 583 static int 584 sunxi_mmc_update_clock(struct sunxi_mmc_softc *sc) 585 { 586 uint32_t cmd; 587 int retry; 588 589 #ifdef SUNXI_MMC_DEBUG 590 aprint_normal_dev(sc->sc_dev, "update clock\n"); 591 #endif 592 593 cmd = SUNXI_MMC_CMD_START | 594 SUNXI_MMC_CMD_UPCLK_ONLY | 595 SUNXI_MMC_CMD_WAIT_PRE_OVER; 596 MMC_WRITE(sc, SUNXI_MMC_CMD, cmd); 597 retry = 0xfffff; 598 while (--retry > 0) { 599 if (!(MMC_READ(sc, SUNXI_MMC_CMD) & SUNXI_MMC_CMD_START)) 600 break; 601 delay(10); 602 } 603 604 if (retry == 0) { 605 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 606 #ifdef SUNXI_MMC_DEBUG 607 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 608 MMC_READ(sc, SUNXI_MMC_GCTRL)); 609 device_printf(sc->sc_dev, "CLKCR: 0x%08x\n", 610 MMC_READ(sc, SUNXI_MMC_CLKCR)); 611 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 612 MMC_READ(sc, SUNXI_MMC_TIMEOUT)); 613 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 614 MMC_READ(sc, SUNXI_MMC_WIDTH)); 615 device_printf(sc->sc_dev, "CMD: 0x%08x\n", 616 MMC_READ(sc, SUNXI_MMC_CMD)); 617 device_printf(sc->sc_dev, "MINT: 0x%08x\n", 618 MMC_READ(sc, SUNXI_MMC_MINT)); 619 device_printf(sc->sc_dev, "RINT: 0x%08x\n", 620 MMC_READ(sc, SUNXI_MMC_RINT)); 621 device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 622 MMC_READ(sc, SUNXI_MMC_STATUS)); 623 #endif 624 return ETIMEDOUT; 625 } 626 627 return 0; 628 } 629 630 static int 631 sunxi_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 632 { 633 struct sunxi_mmc_softc *sc = sch; 634 uint32_t clkcr, gctrl, ntsr; 635 const u_int flags = sc->sc_config->flags; 636 637 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 638 if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) { 639 clkcr &= ~SUNXI_MMC_CLKCR_CARDCLKON; 640 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 641 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 642 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 643 if (sunxi_mmc_update_clock(sc) != 0) 644 return 1; 645 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 646 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 647 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 648 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 649 } 650 } 651 652 if (freq) { 653 654 clkcr &= ~SUNXI_MMC_CLKCR_DIV; 655 clkcr |= __SHIFTIN(ddr, SUNXI_MMC_CLKCR_DIV); 656 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 657 658 if (flags & SUNXI_MMC_FLAG_NEW_TIMINGS) { 659 ntsr = MMC_READ(sc, SUNXI_MMC_NTSR); 660 ntsr |= SUNXI_MMC_NTSR_MODE_SELECT; 661 MMC_WRITE(sc, SUNXI_MMC_NTSR, ntsr); 662 } 663 664 if (flags & SUNXI_MMC_FLAG_CALIB_REG) 665 MMC_WRITE(sc, SUNXI_MMC_SAMP_DL, SUNXI_MMC_SAMP_DL_SW_EN); 666 667 if (sunxi_mmc_update_clock(sc) != 0) 668 return 1; 669 670 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 671 if (ddr) 672 gctrl |= SUNXI_MMC_GCTRL_DDR_MODE; 673 else 674 gctrl &= ~SUNXI_MMC_GCTRL_DDR_MODE; 675 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 676 677 if (sunxi_mmc_set_clock(sc, freq, ddr) != 0) 678 return 1; 679 680 clkcr |= SUNXI_MMC_CLKCR_CARDCLKON; 681 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 682 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 683 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 684 if (sunxi_mmc_update_clock(sc) != 0) 685 return 1; 686 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 687 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 688 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 689 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 690 } 691 } 692 693 return 0; 694 } 695 696 static int 697 sunxi_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 698 { 699 struct sunxi_mmc_softc *sc = sch; 700 701 #ifdef SUNXI_MMC_DEBUG 702 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 703 #endif 704 705 switch (width) { 706 case 1: 707 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_1); 708 break; 709 case 4: 710 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_4); 711 break; 712 case 8: 713 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_8); 714 break; 715 default: 716 return 1; 717 } 718 719 sc->sc_mmc_width = width; 720 721 return 0; 722 } 723 724 static int 725 sunxi_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 726 { 727 return -1; 728 } 729 730 static int 731 sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 732 { 733 struct sunxi_mmc_softc *sc = sch; 734 u_int uvol; 735 int error; 736 737 if (sc->sc_reg_vqmmc == NULL) 738 return 0; 739 740 switch (signal_voltage) { 741 case SDMMC_SIGNAL_VOLTAGE_330: 742 uvol = 3300000; 743 break; 744 case SDMMC_SIGNAL_VOLTAGE_180: 745 uvol = 1800000; 746 break; 747 default: 748 return EINVAL; 749 } 750 751 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 752 if (error != 0) 753 return error; 754 755 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 756 } 757 758 static int 759 sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 760 { 761 struct sunxi_mmc_idma_descriptor *dma = sc->sc_idma_desc; 762 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 763 bus_size_t off; 764 int desc, resid, seg; 765 uint32_t val; 766 767 desc = 0; 768 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 769 bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr; 770 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 771 resid = min(len, cmd->c_resid); 772 off = 0; 773 while (resid > 0) { 774 if (desc == sc->sc_idma_ndesc) 775 break; 776 len = min(sc->sc_config->idma_xferlen, resid); 777 dma[desc].dma_buf_size = htole32(len); 778 dma[desc].dma_buf_addr = htole32(paddr + off); 779 dma[desc].dma_config = htole32(SUNXI_MMC_IDMA_CONFIG_CH | 780 SUNXI_MMC_IDMA_CONFIG_OWN); 781 cmd->c_resid -= len; 782 resid -= len; 783 off += len; 784 if (desc == 0) { 785 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_FD); 786 } 787 if (cmd->c_resid == 0) { 788 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_LD); 789 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_ER); 790 dma[desc].dma_next = 0; 791 } else { 792 dma[desc].dma_config |= 793 htole32(SUNXI_MMC_IDMA_CONFIG_DIC); 794 dma[desc].dma_next = htole32( 795 desc_paddr + ((desc+1) * 796 sizeof(struct sunxi_mmc_idma_descriptor))); 797 } 798 ++desc; 799 } 800 } 801 if (desc == sc->sc_idma_ndesc) { 802 aprint_error_dev(sc->sc_dev, 803 "not enough descriptors for %d byte transfer!\n", 804 cmd->c_datalen); 805 return EIO; 806 } 807 808 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 809 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 810 811 sc->sc_idma_idst = 0; 812 813 val = MMC_READ(sc, SUNXI_MMC_GCTRL); 814 val |= SUNXI_MMC_GCTRL_DMAEN; 815 val |= SUNXI_MMC_GCTRL_INTEN; 816 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 817 val |= SUNXI_MMC_GCTRL_DMARESET; 818 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 819 MMC_WRITE(sc, SUNXI_MMC_DMAC, SUNXI_MMC_DMAC_SOFTRESET); 820 MMC_WRITE(sc, SUNXI_MMC_DMAC, 821 SUNXI_MMC_DMAC_IDMA_ON|SUNXI_MMC_DMAC_FIX_BURST); 822 val = MMC_READ(sc, SUNXI_MMC_IDIE); 823 val &= ~(SUNXI_MMC_IDST_RECEIVE_INT|SUNXI_MMC_IDST_TRANSMIT_INT); 824 if (cmd->c_flags & SCF_CMD_READ) 825 val |= SUNXI_MMC_IDST_RECEIVE_INT; 826 else 827 val |= SUNXI_MMC_IDST_TRANSMIT_INT; 828 MMC_WRITE(sc, SUNXI_MMC_IDIE, val); 829 MMC_WRITE(sc, SUNXI_MMC_DLBA, desc_paddr); 830 MMC_WRITE(sc, SUNXI_MMC_FTRGLEVEL, sc->sc_config->dma_ftrglevel); 831 832 return 0; 833 } 834 835 static void 836 sunxi_mmc_dma_complete(struct sunxi_mmc_softc *sc) 837 { 838 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 839 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 840 } 841 842 static void 843 sunxi_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 844 { 845 struct sunxi_mmc_softc *sc = sch; 846 uint32_t cmdval = SUNXI_MMC_CMD_START; 847 const bool poll = (cmd->c_flags & SCF_POLL) != 0; 848 int retry; 849 850 #ifdef SUNXI_MMC_DEBUG 851 aprint_normal_dev(sc->sc_dev, 852 "opcode %d flags 0x%x data %p datalen %d blklen %d poll %d\n", 853 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 854 cmd->c_blklen, poll); 855 #endif 856 857 mutex_enter(&sc->sc_intr_lock); 858 859 if (cmd->c_opcode == 0) 860 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 861 if (cmd->c_flags & SCF_RSP_PRESENT) 862 cmdval |= SUNXI_MMC_CMD_RSP_EXP; 863 if (cmd->c_flags & SCF_RSP_136) 864 cmdval |= SUNXI_MMC_CMD_LONG_RSP; 865 if (cmd->c_flags & SCF_RSP_CRC) 866 cmdval |= SUNXI_MMC_CMD_CHECK_RSP_CRC; 867 868 if (cmd->c_datalen > 0) { 869 unsigned int nblks; 870 871 cmdval |= SUNXI_MMC_CMD_DATA_EXP | SUNXI_MMC_CMD_WAIT_PRE_OVER; 872 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 873 cmdval |= SUNXI_MMC_CMD_WRITE; 874 } 875 876 nblks = cmd->c_datalen / cmd->c_blklen; 877 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 878 ++nblks; 879 880 if (nblks > 1) { 881 cmdval |= SUNXI_MMC_CMD_SEND_AUTO_STOP; 882 } 883 884 MMC_WRITE(sc, SUNXI_MMC_BLKSZ, cmd->c_blklen); 885 MMC_WRITE(sc, SUNXI_MMC_BYTECNT, nblks * cmd->c_blklen); 886 } 887 888 sc->sc_intr_rint = 0; 889 890 MMC_WRITE(sc, SUNXI_MMC_A12A, 891 (cmdval & SUNXI_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff); 892 893 MMC_WRITE(sc, SUNXI_MMC_ARG, cmd->c_arg); 894 895 #ifdef SUNXI_MMC_DEBUG 896 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 897 #endif 898 899 if (cmd->c_datalen == 0) { 900 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 901 } else { 902 cmd->c_resid = cmd->c_datalen; 903 cmd->c_error = sunxi_mmc_dma_prepare(sc, cmd); 904 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 905 if (cmd->c_error == 0) { 906 const uint32_t idst_mask = 907 SUNXI_MMC_IDST_ERROR | SUNXI_MMC_IDST_COMPLETE; 908 retry = 10; 909 while ((sc->sc_idma_idst & idst_mask) == 0) { 910 if (retry-- == 0) { 911 cmd->c_error = ETIMEDOUT; 912 break; 913 } 914 cv_timedwait(&sc->sc_idst_cv, 915 &sc->sc_intr_lock, hz); 916 } 917 } 918 sunxi_mmc_dma_complete(sc); 919 if (sc->sc_idma_idst & SUNXI_MMC_IDST_ERROR) { 920 cmd->c_error = EIO; 921 } else if (!(sc->sc_idma_idst & SUNXI_MMC_IDST_COMPLETE)) { 922 cmd->c_error = ETIMEDOUT; 923 } 924 if (cmd->c_error) { 925 #ifdef SUNXI_MMC_DEBUG 926 aprint_error_dev(sc->sc_dev, 927 "xfer failed, error %d\n", cmd->c_error); 928 #endif 929 goto done; 930 } 931 } 932 933 cmd->c_error = sunxi_mmc_wait_rint(sc, 934 SUNXI_MMC_INT_ERROR|SUNXI_MMC_INT_CMD_DONE, hz * 10, poll); 935 if (cmd->c_error == 0 && (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 936 if (sc->sc_intr_rint & SUNXI_MMC_INT_RESP_TIMEOUT) { 937 cmd->c_error = ETIMEDOUT; 938 } else { 939 cmd->c_error = EIO; 940 } 941 } 942 if (cmd->c_error) { 943 #ifdef SUNXI_MMC_DEBUG 944 aprint_error_dev(sc->sc_dev, 945 "cmd failed, error %d\n", cmd->c_error); 946 #endif 947 goto done; 948 } 949 950 if (cmd->c_datalen > 0) { 951 cmd->c_error = sunxi_mmc_wait_rint(sc, 952 SUNXI_MMC_INT_ERROR| 953 SUNXI_MMC_INT_AUTO_CMD_DONE| 954 SUNXI_MMC_INT_DATA_OVER, 955 hz*10, poll); 956 if (cmd->c_error == 0 && 957 (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 958 cmd->c_error = ETIMEDOUT; 959 } 960 if (cmd->c_error) { 961 #ifdef SUNXI_MMC_DEBUG 962 aprint_error_dev(sc->sc_dev, 963 "data timeout, rint = %08x\n", 964 sc->sc_intr_rint); 965 #endif 966 cmd->c_error = ETIMEDOUT; 967 goto done; 968 } 969 } 970 971 if (cmd->c_flags & SCF_RSP_PRESENT) { 972 if (cmd->c_flags & SCF_RSP_136) { 973 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 974 cmd->c_resp[1] = MMC_READ(sc, SUNXI_MMC_RESP1); 975 cmd->c_resp[2] = MMC_READ(sc, SUNXI_MMC_RESP2); 976 cmd->c_resp[3] = MMC_READ(sc, SUNXI_MMC_RESP3); 977 if (cmd->c_flags & SCF_RSP_CRC) { 978 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 979 (cmd->c_resp[1] << 24); 980 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 981 (cmd->c_resp[2] << 24); 982 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 983 (cmd->c_resp[3] << 24); 984 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 985 } 986 } else { 987 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 988 } 989 } 990 991 done: 992 cmd->c_flags |= SCF_ITSDONE; 993 mutex_exit(&sc->sc_intr_lock); 994 995 if (cmd->c_error) { 996 #ifdef SUNXI_MMC_DEBUG 997 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 998 #endif 999 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1000 MMC_READ(sc, SUNXI_MMC_GCTRL) | 1001 SUNXI_MMC_GCTRL_DMARESET | SUNXI_MMC_GCTRL_FIFORESET); 1002 for (retry = 0; retry < 1000; retry++) { 1003 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 1004 break; 1005 delay(10); 1006 } 1007 sunxi_mmc_update_clock(sc); 1008 } 1009 1010 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1011 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_FIFORESET); 1012 } 1013 1014 static void 1015 sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1016 { 1017 } 1018 1019 static void 1020 sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 1021 { 1022 } 1023
Indexes created Tue Sep 30 11:09:46 GMT 2025