sunxi_mmc.c revision 1.9
1 /* $NetBSD: sunxi_mmc.c,v 1.9 2017/10/08 13:48:40 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_mmc.c,v 1.9 2017/10/08 13:48:40 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/gpio.h> 39 40 #include <dev/sdmmc/sdmmcvar.h> 41 #include <dev/sdmmc/sdmmcchip.h> 42 #include <dev/sdmmc/sdmmc_ioreg.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/sunxi/sunxi_mmc.h> 47 48 enum sunxi_mmc_timing { 49 SUNXI_MMC_TIMING_400K, 50 SUNXI_MMC_TIMING_25M, 51 SUNXI_MMC_TIMING_50M, 52 SUNXI_MMC_TIMING_50M_DDR, 53 SUNXI_MMC_TIMING_50M_DDR_8BIT, 54 }; 55 56 struct sunxi_mmc_delay { 57 u_int output_phase; 58 u_int sample_phase; 59 }; 60 61 static const struct sunxi_mmc_delay sunxi_mmc_delays[] = { 62 [SUNXI_MMC_TIMING_400K] = { 180, 180 }, 63 [SUNXI_MMC_TIMING_25M] = { 180, 75 }, 64 [SUNXI_MMC_TIMING_50M] = { 90, 120 }, 65 [SUNXI_MMC_TIMING_50M_DDR] = { 60, 120 }, 66 [SUNXI_MMC_TIMING_50M_DDR_8BIT] = { 90, 180 }, 67 }; 68 69 #define SUNXI_MMC_NDESC 16 70 71 struct sunxi_mmc_softc; 72 73 static int sunxi_mmc_match(device_t, cfdata_t, void *); 74 static void sunxi_mmc_attach(device_t, device_t, void *); 75 static void sunxi_mmc_attach_i(device_t); 76 77 static int sunxi_mmc_intr(void *); 78 static int sunxi_mmc_idma_setup(struct sunxi_mmc_softc *); 79 80 static int sunxi_mmc_host_reset(sdmmc_chipset_handle_t); 81 static uint32_t sunxi_mmc_host_ocr(sdmmc_chipset_handle_t); 82 static int sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t); 83 static int sunxi_mmc_card_detect(sdmmc_chipset_handle_t); 84 static int sunxi_mmc_write_protect(sdmmc_chipset_handle_t); 85 static int sunxi_mmc_bus_power(sdmmc_chipset_handle_t, uint32_t); 86 static int sunxi_mmc_bus_clock(sdmmc_chipset_handle_t, int, bool); 87 static int sunxi_mmc_bus_width(sdmmc_chipset_handle_t, int); 88 static int sunxi_mmc_bus_rod(sdmmc_chipset_handle_t, int); 89 static int sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t, int); 90 static void sunxi_mmc_exec_command(sdmmc_chipset_handle_t, 91 struct sdmmc_command *); 92 static void sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t, int); 93 static void sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t); 94 95 static struct sdmmc_chip_functions sunxi_mmc_chip_functions = { 96 .host_reset = sunxi_mmc_host_reset, 97 .host_ocr = sunxi_mmc_host_ocr, 98 .host_maxblklen = sunxi_mmc_host_maxblklen, 99 .card_detect = sunxi_mmc_card_detect, 100 .write_protect = sunxi_mmc_write_protect, 101 .bus_power = sunxi_mmc_bus_power, 102 .bus_clock_ddr = sunxi_mmc_bus_clock, 103 .bus_width = sunxi_mmc_bus_width, 104 .bus_rod = sunxi_mmc_bus_rod, 105 .signal_voltage = sunxi_mmc_signal_voltage, 106 .exec_command = sunxi_mmc_exec_command, 107 .card_enable_intr = sunxi_mmc_card_enable_intr, 108 .card_intr_ack = sunxi_mmc_card_intr_ack, 109 }; 110 111 struct sunxi_mmc_config { 112 u_int idma_xferlen; 113 u_int flags; 114 #define SUNXI_MMC_FLAG_CALIB_REG 0x01 115 #define SUNXI_MMC_FLAG_NEW_TIMINGS 0x02 116 #define SUNXI_MMC_FLAG_MASK_DATA0 0x04 117 const struct sunxi_mmc_delay *delays; 118 uint32_t dma_ftrglevel; 119 }; 120 121 struct sunxi_mmc_softc { 122 device_t sc_dev; 123 bus_space_tag_t sc_bst; 124 bus_space_handle_t sc_bsh; 125 bus_dma_tag_t sc_dmat; 126 int sc_phandle; 127 128 void *sc_ih; 129 kmutex_t sc_intr_lock; 130 kcondvar_t sc_intr_cv; 131 kcondvar_t sc_idst_cv; 132 133 int sc_mmc_width; 134 int sc_mmc_present; 135 136 device_t sc_sdmmc_dev; 137 138 struct sunxi_mmc_config *sc_config; 139 140 bus_dma_segment_t sc_idma_segs[1]; 141 int sc_idma_nsegs; 142 bus_size_t sc_idma_size; 143 bus_dmamap_t sc_idma_map; 144 int sc_idma_ndesc; 145 void *sc_idma_desc; 146 147 uint32_t sc_intr_rint; 148 uint32_t sc_intr_mint; 149 uint32_t sc_idma_idst; 150 151 struct clk *sc_clk_ahb; 152 struct clk *sc_clk_mmc; 153 struct clk *sc_clk_output; 154 struct clk *sc_clk_sample; 155 156 struct fdtbus_reset *sc_rst_ahb; 157 158 struct fdtbus_gpio_pin *sc_gpio_cd; 159 int sc_gpio_cd_inverted; 160 struct fdtbus_gpio_pin *sc_gpio_wp; 161 int sc_gpio_wp_inverted; 162 163 struct fdtbus_regulator *sc_reg_vqmmc; 164 }; 165 166 CFATTACH_DECL_NEW(sunxi_mmc, sizeof(struct sunxi_mmc_softc), 167 sunxi_mmc_match, sunxi_mmc_attach, NULL, NULL); 168 169 #define MMC_WRITE(sc, reg, val) \ 170 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 171 #define MMC_READ(sc, reg) \ 172 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 173 174 static const struct sunxi_mmc_config sun4i_a10_mmc_config = { 175 .idma_xferlen = 0x2000, 176 .dma_ftrglevel = 0x20070008, 177 .delays = NULL, 178 .flags = 0, 179 }; 180 181 static const struct sunxi_mmc_config sun5i_a13_mmc_config = { 182 .idma_xferlen = 0x10000, 183 .dma_ftrglevel = 0x20070008, 184 .delays = NULL, 185 .flags = 0, 186 }; 187 188 static const struct sunxi_mmc_config sun7i_a20_mmc_config = { 189 .idma_xferlen = 0x2000, 190 .dma_ftrglevel = 0x20070008, 191 .delays = sunxi_mmc_delays, 192 .flags = 0, 193 }; 194 195 static const struct sunxi_mmc_config sun50i_a64_mmc_config = { 196 .idma_xferlen = 0x10000, 197 .dma_ftrglevel = 0x20070008, 198 .delays = NULL, 199 .flags = SUNXI_MMC_FLAG_CALIB_REG | 200 SUNXI_MMC_FLAG_NEW_TIMINGS | 201 SUNXI_MMC_FLAG_MASK_DATA0, 202 }; 203 204 static const struct of_compat_data compat_data[] = { 205 { "allwinner,sun4i-a10-mmc", (uintptr_t)&sun4i_a10_mmc_config }, 206 { "allwinner,sun5i-a13-mmc", (uintptr_t)&sun5i_a13_mmc_config }, 207 { "allwinner,sun7i-a20-mmc", (uintptr_t)&sun7i_a20_mmc_config }, 208 { "allwinner,sun50i-a64-mmc", (uintptr_t)&sun50i_a64_mmc_config }, 209 { NULL } 210 }; 211 212 static int 213 sunxi_mmc_match(device_t parent, cfdata_t cf, void *aux) 214 { 215 struct fdt_attach_args * const faa = aux; 216 217 return of_match_compat_data(faa->faa_phandle, compat_data); 218 } 219 220 static void 221 sunxi_mmc_attach(device_t parent, device_t self, void *aux) 222 { 223 struct sunxi_mmc_softc * const sc = device_private(self); 224 struct fdt_attach_args * const faa = aux; 225 const int phandle = faa->faa_phandle; 226 char intrstr[128]; 227 bus_addr_t addr; 228 bus_size_t size; 229 230 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 231 aprint_error(": couldn't get registers\n"); 232 return; 233 } 234 235 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 236 sc->sc_clk_mmc = fdtbus_clock_get(phandle, "mmc"); 237 sc->sc_clk_output = fdtbus_clock_get(phandle, "output"); 238 sc->sc_clk_sample = fdtbus_clock_get(phandle, "sample"); 239 240 #if notyet 241 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL || 242 sc->sc_clk_output == NULL || sc->sc_clk_sample == NULL) { 243 #else 244 if (sc->sc_clk_ahb == NULL || sc->sc_clk_mmc == NULL) { 245 #endif 246 aprint_error(": couldn't get clocks\n"); 247 return; 248 } 249 250 sc->sc_rst_ahb = fdtbus_reset_get(phandle, "ahb"); 251 252 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(phandle, "vqmmc-supply"); 253 254 if (clk_enable(sc->sc_clk_ahb) != 0 || 255 clk_enable(sc->sc_clk_mmc) != 0) { 256 aprint_error(": couldn't enable clocks\n"); 257 return; 258 } 259 260 if (sc->sc_rst_ahb != NULL) { 261 if (fdtbus_reset_deassert(sc->sc_rst_ahb) != 0) { 262 aprint_error(": couldn't de-assert resets\n"); 263 return; 264 } 265 } 266 267 sc->sc_dev = self; 268 sc->sc_phandle = phandle; 269 sc->sc_config = (void *)of_search_compatible(phandle, compat_data)->data; 270 sc->sc_bst = faa->faa_bst; 271 sc->sc_dmat = faa->faa_dmat; 272 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_BIO); 273 cv_init(&sc->sc_intr_cv, "awinmmcirq"); 274 cv_init(&sc->sc_idst_cv, "awinmmcdma"); 275 276 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 277 aprint_error(": couldn't map registers\n"); 278 return; 279 } 280 281 aprint_naive("\n"); 282 aprint_normal(": SD/MMC controller\n"); 283 284 sc->sc_gpio_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 285 GPIO_PIN_INPUT); 286 sc->sc_gpio_wp = fdtbus_gpio_acquire(phandle, "wp-gpios", 287 GPIO_PIN_INPUT); 288 289 sc->sc_gpio_cd_inverted = of_hasprop(phandle, "cd-inverted") ? 0 : 1; 290 sc->sc_gpio_wp_inverted = of_hasprop(phandle, "wp-inverted") ? 0 : 1; 291 292 if (sunxi_mmc_idma_setup(sc) != 0) { 293 aprint_error_dev(self, "failed to setup DMA\n"); 294 return; 295 } 296 297 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 298 aprint_error_dev(self, "failed to decode interrupt\n"); 299 return; 300 } 301 302 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, FDT_INTR_MPSAFE, 303 sunxi_mmc_intr, sc); 304 if (sc->sc_ih == NULL) { 305 aprint_error_dev(self, "failed to establish interrupt on %s\n", 306 intrstr); 307 return; 308 } 309 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 310 311 config_interrupts(self, sunxi_mmc_attach_i); 312 } 313 314 static int 315 sunxi_mmc_idma_setup(struct sunxi_mmc_softc *sc) 316 { 317 int error; 318 319 sc->sc_idma_ndesc = SUNXI_MMC_NDESC; 320 sc->sc_idma_size = sizeof(struct sunxi_mmc_idma_descriptor) * 321 sc->sc_idma_ndesc; 322 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_idma_size, 0, 323 sc->sc_idma_size, sc->sc_idma_segs, 1, 324 &sc->sc_idma_nsegs, BUS_DMA_WAITOK); 325 if (error) 326 return error; 327 error = bus_dmamem_map(sc->sc_dmat, sc->sc_idma_segs, 328 sc->sc_idma_nsegs, sc->sc_idma_size, 329 &sc->sc_idma_desc, BUS_DMA_WAITOK); 330 if (error) 331 goto free; 332 error = bus_dmamap_create(sc->sc_dmat, sc->sc_idma_size, 1, 333 sc->sc_idma_size, 0, BUS_DMA_WAITOK, &sc->sc_idma_map); 334 if (error) 335 goto unmap; 336 error = bus_dmamap_load(sc->sc_dmat, sc->sc_idma_map, 337 sc->sc_idma_desc, sc->sc_idma_size, NULL, BUS_DMA_WAITOK); 338 if (error) 339 goto destroy; 340 return 0; 341 342 destroy: 343 bus_dmamap_destroy(sc->sc_dmat, sc->sc_idma_map); 344 unmap: 345 bus_dmamem_unmap(sc->sc_dmat, sc->sc_idma_desc, sc->sc_idma_size); 346 free: 347 bus_dmamem_free(sc->sc_dmat, sc->sc_idma_segs, sc->sc_idma_nsegs); 348 return error; 349 } 350 351 static int 352 sunxi_mmc_set_clock(struct sunxi_mmc_softc *sc, u_int freq, bool ddr) 353 { 354 const struct sunxi_mmc_delay *delays; 355 int error, timing; 356 357 if (freq <= 400) { 358 timing = SUNXI_MMC_TIMING_400K; 359 } else if (freq <= 25000) { 360 timing = SUNXI_MMC_TIMING_25M; 361 } else if (freq <= 52000) { 362 if (ddr) { 363 timing = sc->sc_mmc_width == 8 ? 364 SUNXI_MMC_TIMING_50M_DDR_8BIT : 365 SUNXI_MMC_TIMING_50M_DDR; 366 } else { 367 timing = SUNXI_MMC_TIMING_50M; 368 } 369 } else 370 return EINVAL; 371 372 error = clk_set_rate(sc->sc_clk_mmc, (freq * 1000) << ddr); 373 if (error != 0) 374 return error; 375 376 if (sc->sc_config->delays == NULL) 377 return 0; 378 379 delays = &sc->sc_config->delays[timing]; 380 381 if (sc->sc_clk_sample) { 382 error = clk_set_rate(sc->sc_clk_sample, delays->sample_phase); 383 if (error != 0) 384 return error; 385 } 386 if (sc->sc_clk_output) { 387 error = clk_set_rate(sc->sc_clk_output, delays->output_phase); 388 if (error != 0) 389 return error; 390 } 391 392 return 0; 393 } 394 395 static void 396 sunxi_mmc_attach_i(device_t self) 397 { 398 struct sunxi_mmc_softc *sc = device_private(self); 399 struct sdmmcbus_attach_args saa; 400 uint32_t width; 401 402 sunxi_mmc_host_reset(sc); 403 sunxi_mmc_bus_width(sc, 1); 404 sunxi_mmc_set_clock(sc, 400, false); 405 406 if (of_getprop_uint32(sc->sc_phandle, "bus-width", &width) != 0) 407 width = 4; 408 409 memset(&saa, 0, sizeof(saa)); 410 saa.saa_busname = "sdmmc"; 411 saa.saa_sct = &sunxi_mmc_chip_functions; 412 saa.saa_sch = sc; 413 saa.saa_dmat = sc->sc_dmat; 414 saa.saa_clkmin = 400; 415 saa.saa_clkmax = 52000; 416 saa.saa_caps = SMC_CAPS_DMA | 417 SMC_CAPS_MULTI_SEG_DMA | 418 SMC_CAPS_AUTO_STOP | 419 SMC_CAPS_SD_HIGHSPEED | 420 SMC_CAPS_MMC_HIGHSPEED | 421 SMC_CAPS_MMC_DDR52 | 422 SMC_CAPS_POLLING; 423 if (width == 4) 424 saa.saa_caps |= SMC_CAPS_4BIT_MODE; 425 if (width == 8) 426 saa.saa_caps |= SMC_CAPS_8BIT_MODE; 427 428 if (sc->sc_gpio_cd) 429 saa.saa_caps |= SMC_CAPS_POLL_CARD_DET; 430 431 sc->sc_sdmmc_dev = config_found(self, &saa, NULL); 432 } 433 434 static int 435 sunxi_mmc_intr(void *priv) 436 { 437 struct sunxi_mmc_softc *sc = priv; 438 uint32_t idst, rint, mint; 439 440 mutex_enter(&sc->sc_intr_lock); 441 idst = MMC_READ(sc, SUNXI_MMC_IDST); 442 rint = MMC_READ(sc, SUNXI_MMC_RINT); 443 mint = MMC_READ(sc, SUNXI_MMC_MINT); 444 if (!idst && !rint && !mint) { 445 mutex_exit(&sc->sc_intr_lock); 446 return 0; 447 } 448 MMC_WRITE(sc, SUNXI_MMC_IDST, idst); 449 MMC_WRITE(sc, SUNXI_MMC_RINT, rint); 450 MMC_WRITE(sc, SUNXI_MMC_MINT, mint); 451 452 #ifdef SUNXI_MMC_DEBUG 453 device_printf(sc->sc_dev, "mmc intr idst=%08X rint=%08X mint=%08X\n", 454 idst, rint, mint); 455 #endif 456 457 if (idst) { 458 sc->sc_idma_idst |= idst; 459 cv_broadcast(&sc->sc_idst_cv); 460 } 461 462 if (rint) { 463 sc->sc_intr_rint |= rint; 464 cv_broadcast(&sc->sc_intr_cv); 465 } 466 467 mutex_exit(&sc->sc_intr_lock); 468 469 return 1; 470 } 471 472 static int 473 sunxi_mmc_wait_rint(struct sunxi_mmc_softc *sc, uint32_t mask, 474 int timeout, bool poll) 475 { 476 int retry; 477 int error; 478 479 KASSERT(mutex_owned(&sc->sc_intr_lock)); 480 481 if (sc->sc_intr_rint & mask) 482 return 0; 483 484 if (poll) 485 retry = timeout / hz * 1000; 486 else 487 retry = timeout / hz; 488 489 while (retry > 0) { 490 if (poll) { 491 sc->sc_intr_rint |= MMC_READ(sc, SUNXI_MMC_RINT); 492 } else { 493 error = cv_timedwait(&sc->sc_intr_cv, 494 &sc->sc_intr_lock, hz); 495 if (error && error != EWOULDBLOCK) 496 return error; 497 } 498 if (sc->sc_intr_rint & mask) 499 return 0; 500 if (poll) 501 delay(1000); 502 --retry; 503 } 504 505 return ETIMEDOUT; 506 } 507 508 static int 509 sunxi_mmc_host_reset(sdmmc_chipset_handle_t sch) 510 { 511 struct sunxi_mmc_softc *sc = sch; 512 int retry = 1000; 513 514 #ifdef SUNXI_MMC_DEBUG 515 aprint_normal_dev(sc->sc_dev, "host reset\n"); 516 #endif 517 518 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 519 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_RESET); 520 while (--retry > 0) { 521 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 522 break; 523 delay(100); 524 } 525 526 MMC_WRITE(sc, SUNXI_MMC_TIMEOUT, 0xffffffff); 527 528 MMC_WRITE(sc, SUNXI_MMC_IMASK, 529 SUNXI_MMC_INT_CMD_DONE | SUNXI_MMC_INT_ERROR | 530 SUNXI_MMC_INT_DATA_OVER | SUNXI_MMC_INT_AUTO_CMD_DONE); 531 532 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 533 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_INTEN); 534 535 return 0; 536 } 537 538 static uint32_t 539 sunxi_mmc_host_ocr(sdmmc_chipset_handle_t sch) 540 { 541 return MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V | MMC_OCR_HCS; 542 } 543 544 static int 545 sunxi_mmc_host_maxblklen(sdmmc_chipset_handle_t sch) 546 { 547 return 8192; 548 } 549 550 static int 551 sunxi_mmc_card_detect(sdmmc_chipset_handle_t sch) 552 { 553 struct sunxi_mmc_softc *sc = sch; 554 555 if (sc->sc_gpio_cd == NULL) { 556 return 1; /* no card detect pin, assume present */ 557 } else { 558 int v = 0, i; 559 for (i = 0; i < 5; i++) { 560 v += (fdtbus_gpio_read(sc->sc_gpio_cd) ^ 561 sc->sc_gpio_cd_inverted); 562 delay(1000); 563 } 564 if (v == 5) 565 sc->sc_mmc_present = 0; 566 else if (v == 0) 567 sc->sc_mmc_present = 1; 568 return sc->sc_mmc_present; 569 } 570 } 571 572 static int 573 sunxi_mmc_write_protect(sdmmc_chipset_handle_t sch) 574 { 575 struct sunxi_mmc_softc *sc = sch; 576 577 if (sc->sc_gpio_wp == NULL) { 578 return 0; /* no write protect pin, assume rw */ 579 } else { 580 return fdtbus_gpio_read(sc->sc_gpio_wp) ^ 581 sc->sc_gpio_wp_inverted; 582 } 583 } 584 585 static int 586 sunxi_mmc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 587 { 588 return 0; 589 } 590 591 static int 592 sunxi_mmc_update_clock(struct sunxi_mmc_softc *sc) 593 { 594 uint32_t cmd; 595 int retry; 596 597 #ifdef SUNXI_MMC_DEBUG 598 aprint_normal_dev(sc->sc_dev, "update clock\n"); 599 #endif 600 601 cmd = SUNXI_MMC_CMD_START | 602 SUNXI_MMC_CMD_UPCLK_ONLY | 603 SUNXI_MMC_CMD_WAIT_PRE_OVER; 604 MMC_WRITE(sc, SUNXI_MMC_CMD, cmd); 605 retry = 0xfffff; 606 while (--retry > 0) { 607 if (!(MMC_READ(sc, SUNXI_MMC_CMD) & SUNXI_MMC_CMD_START)) 608 break; 609 delay(10); 610 } 611 612 if (retry == 0) { 613 aprint_error_dev(sc->sc_dev, "timeout updating clock\n"); 614 #ifdef SUNXI_MMC_DEBUG 615 device_printf(sc->sc_dev, "GCTRL: 0x%08x\n", 616 MMC_READ(sc, SUNXI_MMC_GCTRL)); 617 device_printf(sc->sc_dev, "CLKCR: 0x%08x\n", 618 MMC_READ(sc, SUNXI_MMC_CLKCR)); 619 device_printf(sc->sc_dev, "TIMEOUT: 0x%08x\n", 620 MMC_READ(sc, SUNXI_MMC_TIMEOUT)); 621 device_printf(sc->sc_dev, "WIDTH: 0x%08x\n", 622 MMC_READ(sc, SUNXI_MMC_WIDTH)); 623 device_printf(sc->sc_dev, "CMD: 0x%08x\n", 624 MMC_READ(sc, SUNXI_MMC_CMD)); 625 device_printf(sc->sc_dev, "MINT: 0x%08x\n", 626 MMC_READ(sc, SUNXI_MMC_MINT)); 627 device_printf(sc->sc_dev, "RINT: 0x%08x\n", 628 MMC_READ(sc, SUNXI_MMC_RINT)); 629 device_printf(sc->sc_dev, "STATUS: 0x%08x\n", 630 MMC_READ(sc, SUNXI_MMC_STATUS)); 631 #endif 632 return ETIMEDOUT; 633 } 634 635 return 0; 636 } 637 638 static int 639 sunxi_mmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, bool ddr) 640 { 641 struct sunxi_mmc_softc *sc = sch; 642 uint32_t clkcr, gctrl, ntsr; 643 const u_int flags = sc->sc_config->flags; 644 645 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 646 if (clkcr & SUNXI_MMC_CLKCR_CARDCLKON) { 647 clkcr &= ~SUNXI_MMC_CLKCR_CARDCLKON; 648 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 649 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 650 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 651 if (sunxi_mmc_update_clock(sc) != 0) 652 return 1; 653 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 654 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 655 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 656 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 657 } 658 } 659 660 if (freq) { 661 662 clkcr &= ~SUNXI_MMC_CLKCR_DIV; 663 clkcr |= __SHIFTIN(ddr, SUNXI_MMC_CLKCR_DIV); 664 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 665 666 if (flags & SUNXI_MMC_FLAG_NEW_TIMINGS) { 667 ntsr = MMC_READ(sc, SUNXI_MMC_NTSR); 668 ntsr |= SUNXI_MMC_NTSR_MODE_SELECT; 669 MMC_WRITE(sc, SUNXI_MMC_NTSR, ntsr); 670 } 671 672 if (flags & SUNXI_MMC_FLAG_CALIB_REG) 673 MMC_WRITE(sc, SUNXI_MMC_SAMP_DL, SUNXI_MMC_SAMP_DL_SW_EN); 674 675 if (sunxi_mmc_update_clock(sc) != 0) 676 return 1; 677 678 gctrl = MMC_READ(sc, SUNXI_MMC_GCTRL); 679 if (ddr) 680 gctrl |= SUNXI_MMC_GCTRL_DDR_MODE; 681 else 682 gctrl &= ~SUNXI_MMC_GCTRL_DDR_MODE; 683 MMC_WRITE(sc, SUNXI_MMC_GCTRL, gctrl); 684 685 if (sunxi_mmc_set_clock(sc, freq, ddr) != 0) 686 return 1; 687 688 clkcr |= SUNXI_MMC_CLKCR_CARDCLKON; 689 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) 690 clkcr |= SUNXI_MMC_CLKCR_MASK_DATA0; 691 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 692 if (sunxi_mmc_update_clock(sc) != 0) 693 return 1; 694 if (flags & SUNXI_MMC_CLKCR_MASK_DATA0) { 695 clkcr = MMC_READ(sc, SUNXI_MMC_CLKCR); 696 clkcr &= ~SUNXI_MMC_CLKCR_MASK_DATA0; 697 MMC_WRITE(sc, SUNXI_MMC_CLKCR, clkcr); 698 } 699 } 700 701 return 0; 702 } 703 704 static int 705 sunxi_mmc_bus_width(sdmmc_chipset_handle_t sch, int width) 706 { 707 struct sunxi_mmc_softc *sc = sch; 708 709 #ifdef SUNXI_MMC_DEBUG 710 aprint_normal_dev(sc->sc_dev, "width = %d\n", width); 711 #endif 712 713 switch (width) { 714 case 1: 715 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_1); 716 break; 717 case 4: 718 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_4); 719 break; 720 case 8: 721 MMC_WRITE(sc, SUNXI_MMC_WIDTH, SUNXI_MMC_WIDTH_8); 722 break; 723 default: 724 return 1; 725 } 726 727 sc->sc_mmc_width = width; 728 729 return 0; 730 } 731 732 static int 733 sunxi_mmc_bus_rod(sdmmc_chipset_handle_t sch, int on) 734 { 735 return -1; 736 } 737 738 static int 739 sunxi_mmc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage) 740 { 741 struct sunxi_mmc_softc *sc = sch; 742 u_int uvol; 743 int error; 744 745 if (sc->sc_reg_vqmmc == NULL) 746 return 0; 747 748 switch (signal_voltage) { 749 case SDMMC_SIGNAL_VOLTAGE_330: 750 uvol = 3300000; 751 break; 752 case SDMMC_SIGNAL_VOLTAGE_180: 753 uvol = 1800000; 754 break; 755 default: 756 return EINVAL; 757 } 758 759 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 760 if (error != 0) 761 return error; 762 763 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 764 } 765 766 static int 767 sunxi_mmc_dma_prepare(struct sunxi_mmc_softc *sc, struct sdmmc_command *cmd) 768 { 769 struct sunxi_mmc_idma_descriptor *dma = sc->sc_idma_desc; 770 bus_addr_t desc_paddr = sc->sc_idma_map->dm_segs[0].ds_addr; 771 bus_size_t off; 772 int desc, resid, seg; 773 uint32_t val; 774 775 desc = 0; 776 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) { 777 bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr; 778 bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len; 779 resid = min(len, cmd->c_resid); 780 off = 0; 781 while (resid > 0) { 782 if (desc == sc->sc_idma_ndesc) 783 break; 784 len = min(sc->sc_config->idma_xferlen, resid); 785 dma[desc].dma_buf_size = htole32(len); 786 dma[desc].dma_buf_addr = htole32(paddr + off); 787 dma[desc].dma_config = htole32(SUNXI_MMC_IDMA_CONFIG_CH | 788 SUNXI_MMC_IDMA_CONFIG_OWN); 789 cmd->c_resid -= len; 790 resid -= len; 791 off += len; 792 if (desc == 0) { 793 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_FD); 794 } 795 if (cmd->c_resid == 0) { 796 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_LD); 797 dma[desc].dma_config |= htole32(SUNXI_MMC_IDMA_CONFIG_ER); 798 dma[desc].dma_next = 0; 799 } else { 800 dma[desc].dma_config |= 801 htole32(SUNXI_MMC_IDMA_CONFIG_DIC); 802 dma[desc].dma_next = htole32( 803 desc_paddr + ((desc+1) * 804 sizeof(struct sunxi_mmc_idma_descriptor))); 805 } 806 ++desc; 807 } 808 } 809 if (desc == sc->sc_idma_ndesc) { 810 aprint_error_dev(sc->sc_dev, 811 "not enough descriptors for %d byte transfer!\n", 812 cmd->c_datalen); 813 return EIO; 814 } 815 816 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 817 sc->sc_idma_size, BUS_DMASYNC_PREWRITE); 818 819 sc->sc_idma_idst = 0; 820 821 val = MMC_READ(sc, SUNXI_MMC_GCTRL); 822 val |= SUNXI_MMC_GCTRL_DMAEN; 823 val |= SUNXI_MMC_GCTRL_INTEN; 824 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 825 val |= SUNXI_MMC_GCTRL_DMARESET; 826 MMC_WRITE(sc, SUNXI_MMC_GCTRL, val); 827 MMC_WRITE(sc, SUNXI_MMC_DMAC, SUNXI_MMC_DMAC_SOFTRESET); 828 MMC_WRITE(sc, SUNXI_MMC_DMAC, 829 SUNXI_MMC_DMAC_IDMA_ON|SUNXI_MMC_DMAC_FIX_BURST); 830 val = MMC_READ(sc, SUNXI_MMC_IDIE); 831 val &= ~(SUNXI_MMC_IDST_RECEIVE_INT|SUNXI_MMC_IDST_TRANSMIT_INT); 832 if (cmd->c_flags & SCF_CMD_READ) 833 val |= SUNXI_MMC_IDST_RECEIVE_INT; 834 else 835 val |= SUNXI_MMC_IDST_TRANSMIT_INT; 836 MMC_WRITE(sc, SUNXI_MMC_IDIE, val); 837 MMC_WRITE(sc, SUNXI_MMC_DLBA, desc_paddr); 838 MMC_WRITE(sc, SUNXI_MMC_FTRGLEVEL, sc->sc_config->dma_ftrglevel); 839 840 return 0; 841 } 842 843 static void 844 sunxi_mmc_dma_complete(struct sunxi_mmc_softc *sc) 845 { 846 bus_dmamap_sync(sc->sc_dmat, sc->sc_idma_map, 0, 847 sc->sc_idma_size, BUS_DMASYNC_POSTWRITE); 848 } 849 850 static void 851 sunxi_mmc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 852 { 853 struct sunxi_mmc_softc *sc = sch; 854 uint32_t cmdval = SUNXI_MMC_CMD_START; 855 const bool poll = (cmd->c_flags & SCF_POLL) != 0; 856 int retry; 857 858 #ifdef SUNXI_MMC_DEBUG 859 aprint_normal_dev(sc->sc_dev, 860 "opcode %d flags 0x%x data %p datalen %d blklen %d poll %d\n", 861 cmd->c_opcode, cmd->c_flags, cmd->c_data, cmd->c_datalen, 862 cmd->c_blklen, poll); 863 #endif 864 865 mutex_enter(&sc->sc_intr_lock); 866 867 if (cmd->c_opcode == 0) 868 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; 869 if (cmd->c_flags & SCF_RSP_PRESENT) 870 cmdval |= SUNXI_MMC_CMD_RSP_EXP; 871 if (cmd->c_flags & SCF_RSP_136) 872 cmdval |= SUNXI_MMC_CMD_LONG_RSP; 873 if (cmd->c_flags & SCF_RSP_CRC) 874 cmdval |= SUNXI_MMC_CMD_CHECK_RSP_CRC; 875 876 if (cmd->c_datalen > 0) { 877 unsigned int nblks; 878 879 cmdval |= SUNXI_MMC_CMD_DATA_EXP | SUNXI_MMC_CMD_WAIT_PRE_OVER; 880 if (!ISSET(cmd->c_flags, SCF_CMD_READ)) { 881 cmdval |= SUNXI_MMC_CMD_WRITE; 882 } 883 884 nblks = cmd->c_datalen / cmd->c_blklen; 885 if (nblks == 0 || (cmd->c_datalen % cmd->c_blklen) != 0) 886 ++nblks; 887 888 if (nblks > 1) { 889 cmdval |= SUNXI_MMC_CMD_SEND_AUTO_STOP; 890 } 891 892 MMC_WRITE(sc, SUNXI_MMC_BLKSZ, cmd->c_blklen); 893 MMC_WRITE(sc, SUNXI_MMC_BYTECNT, nblks * cmd->c_blklen); 894 } 895 896 sc->sc_intr_rint = 0; 897 898 MMC_WRITE(sc, SUNXI_MMC_A12A, 899 (cmdval & SUNXI_MMC_CMD_SEND_AUTO_STOP) ? 0 : 0xffff); 900 901 MMC_WRITE(sc, SUNXI_MMC_ARG, cmd->c_arg); 902 903 #ifdef SUNXI_MMC_DEBUG 904 aprint_normal_dev(sc->sc_dev, "cmdval = %08x\n", cmdval); 905 #endif 906 907 if (cmd->c_datalen == 0) { 908 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 909 } else { 910 cmd->c_resid = cmd->c_datalen; 911 cmd->c_error = sunxi_mmc_dma_prepare(sc, cmd); 912 MMC_WRITE(sc, SUNXI_MMC_CMD, cmdval | cmd->c_opcode); 913 if (cmd->c_error == 0) { 914 const uint32_t idst_mask = 915 SUNXI_MMC_IDST_ERROR | SUNXI_MMC_IDST_COMPLETE; 916 retry = 10; 917 while ((sc->sc_idma_idst & idst_mask) == 0) { 918 if (retry-- == 0) { 919 cmd->c_error = ETIMEDOUT; 920 break; 921 } 922 cv_timedwait(&sc->sc_idst_cv, 923 &sc->sc_intr_lock, hz); 924 } 925 } 926 sunxi_mmc_dma_complete(sc); 927 if (sc->sc_idma_idst & SUNXI_MMC_IDST_ERROR) { 928 cmd->c_error = EIO; 929 } else if (!(sc->sc_idma_idst & SUNXI_MMC_IDST_COMPLETE)) { 930 cmd->c_error = ETIMEDOUT; 931 } 932 if (cmd->c_error) { 933 #ifdef SUNXI_MMC_DEBUG 934 aprint_error_dev(sc->sc_dev, 935 "xfer failed, error %d\n", cmd->c_error); 936 #endif 937 goto done; 938 } 939 } 940 941 cmd->c_error = sunxi_mmc_wait_rint(sc, 942 SUNXI_MMC_INT_ERROR|SUNXI_MMC_INT_CMD_DONE, hz * 10, poll); 943 if (cmd->c_error == 0 && (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 944 if (sc->sc_intr_rint & SUNXI_MMC_INT_RESP_TIMEOUT) { 945 cmd->c_error = ETIMEDOUT; 946 } else { 947 cmd->c_error = EIO; 948 } 949 } 950 if (cmd->c_error) { 951 #ifdef SUNXI_MMC_DEBUG 952 aprint_error_dev(sc->sc_dev, 953 "cmd failed, error %d\n", cmd->c_error); 954 #endif 955 goto done; 956 } 957 958 if (cmd->c_datalen > 0) { 959 cmd->c_error = sunxi_mmc_wait_rint(sc, 960 SUNXI_MMC_INT_ERROR| 961 SUNXI_MMC_INT_AUTO_CMD_DONE| 962 SUNXI_MMC_INT_DATA_OVER, 963 hz*10, poll); 964 if (cmd->c_error == 0 && 965 (sc->sc_intr_rint & SUNXI_MMC_INT_ERROR)) { 966 cmd->c_error = ETIMEDOUT; 967 } 968 if (cmd->c_error) { 969 #ifdef SUNXI_MMC_DEBUG 970 aprint_error_dev(sc->sc_dev, 971 "data timeout, rint = %08x\n", 972 sc->sc_intr_rint); 973 #endif 974 cmd->c_error = ETIMEDOUT; 975 goto done; 976 } 977 } 978 979 if (cmd->c_flags & SCF_RSP_PRESENT) { 980 if (cmd->c_flags & SCF_RSP_136) { 981 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 982 cmd->c_resp[1] = MMC_READ(sc, SUNXI_MMC_RESP1); 983 cmd->c_resp[2] = MMC_READ(sc, SUNXI_MMC_RESP2); 984 cmd->c_resp[3] = MMC_READ(sc, SUNXI_MMC_RESP3); 985 if (cmd->c_flags & SCF_RSP_CRC) { 986 cmd->c_resp[0] = (cmd->c_resp[0] >> 8) | 987 (cmd->c_resp[1] << 24); 988 cmd->c_resp[1] = (cmd->c_resp[1] >> 8) | 989 (cmd->c_resp[2] << 24); 990 cmd->c_resp[2] = (cmd->c_resp[2] >> 8) | 991 (cmd->c_resp[3] << 24); 992 cmd->c_resp[3] = (cmd->c_resp[3] >> 8); 993 } 994 } else { 995 cmd->c_resp[0] = MMC_READ(sc, SUNXI_MMC_RESP0); 996 } 997 } 998 999 done: 1000 cmd->c_flags |= SCF_ITSDONE; 1001 mutex_exit(&sc->sc_intr_lock); 1002 1003 if (cmd->c_error) { 1004 #ifdef SUNXI_MMC_DEBUG 1005 aprint_error_dev(sc->sc_dev, "i/o error %d\n", cmd->c_error); 1006 #endif 1007 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1008 MMC_READ(sc, SUNXI_MMC_GCTRL) | 1009 SUNXI_MMC_GCTRL_DMARESET | SUNXI_MMC_GCTRL_FIFORESET); 1010 for (retry = 0; retry < 1000; retry++) { 1011 if (!(MMC_READ(sc, SUNXI_MMC_GCTRL) & SUNXI_MMC_GCTRL_RESET)) 1012 break; 1013 delay(10); 1014 } 1015 sunxi_mmc_update_clock(sc); 1016 } 1017 1018 MMC_WRITE(sc, SUNXI_MMC_GCTRL, 1019 MMC_READ(sc, SUNXI_MMC_GCTRL) | SUNXI_MMC_GCTRL_FIFORESET); 1020 } 1021 1022 static void 1023 sunxi_mmc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable) 1024 { 1025 } 1026 1027 static void 1028 sunxi_mmc_card_intr_ack(sdmmc_chipset_handle_t sch) 1029 { 1030 } 1031
Indexes created Tue Sep 30 11:09:46 GMT 2025