sunxi_musb.c revision 1.2
1 /* $NetBSD: sunxi_musb.c,v 1.2 2017/10/29 16:02:46 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_motg.h" 30 #ifdef MOTG_ALLWINNER 31 # error Do not define MOTG_ALLWINNER when using this driver 32 #endif 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: sunxi_musb.c,v 1.2 2017/10/29 16:02:46 jmcneill Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/device.h> 40 #include <sys/intr.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/pool.h> 44 45 #include <dev/usb/usb.h> 46 #include <dev/usb/usbdi.h> 47 #include <dev/usb/usbdivar.h> 48 #include <dev/usb/motgvar.h> 49 #include <dev/usb/motgreg.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 #include <machine/bus_defs.h> 54 55 #define MUSB2_REG_AWIN_VEND0 0x43 56 57 static int sunxi_musb_match(device_t, cfdata_t, void *); 58 static void sunxi_musb_attach(device_t, device_t, void *); 59 60 struct sunxi_musb_softc { 61 struct motg_softc sc_otg; 62 struct bus_space sc_bs; 63 }; 64 65 CFATTACH_DECL_NEW(sunxi_musb, sizeof(struct sunxi_musb_softc), 66 sunxi_musb_match, sunxi_musb_attach, NULL, NULL); 67 68 static const struct of_compat_data compat_data[] = { 69 { "allwinner,sun4i-a10-musb", 5 }, 70 { "allwinner,sun6i-a13-musb", 5 }, 71 { "allwinner,sun8i-h3-musb", 4 }, 72 { "allwinner,sun8i-a33-musb", 5 }, 73 { NULL } 74 }; 75 76 #define REMAPFLAG 0x8000 77 #define REGDECL(a, b) [(a)] = ((b) | REMAPFLAG) 78 79 /* Allwinner USB DRD register mappings */ 80 static const uint16_t sunxi_musb_regmap[] = { 81 REGDECL(MUSB2_REG_EPFIFO(0), 0x0000), 82 REGDECL(MUSB2_REG_EPFIFO(1), 0x0004), 83 REGDECL(MUSB2_REG_EPFIFO(2), 0x0008), 84 REGDECL(MUSB2_REG_EPFIFO(3), 0x000c), 85 REGDECL(MUSB2_REG_EPFIFO(4), 0x0010), 86 REGDECL(MUSB2_REG_EPFIFO(5), 0x0014), 87 REGDECL(MUSB2_REG_POWER, 0x0040), 88 REGDECL(MUSB2_REG_DEVCTL, 0x0041), 89 REGDECL(MUSB2_REG_EPINDEX, 0x0042), 90 REGDECL(MUSB2_REG_AWIN_VEND0, 0x0043), 91 REGDECL(MUSB2_REG_INTTX, 0x0044), 92 REGDECL(MUSB2_REG_INTRX, 0x0046), 93 REGDECL(MUSB2_REG_INTTXE, 0x0048), 94 REGDECL(MUSB2_REG_INTRXE, 0x004a), 95 REGDECL(MUSB2_REG_INTUSB, 0x004c), 96 REGDECL(MUSB2_REG_INTUSBE, 0x0050), 97 REGDECL(MUSB2_REG_FRAME, 0x0054), 98 REGDECL(MUSB2_REG_TESTMODE, 0x007c), 99 REGDECL(MUSB2_REG_TXMAXP, 0x0080), 100 REGDECL(MUSB2_REG_TXCSRL, 0x0082), 101 REGDECL(MUSB2_REG_TXCSRH, 0x0083), 102 REGDECL(MUSB2_REG_RXMAXP, 0x0084), 103 REGDECL(MUSB2_REG_RXCSRL, 0x0086), 104 REGDECL(MUSB2_REG_RXCSRH, 0x0087), 105 REGDECL(MUSB2_REG_RXCOUNT, 0x0088), 106 REGDECL(MUSB2_REG_TXTI, 0x008c), 107 REGDECL(MUSB2_REG_TXNAKLIMIT, 0x008d), 108 REGDECL(MUSB2_REG_RXNAKLIMIT, 0x008d), 109 REGDECL(MUSB2_REG_RXTI, 0x008e), 110 REGDECL(MUSB2_REG_TXFIFOSZ, 0x0090), 111 REGDECL(MUSB2_REG_TXFIFOADD, 0x0092), 112 REGDECL(MUSB2_REG_RXFIFOSZ, 0x0094), 113 REGDECL(MUSB2_REG_RXFIFOADD, 0x0096), 114 REGDECL(MUSB2_REG_FADDR, 0x0098), 115 REGDECL(MUSB2_REG_TXFADDR(0), 0x0098), 116 REGDECL(MUSB2_REG_TXHADDR(0), 0x009a), 117 REGDECL(MUSB2_REG_TXHUBPORT(0), 0x009b), 118 REGDECL(MUSB2_REG_RXFADDR(0), 0x009c), 119 REGDECL(MUSB2_REG_RXHADDR(0), 0x009e), 120 REGDECL(MUSB2_REG_RXHUBPORT(0), 0x009f), 121 REGDECL(MUSB2_REG_TXFADDR(1), 0x0098), 122 REGDECL(MUSB2_REG_TXHADDR(1), 0x009a), 123 REGDECL(MUSB2_REG_TXHUBPORT(1), 0x009b), 124 REGDECL(MUSB2_REG_RXFADDR(1), 0x009c), 125 REGDECL(MUSB2_REG_RXHADDR(1), 0x009e), 126 REGDECL(MUSB2_REG_RXHUBPORT(1), 0x009f), 127 REGDECL(MUSB2_REG_TXFADDR(2), 0x0098), 128 REGDECL(MUSB2_REG_TXHADDR(2), 0x009a), 129 REGDECL(MUSB2_REG_TXHUBPORT(2), 0x009b), 130 REGDECL(MUSB2_REG_RXFADDR(2), 0x009c), 131 REGDECL(MUSB2_REG_RXHADDR(2), 0x009e), 132 REGDECL(MUSB2_REG_RXHUBPORT(2), 0x009f), 133 REGDECL(MUSB2_REG_TXFADDR(3), 0x0098), 134 REGDECL(MUSB2_REG_TXHADDR(3), 0x009a), 135 REGDECL(MUSB2_REG_TXHUBPORT(3), 0x009b), 136 REGDECL(MUSB2_REG_RXFADDR(3), 0x009c), 137 REGDECL(MUSB2_REG_RXHADDR(3), 0x009e), 138 REGDECL(MUSB2_REG_RXHUBPORT(3), 0x009f), 139 REGDECL(MUSB2_REG_TXFADDR(4), 0x0098), 140 REGDECL(MUSB2_REG_TXHADDR(4), 0x009a), 141 REGDECL(MUSB2_REG_TXHUBPORT(4), 0x009b), 142 REGDECL(MUSB2_REG_RXFADDR(4), 0x009c), 143 REGDECL(MUSB2_REG_RXHADDR(4), 0x009e), 144 REGDECL(MUSB2_REG_RXHUBPORT(4), 0x009f), 145 REGDECL(MUSB2_REG_TXFADDR(5), 0x0098), 146 REGDECL(MUSB2_REG_TXHADDR(5), 0x009a), 147 REGDECL(MUSB2_REG_TXHUBPORT(5), 0x009b), 148 REGDECL(MUSB2_REG_RXFADDR(5), 0x009c), 149 REGDECL(MUSB2_REG_RXHADDR(5), 0x009e), 150 REGDECL(MUSB2_REG_RXHUBPORT(5), 0x009f), 151 REGDECL(MUSB2_REG_CONFDATA, 0x00c0), 152 }; 153 154 static bus_size_t 155 sunxi_musb_reg(bus_size_t o) 156 { 157 bus_size_t v; 158 159 if (o >= __arraycount(sunxi_musb_regmap)) 160 return o; 161 162 v = sunxi_musb_regmap[o]; 163 KASSERTMSG((v & REMAPFLAG) != 0, "%s: reg %#lx not in regmap", 164 __func__, o); 165 166 return v & ~REMAPFLAG; 167 } 168 169 static int 170 sunxi_musb_filt(bus_size_t o) 171 { 172 switch (o) { 173 case MUSB2_REG_MISC: 174 case MUSB2_REG_RXDBDIS: 175 case MUSB2_REG_TXDBDIS: 176 return 1; 177 default: 178 return 0; 179 } 180 } 181 182 static uint8_t 183 sunxi_musb_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o) 184 { 185 const struct bus_space *bs = t; 186 const struct bus_space *bs_parent = bs->bs_cookie; 187 188 switch (o) { 189 case MUSB2_REG_HWVERS: 190 return 0; /* no known equivalent */ 191 } 192 193 return bus_space_read_1(bs_parent, h, sunxi_musb_reg(o)); 194 } 195 196 static uint16_t 197 sunxi_musb_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o) 198 { 199 const struct bus_space *bs = t; 200 const struct bus_space *bs_parent = bs->bs_cookie; 201 202 return bus_space_read_2(bs_parent, h, sunxi_musb_reg(o)); 203 } 204 205 static void 206 sunxi_musb_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o, 207 uint8_t v) 208 { 209 const struct bus_space *bs = t; 210 const struct bus_space *bs_parent = bs->bs_cookie; 211 212 if (sunxi_musb_filt(o) != 0) 213 return; 214 215 bus_space_write_1(bs_parent, h, sunxi_musb_reg(o), v); 216 } 217 218 static void 219 sunxi_musb_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, 220 uint16_t v) 221 { 222 const struct bus_space *bs = t; 223 const struct bus_space *bs_parent = bs->bs_cookie; 224 225 if (sunxi_musb_filt(o) != 0) 226 return; 227 228 bus_space_write_2(bs_parent, h, sunxi_musb_reg(o), v); 229 } 230 231 static void 232 sunxi_musb_bs_rm_1(void *t, bus_space_handle_t h, bus_size_t o, 233 uint8_t *d, bus_size_t c) 234 { 235 const struct bus_space *bs = t; 236 const struct bus_space *bs_parent = bs->bs_cookie; 237 238 bus_space_read_multi_1(bs_parent, h, sunxi_musb_reg(o), d, c); 239 } 240 241 static void 242 sunxi_musb_bs_rm_4(void *t, bus_space_handle_t h, bus_size_t o, 243 uint32_t *d, bus_size_t c) 244 { 245 const struct bus_space *bs = t; 246 const struct bus_space *bs_parent = bs->bs_cookie; 247 248 bus_space_read_multi_4(bs_parent, h, sunxi_musb_reg(o), d, c); 249 } 250 251 static void 252 sunxi_musb_bs_wm_1(void *t, bus_space_handle_t h, bus_size_t o, 253 const uint8_t *d, bus_size_t c) 254 { 255 const struct bus_space *bs = t; 256 const struct bus_space *bs_parent = bs->bs_cookie; 257 258 if (sunxi_musb_filt(o) != 0) 259 return; 260 261 bus_space_write_multi_1(bs_parent, h, sunxi_musb_reg(o), d, c); 262 } 263 264 static void 265 sunxi_musb_bs_wm_4(void *t, bus_space_handle_t h, bus_size_t o, 266 const uint32_t *d, bus_size_t c) 267 { 268 const struct bus_space *bs = t; 269 const struct bus_space *bs_parent = bs->bs_cookie; 270 271 if (sunxi_musb_filt(o) != 0) 272 return; 273 274 bus_space_write_multi_4(bs_parent, h, sunxi_musb_reg(o), d, c); 275 } 276 277 static void 278 sunxi_musb_bs_barrier(void *t, bus_space_handle_t h, bus_size_t o, 279 bus_size_t l, int f) 280 { 281 const struct bus_space *bs = t; 282 const struct bus_space *bs_parent = bs->bs_cookie; 283 284 bus_space_barrier(bs_parent, h, o, l, f); 285 } 286 287 static int 288 sunxi_musb_intr(void *priv) 289 { 290 struct motg_softc * const sc = priv; 291 uint16_t inttx, intrx; 292 uint8_t intusb; 293 294 mutex_enter(&sc->sc_intr_lock); 295 296 intusb = bus_space_read_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTUSB); 297 inttx = bus_space_read_2(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTTX); 298 intrx = bus_space_read_2(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTRX); 299 if (!intusb && !inttx && !intrx) { 300 mutex_exit(&sc->sc_intr_lock); 301 return 0; 302 } 303 304 if (intusb) 305 bus_space_write_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTUSB, intusb); 306 if (inttx) 307 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTTX, inttx); 308 if (intrx) 309 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTRX, intrx); 310 311 motg_intr(sc, intrx, inttx, intusb); 312 313 mutex_exit(&sc->sc_intr_lock); 314 315 return 1; 316 } 317 318 static void 319 sunxi_musb_poll(void *priv) 320 { 321 sunxi_musb_intr(priv); 322 } 323 324 static int 325 sunxi_musb_match(device_t parent, cfdata_t cf, void *aux) 326 { 327 struct fdt_attach_args * const faa = aux; 328 329 return of_match_compat_data(faa->faa_phandle, compat_data); 330 } 331 332 static void 333 sunxi_musb_attach(device_t parent, device_t self, void *aux) 334 { 335 struct sunxi_musb_softc * const msc = device_private(self); 336 struct motg_softc * const sc = &msc->sc_otg; 337 struct fdt_attach_args * const faa = aux; 338 const int phandle = faa->faa_phandle; 339 struct fdtbus_reset *rst; 340 struct fdtbus_phy *phy; 341 struct clk *clk; 342 char intrstr[128]; 343 const char *dr_mode; 344 bus_addr_t addr; 345 bus_size_t size; 346 void *ih; 347 u_int n; 348 349 /* Only "host" mode is supported */ 350 dr_mode = fdtbus_get_string(phandle, "dr_mode"); 351 if (dr_mode == NULL || strcmp(dr_mode, "host") != 0) { 352 aprint_normal(": '%s' mode not supported\n", dr_mode); 353 return; 354 } 355 356 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 357 aprint_error(": couldn't get registers\n"); 358 return; 359 } 360 361 /* Enable clocks */ 362 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) 363 if (clk_enable(clk) != 0) { 364 aprint_error(": couldn't enable clock #%d\n", n); 365 return; 366 } 367 /* De-assert resets */ 368 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) 369 if (fdtbus_reset_deassert(rst) != 0) { 370 aprint_error(": couldn't de-assert reset #%d\n", n); 371 return; 372 } 373 374 /* Enable optional phy */ 375 phy = fdtbus_phy_get(phandle, "usb"); 376 if (phy && fdtbus_phy_enable(phy, true) != 0) { 377 aprint_error(": couldn't enable phy\n"); 378 return; 379 } 380 381 /* Create custom bus space tag for remapping registers */ 382 msc->sc_bs.bs_cookie = faa->faa_bst; 383 msc->sc_bs.bs_r_1 = sunxi_musb_bs_r_1; 384 msc->sc_bs.bs_r_2 = sunxi_musb_bs_r_2; 385 msc->sc_bs.bs_w_1 = sunxi_musb_bs_w_1; 386 msc->sc_bs.bs_w_2 = sunxi_musb_bs_w_2; 387 msc->sc_bs.bs_rm_1 = sunxi_musb_bs_rm_1; 388 msc->sc_bs.bs_rm_4 = sunxi_musb_bs_rm_4; 389 msc->sc_bs.bs_wm_1 = sunxi_musb_bs_wm_1; 390 msc->sc_bs.bs_wm_4 = sunxi_musb_bs_wm_4; 391 msc->sc_bs.bs_barrier = sunxi_musb_bs_barrier; 392 393 sc->sc_dev = self; 394 sc->sc_bus.ub_hcpriv = sc; 395 sc->sc_bus.ub_dmatag = faa->faa_dmat; 396 strlcpy(sc->sc_vendor, "Allwinner", sizeof(sc->sc_vendor)); 397 sc->sc_size = size; 398 sc->sc_iot = &msc->sc_bs; 399 if (bus_space_map(faa->faa_bst, addr, size, 0, &sc->sc_ioh) != 0) { 400 aprint_error(": couldn't map registers\n"); 401 return; 402 } 403 sc->sc_intr_poll = sunxi_musb_poll; 404 sc->sc_intr_poll_arg = sc; 405 sc->sc_mode = MOTG_MODE_HOST; 406 sc->sc_ep_max = of_search_compatible(phandle, compat_data)->data; 407 sc->sc_ep_fifosize = 512; 408 409 aprint_naive("\n"); 410 aprint_normal(": USB OTG\n"); 411 412 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 413 aprint_error_dev(self, "failed to decode interrupt\n"); 414 return; 415 } 416 417 ih = fdtbus_intr_establish(phandle, 0, IPL_USB, FDT_INTR_MPSAFE, 418 sunxi_musb_intr, sc); 419 if (ih == NULL) { 420 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 421 intrstr); 422 return; 423 } 424 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 425 426 bus_space_write_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_AWIN_VEND0, 0); 427 428 motg_init(sc); 429 } 430
Indexes created Tue Sep 30 20:09:53 GMT 2025