sunxi_musb.c revision 1.7
1 /* $NetBSD: sunxi_musb.c,v 1.7 2021/01/18 02:35:49 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_musb.c,v 1.7 2021/01/18 02:35:49 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/pool.h> 39 40 #include <dev/usb/usb.h> 41 #include <dev/usb/usbdi.h> 42 #include <dev/usb/usbdivar.h> 43 #include <dev/usb/motgvar.h> 44 #include <dev/usb/motgreg.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #include <machine/bus_defs.h> 49 50 #define MUSB2_REG_AWIN_VEND0 0x43 51 52 static int sunxi_musb_match(device_t, cfdata_t, void *); 53 static void sunxi_musb_attach(device_t, device_t, void *); 54 55 struct sunxi_musb_softc { 56 struct motg_softc sc_otg; 57 struct bus_space sc_bs; 58 }; 59 60 CFATTACH_DECL_NEW(sunxi_musb, sizeof(struct sunxi_musb_softc), 61 sunxi_musb_match, sunxi_musb_attach, NULL, NULL); 62 63 static const struct device_compatible_entry compat_data[] = { 64 { .compat = "allwinner,sun4i-a10-musb", .value = 5 }, 65 { .compat = "allwinner,sun6i-a13-musb", .value = 5 }, 66 { .compat = "allwinner,sun8i-h3-musb", .value = 4 }, 67 { .compat = "allwinner,sun8i-a33-musb", .value = 5 }, 68 69 { 0 } 70 }; 71 72 #define REMAPFLAG 0x8000 73 #define REGDECL(a, b) [(a)] = ((b) | REMAPFLAG) 74 75 /* Allwinner USB DRD register mappings */ 76 static const uint16_t sunxi_musb_regmap[] = { 77 REGDECL(MUSB2_REG_EPFIFO(0), 0x0000), 78 REGDECL(MUSB2_REG_EPFIFO(1), 0x0004), 79 REGDECL(MUSB2_REG_EPFIFO(2), 0x0008), 80 REGDECL(MUSB2_REG_EPFIFO(3), 0x000c), 81 REGDECL(MUSB2_REG_EPFIFO(4), 0x0010), 82 REGDECL(MUSB2_REG_EPFIFO(5), 0x0014), 83 REGDECL(MUSB2_REG_POWER, 0x0040), 84 REGDECL(MUSB2_REG_DEVCTL, 0x0041), 85 REGDECL(MUSB2_REG_EPINDEX, 0x0042), 86 REGDECL(MUSB2_REG_AWIN_VEND0, 0x0043), 87 REGDECL(MUSB2_REG_INTTX, 0x0044), 88 REGDECL(MUSB2_REG_INTRX, 0x0046), 89 REGDECL(MUSB2_REG_INTTXE, 0x0048), 90 REGDECL(MUSB2_REG_INTRXE, 0x004a), 91 REGDECL(MUSB2_REG_INTUSB, 0x004c), 92 REGDECL(MUSB2_REG_INTUSBE, 0x0050), 93 REGDECL(MUSB2_REG_FRAME, 0x0054), 94 REGDECL(MUSB2_REG_TESTMODE, 0x007c), 95 REGDECL(MUSB2_REG_TXMAXP, 0x0080), 96 REGDECL(MUSB2_REG_TXCSRL, 0x0082), 97 REGDECL(MUSB2_REG_TXCSRH, 0x0083), 98 REGDECL(MUSB2_REG_RXMAXP, 0x0084), 99 REGDECL(MUSB2_REG_RXCSRL, 0x0086), 100 REGDECL(MUSB2_REG_RXCSRH, 0x0087), 101 REGDECL(MUSB2_REG_RXCOUNT, 0x0088), 102 REGDECL(MUSB2_REG_TXTI, 0x008c), 103 REGDECL(MUSB2_REG_TXNAKLIMIT, 0x008d), 104 REGDECL(MUSB2_REG_RXNAKLIMIT, 0x008d), 105 REGDECL(MUSB2_REG_RXTI, 0x008e), 106 REGDECL(MUSB2_REG_TXFIFOSZ, 0x0090), 107 REGDECL(MUSB2_REG_TXFIFOADD, 0x0092), 108 REGDECL(MUSB2_REG_RXFIFOSZ, 0x0094), 109 REGDECL(MUSB2_REG_RXFIFOADD, 0x0096), 110 REGDECL(MUSB2_REG_FADDR, 0x0098), 111 REGDECL(MUSB2_REG_TXFADDR(0), 0x0098), 112 REGDECL(MUSB2_REG_TXHADDR(0), 0x009a), 113 REGDECL(MUSB2_REG_TXHUBPORT(0), 0x009b), 114 REGDECL(MUSB2_REG_RXFADDR(0), 0x009c), 115 REGDECL(MUSB2_REG_RXHADDR(0), 0x009e), 116 REGDECL(MUSB2_REG_RXHUBPORT(0), 0x009f), 117 REGDECL(MUSB2_REG_TXFADDR(1), 0x0098), 118 REGDECL(MUSB2_REG_TXHADDR(1), 0x009a), 119 REGDECL(MUSB2_REG_TXHUBPORT(1), 0x009b), 120 REGDECL(MUSB2_REG_RXFADDR(1), 0x009c), 121 REGDECL(MUSB2_REG_RXHADDR(1), 0x009e), 122 REGDECL(MUSB2_REG_RXHUBPORT(1), 0x009f), 123 REGDECL(MUSB2_REG_TXFADDR(2), 0x0098), 124 REGDECL(MUSB2_REG_TXHADDR(2), 0x009a), 125 REGDECL(MUSB2_REG_TXHUBPORT(2), 0x009b), 126 REGDECL(MUSB2_REG_RXFADDR(2), 0x009c), 127 REGDECL(MUSB2_REG_RXHADDR(2), 0x009e), 128 REGDECL(MUSB2_REG_RXHUBPORT(2), 0x009f), 129 REGDECL(MUSB2_REG_TXFADDR(3), 0x0098), 130 REGDECL(MUSB2_REG_TXHADDR(3), 0x009a), 131 REGDECL(MUSB2_REG_TXHUBPORT(3), 0x009b), 132 REGDECL(MUSB2_REG_RXFADDR(3), 0x009c), 133 REGDECL(MUSB2_REG_RXHADDR(3), 0x009e), 134 REGDECL(MUSB2_REG_RXHUBPORT(3), 0x009f), 135 REGDECL(MUSB2_REG_TXFADDR(4), 0x0098), 136 REGDECL(MUSB2_REG_TXHADDR(4), 0x009a), 137 REGDECL(MUSB2_REG_TXHUBPORT(4), 0x009b), 138 REGDECL(MUSB2_REG_RXFADDR(4), 0x009c), 139 REGDECL(MUSB2_REG_RXHADDR(4), 0x009e), 140 REGDECL(MUSB2_REG_RXHUBPORT(4), 0x009f), 141 REGDECL(MUSB2_REG_TXFADDR(5), 0x0098), 142 REGDECL(MUSB2_REG_TXHADDR(5), 0x009a), 143 REGDECL(MUSB2_REG_TXHUBPORT(5), 0x009b), 144 REGDECL(MUSB2_REG_RXFADDR(5), 0x009c), 145 REGDECL(MUSB2_REG_RXHADDR(5), 0x009e), 146 REGDECL(MUSB2_REG_RXHUBPORT(5), 0x009f), 147 REGDECL(MUSB2_REG_CONFDATA, 0x00c0), 148 }; 149 150 static bus_size_t 151 sunxi_musb_reg(bus_size_t o) 152 { 153 bus_size_t v; 154 155 if (o >= __arraycount(sunxi_musb_regmap)) 156 return o; 157 158 v = sunxi_musb_regmap[o]; 159 KASSERTMSG((v & REMAPFLAG) != 0, "%s: reg %#lx not in regmap", 160 __func__, o); 161 162 return v & ~REMAPFLAG; 163 } 164 165 static int 166 sunxi_musb_filt(bus_size_t o) 167 { 168 switch (o) { 169 case MUSB2_REG_MISC: 170 case MUSB2_REG_RXDBDIS: 171 case MUSB2_REG_TXDBDIS: 172 return 1; 173 default: 174 return 0; 175 } 176 } 177 178 static uint8_t 179 sunxi_musb_bs_r_1(void *t, bus_space_handle_t h, bus_size_t o) 180 { 181 switch (o) { 182 case MUSB2_REG_HWVERS: 183 return 0; /* no known equivalent */ 184 } 185 186 return bus_space_read_1((bus_space_tag_t)t, h, sunxi_musb_reg(o)); 187 } 188 189 static uint16_t 190 sunxi_musb_bs_r_2(void *t, bus_space_handle_t h, bus_size_t o) 191 { 192 return bus_space_read_2((bus_space_tag_t)t, h, sunxi_musb_reg(o)); 193 } 194 195 static void 196 sunxi_musb_bs_w_1(void *t, bus_space_handle_t h, bus_size_t o, 197 uint8_t v) 198 { 199 if (sunxi_musb_filt(o) != 0) 200 return; 201 202 bus_space_write_1((bus_space_tag_t)t, h, sunxi_musb_reg(o), v); 203 } 204 205 static void 206 sunxi_musb_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, 207 uint16_t v) 208 { 209 if (sunxi_musb_filt(o) != 0) 210 return; 211 212 bus_space_write_2((bus_space_tag_t)t, h, sunxi_musb_reg(o), v); 213 } 214 215 static void 216 sunxi_musb_bs_rm_1(void *t, bus_space_handle_t h, bus_size_t o, 217 uint8_t *d, bus_size_t c) 218 { 219 bus_space_read_multi_1((bus_space_tag_t)t, h, sunxi_musb_reg(o), d, c); 220 } 221 222 static void 223 sunxi_musb_bs_rm_4(void *t, bus_space_handle_t h, bus_size_t o, 224 uint32_t *d, bus_size_t c) 225 { 226 bus_space_read_multi_4((bus_space_tag_t)t, h, sunxi_musb_reg(o), d, c); 227 } 228 229 static void 230 sunxi_musb_bs_wm_1(void *t, bus_space_handle_t h, bus_size_t o, 231 const uint8_t *d, bus_size_t c) 232 { 233 if (sunxi_musb_filt(o) != 0) 234 return; 235 236 bus_space_write_multi_1((bus_space_tag_t)t, h, sunxi_musb_reg(o), d, c); 237 } 238 239 static void 240 sunxi_musb_bs_wm_4(void *t, bus_space_handle_t h, bus_size_t o, 241 const uint32_t *d, bus_size_t c) 242 { 243 if (sunxi_musb_filt(o) != 0) 244 return; 245 246 bus_space_write_multi_4((bus_space_tag_t)t, h, sunxi_musb_reg(o), d, c); 247 } 248 249 static void 250 sunxi_musb_bs_barrier(void *t, bus_space_handle_t h, bus_size_t o, 251 bus_size_t l, int f) 252 { 253 bus_space_barrier((bus_space_tag_t)t, h, o, l, f); 254 } 255 256 static int 257 sunxi_musb_intr(void *priv) 258 { 259 struct motg_softc * const sc = priv; 260 uint16_t inttx, intrx; 261 uint8_t intusb; 262 263 mutex_enter(&sc->sc_intr_lock); 264 265 intusb = bus_space_read_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTUSB); 266 inttx = bus_space_read_2(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTTX); 267 intrx = bus_space_read_2(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTRX); 268 if (!intusb && !inttx && !intrx) { 269 mutex_exit(&sc->sc_intr_lock); 270 return 0; 271 } 272 273 if (intusb) 274 bus_space_write_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTUSB, intusb); 275 if (inttx) 276 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTTX, inttx); 277 if (intrx) 278 bus_space_write_2(sc->sc_iot, sc->sc_ioh, MUSB2_REG_INTRX, intrx); 279 280 motg_intr(sc, intrx, inttx, intusb); 281 282 mutex_exit(&sc->sc_intr_lock); 283 284 return 1; 285 } 286 287 static void 288 sunxi_musb_poll(void *priv) 289 { 290 sunxi_musb_intr(priv); 291 } 292 293 static int 294 sunxi_musb_match(device_t parent, cfdata_t cf, void *aux) 295 { 296 struct fdt_attach_args * const faa = aux; 297 298 return of_match_compat_data(faa->faa_phandle, compat_data); 299 } 300 301 static void 302 sunxi_musb_attach(device_t parent, device_t self, void *aux) 303 { 304 struct sunxi_musb_softc * const msc = device_private(self); 305 struct motg_softc * const sc = &msc->sc_otg; 306 struct fdt_attach_args * const faa = aux; 307 const int phandle = faa->faa_phandle; 308 struct fdtbus_reset *rst; 309 struct fdtbus_phy *phy; 310 struct clk *clk; 311 char intrstr[128]; 312 const char *dr_mode; 313 bus_addr_t addr; 314 bus_size_t size; 315 void *ih; 316 u_int n; 317 318 /* Only "host" mode is supported */ 319 dr_mode = fdtbus_get_string(phandle, "dr_mode"); 320 if (dr_mode == NULL || strcmp(dr_mode, "host") != 0) { 321 aprint_normal(": '%s' mode not supported\n", dr_mode); 322 return; 323 } 324 325 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 326 aprint_error(": couldn't get registers\n"); 327 return; 328 } 329 330 /* Enable clocks */ 331 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) 332 if (clk_enable(clk) != 0) { 333 aprint_error(": couldn't enable clock #%d\n", n); 334 return; 335 } 336 /* De-assert resets */ 337 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) 338 if (fdtbus_reset_deassert(rst) != 0) { 339 aprint_error(": couldn't de-assert reset #%d\n", n); 340 return; 341 } 342 343 /* Enable optional phy */ 344 phy = fdtbus_phy_get(phandle, "usb"); 345 if (phy && fdtbus_phy_enable(phy, true) != 0) { 346 aprint_error(": couldn't enable phy\n"); 347 return; 348 } 349 350 /* Create custom bus space tag for remapping registers */ 351 msc->sc_bs.bs_cookie = faa->faa_bst; 352 msc->sc_bs.bs_r_1 = sunxi_musb_bs_r_1; 353 msc->sc_bs.bs_r_2 = sunxi_musb_bs_r_2; 354 msc->sc_bs.bs_w_1 = sunxi_musb_bs_w_1; 355 msc->sc_bs.bs_w_2 = sunxi_musb_bs_w_2; 356 msc->sc_bs.bs_rm_1 = sunxi_musb_bs_rm_1; 357 msc->sc_bs.bs_rm_4 = sunxi_musb_bs_rm_4; 358 msc->sc_bs.bs_wm_1 = sunxi_musb_bs_wm_1; 359 msc->sc_bs.bs_wm_4 = sunxi_musb_bs_wm_4; 360 msc->sc_bs.bs_barrier = sunxi_musb_bs_barrier; 361 362 sc->sc_dev = self; 363 sc->sc_bus.ub_hcpriv = sc; 364 sc->sc_bus.ub_dmatag = faa->faa_dmat; 365 sc->sc_size = size; 366 sc->sc_iot = &msc->sc_bs; 367 if (bus_space_map(faa->faa_bst, addr, size, 0, &sc->sc_ioh) != 0) { 368 aprint_error(": couldn't map registers\n"); 369 return; 370 } 371 sc->sc_intr_poll = sunxi_musb_poll; 372 sc->sc_intr_poll_arg = sc; 373 sc->sc_mode = MOTG_MODE_HOST; 374 sc->sc_ep_max = of_search_compatible(phandle, compat_data)->value; 375 sc->sc_ep_fifosize = 512; 376 377 aprint_naive("\n"); 378 aprint_normal(": USB OTG\n"); 379 380 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 381 aprint_error_dev(self, "failed to decode interrupt\n"); 382 return; 383 } 384 385 ih = fdtbus_intr_establish_xname(phandle, 0, IPL_USB, FDT_INTR_MPSAFE, 386 sunxi_musb_intr, sc, device_xname(self)); 387 if (ih == NULL) { 388 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 389 intrstr); 390 return; 391 } 392 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 393 394 bus_space_write_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_AWIN_VEND0, 0); 395 396 motg_init(sc); 397 } 398
Indexes created Tue Sep 30 20:09:53 GMT 2025