sunxi_platform.c revision 1.37 1 1.37 mrg /* $NetBSD: sunxi_platform.c,v 1.37 2019/06/17 05:27:01 mrg Exp $ */
2 1.1 jmcneill
3 1.1 jmcneill /*-
4 1.1 jmcneill * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca>
5 1.1 jmcneill * All rights reserved.
6 1.1 jmcneill *
7 1.1 jmcneill * Redistribution and use in source and binary forms, with or without
8 1.1 jmcneill * modification, are permitted provided that the following conditions
9 1.1 jmcneill * are met:
10 1.1 jmcneill * 1. Redistributions of source code must retain the above copyright
11 1.1 jmcneill * notice, this list of conditions and the following disclaimer.
12 1.1 jmcneill * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 jmcneill * notice, this list of conditions and the following disclaimer in the
14 1.1 jmcneill * documentation and/or other materials provided with the distribution.
15 1.1 jmcneill *
16 1.1 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.1 jmcneill * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.1 jmcneill * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.1 jmcneill * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.1 jmcneill * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 1.1 jmcneill * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 1.1 jmcneill * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 1.1 jmcneill * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 1.1 jmcneill * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.1 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.1 jmcneill * SUCH DAMAGE.
27 1.1 jmcneill */
28 1.1 jmcneill
29 1.1 jmcneill #include "opt_soc.h"
30 1.1 jmcneill #include "opt_multiprocessor.h"
31 1.28 skrll #include "opt_console.h"
32 1.1 jmcneill
33 1.1 jmcneill #include <sys/cdefs.h>
34 1.37 mrg __KERNEL_RCSID(0, "$NetBSD: sunxi_platform.c,v 1.37 2019/06/17 05:27:01 mrg Exp $");
35 1.1 jmcneill
36 1.1 jmcneill #include <sys/param.h>
37 1.1 jmcneill #include <sys/bus.h>
38 1.1 jmcneill #include <sys/cpu.h>
39 1.1 jmcneill #include <sys/device.h>
40 1.1 jmcneill #include <sys/termios.h>
41 1.1 jmcneill
42 1.1 jmcneill #include <dev/fdt/fdtvar.h>
43 1.1 jmcneill #include <arm/fdt/arm_fdtvar.h>
44 1.1 jmcneill
45 1.1 jmcneill #include <uvm/uvm_extern.h>
46 1.1 jmcneill
47 1.1 jmcneill #include <machine/bootconfig.h>
48 1.1 jmcneill #include <arm/cpufunc.h>
49 1.1 jmcneill
50 1.1 jmcneill #include <arm/cortex/gtmr_var.h>
51 1.1 jmcneill #include <arm/cortex/gic_reg.h>
52 1.1 jmcneill
53 1.1 jmcneill #include <dev/ic/ns16550reg.h>
54 1.1 jmcneill #include <dev/ic/comreg.h>
55 1.1 jmcneill
56 1.1 jmcneill #include <arm/arm/psci.h>
57 1.26 ryo #include <arm/fdt/psci_fdtvar.h>
58 1.1 jmcneill
59 1.1 jmcneill #include <arm/sunxi/sunxi_platform.h>
60 1.1 jmcneill
61 1.32 jmcneill #if defined(SOC_SUNXI_MC)
62 1.32 jmcneill #include <arm/sunxi/sunxi_mc_smp.h>
63 1.32 jmcneill #endif
64 1.32 jmcneill
65 1.8 jmcneill #include <libfdt.h>
66 1.8 jmcneill
67 1.1 jmcneill #define SUNXI_REF_FREQ 24000000
68 1.1 jmcneill
69 1.7 jmcneill #define SUN4I_TIMER_BASE 0x01c20c00
70 1.7 jmcneill #define SUN4I_TIMER_SIZE 0x90
71 1.15 jmcneill #define SUN4I_TIMER_1_CTRL 0x20
72 1.15 jmcneill #define SUN4I_TIMER_1_CTRL_CLK_SRC __BITS(3,2)
73 1.15 jmcneill #define SUN4I_TIMER_1_CTRL_CLK_SRC_OSC24M 1
74 1.15 jmcneill #define SUN4I_TIMER_1_CTRL_RELOAD __BIT(1)
75 1.15 jmcneill #define SUN4I_TIMER_1_CTRL_EN __BIT(0)
76 1.15 jmcneill #define SUN4I_TIMER_1_INTV_VALUE 0x24
77 1.15 jmcneill #define SUN4I_TIMER_1_VAL 0x28
78 1.7 jmcneill
79 1.7 jmcneill #define SUN4I_WDT_BASE 0x01c20c90
80 1.7 jmcneill #define SUN4I_WDT_SIZE 0x10
81 1.7 jmcneill #define SUN4I_WDT_CTRL 0x00
82 1.7 jmcneill #define SUN4I_WDT_CTRL_KEY (0x333 << 1)
83 1.7 jmcneill #define SUN4I_WDT_CTRL_RESTART __BIT(0)
84 1.7 jmcneill #define SUN4I_WDT_MODE 0x04
85 1.7 jmcneill #define SUN4I_WDT_MODE_RST_EN __BIT(1)
86 1.7 jmcneill #define SUN4I_WDT_MODE_EN __BIT(0)
87 1.7 jmcneill
88 1.3 jmcneill #define SUN6I_WDT_BASE 0x01c20ca0
89 1.3 jmcneill #define SUN6I_WDT_SIZE 0x20
90 1.3 jmcneill #define SUN6I_WDT_CFG 0x14
91 1.7 jmcneill #define SUN6I_WDT_CFG_SYS __BIT(0)
92 1.3 jmcneill #define SUN6I_WDT_MODE 0x18
93 1.7 jmcneill #define SUN6I_WDT_MODE_EN __BIT(0)
94 1.1 jmcneill
95 1.10 jmcneill #define SUN9I_WDT_BASE 0x06000ca0
96 1.10 jmcneill #define SUN9I_WDT_SIZE 0x20
97 1.10 jmcneill #define SUN9I_WDT_CFG 0x14
98 1.10 jmcneill #define SUN9I_WDT_CFG_SYS __BIT(0)
99 1.10 jmcneill #define SUN9I_WDT_MODE 0x18
100 1.10 jmcneill #define SUN9I_WDT_MODE_EN __BIT(0)
101 1.10 jmcneill
102 1.20 jmcneill #define SUN50I_H6_WDT_BASE 0x01c20ca0
103 1.20 jmcneill #define SUN50I_H6_WDT_SIZE 0x20
104 1.20 jmcneill #define SUN50I_H6_WDT_CFG 0x14
105 1.20 jmcneill #define SUN50I_H6_WDT_CFG_SYS __BIT(0)
106 1.20 jmcneill #define SUN50I_H6_WDT_MODE 0x18
107 1.20 jmcneill #define SUN50I_H6_WDT_MODE_EN __BIT(0)
108 1.20 jmcneill
109 1.21 ryo extern struct arm32_bus_dma_tag arm_generic_dma_tag;
110 1.22 ryo extern struct bus_space arm_generic_bs_tag;
111 1.22 ryo extern struct bus_space arm_generic_a4x_bs_tag;
112 1.22 ryo
113 1.22 ryo #define sunxi_dma_tag arm_generic_dma_tag
114 1.22 ryo #define sunxi_bs_tag arm_generic_bs_tag
115 1.22 ryo #define sunxi_a4x_bs_tag arm_generic_a4x_bs_tag
116 1.1 jmcneill
117 1.37 mrg static bus_space_handle_t reset_bsh;
118 1.37 mrg
119 1.1 jmcneill static const struct pmap_devmap *
120 1.1 jmcneill sunxi_platform_devmap(void)
121 1.1 jmcneill {
122 1.1 jmcneill static const struct pmap_devmap devmap[] = {
123 1.1 jmcneill DEVMAP_ENTRY(SUNXI_CORE_VBASE,
124 1.1 jmcneill SUNXI_CORE_PBASE,
125 1.1 jmcneill SUNXI_CORE_SIZE),
126 1.1 jmcneill DEVMAP_ENTRY_END
127 1.17 skrll };
128 1.1 jmcneill
129 1.1 jmcneill return devmap;
130 1.1 jmcneill }
131 1.1 jmcneill
132 1.34 jmcneill #define SUNXI_MC_CPU_VBASE (SUNXI_CORE_VBASE + SUNXI_CORE_SIZE)
133 1.34 jmcneill #define SUNXI_MC_CPU_PBASE 0x01700000
134 1.34 jmcneill #define SUNXI_MC_CPU_SIZE 0x00100000
135 1.32 jmcneill
136 1.32 jmcneill static const struct pmap_devmap *
137 1.32 jmcneill sun8i_a83t_platform_devmap(void)
138 1.32 jmcneill {
139 1.32 jmcneill static const struct pmap_devmap devmap[] = {
140 1.32 jmcneill DEVMAP_ENTRY(SUNXI_CORE_VBASE,
141 1.32 jmcneill SUNXI_CORE_PBASE,
142 1.32 jmcneill SUNXI_CORE_SIZE),
143 1.34 jmcneill DEVMAP_ENTRY(SUNXI_MC_CPU_VBASE,
144 1.34 jmcneill SUNXI_MC_CPU_PBASE,
145 1.34 jmcneill SUNXI_MC_CPU_SIZE),
146 1.32 jmcneill DEVMAP_ENTRY_END
147 1.32 jmcneill };
148 1.32 jmcneill
149 1.32 jmcneill return devmap;
150 1.32 jmcneill }
151 1.32 jmcneill
152 1.34 jmcneill #define SUN9I_A80_PRCM_VBASE (SUNXI_MC_CPU_VBASE + SUNXI_MC_CPU_PBASE)
153 1.34 jmcneill #define SUN9I_A80_PRCM_PBASE 0x08000000
154 1.34 jmcneill #define SUN9I_A80_PRCM_SIZE 0x00100000
155 1.34 jmcneill
156 1.34 jmcneill static const struct pmap_devmap *
157 1.34 jmcneill sun9i_a80_platform_devmap(void)
158 1.34 jmcneill {
159 1.34 jmcneill static const struct pmap_devmap devmap[] = {
160 1.34 jmcneill DEVMAP_ENTRY(SUNXI_CORE_VBASE,
161 1.34 jmcneill SUNXI_CORE_PBASE,
162 1.34 jmcneill SUNXI_CORE_SIZE),
163 1.34 jmcneill DEVMAP_ENTRY(SUNXI_MC_CPU_VBASE,
164 1.34 jmcneill SUNXI_MC_CPU_PBASE,
165 1.34 jmcneill SUNXI_MC_CPU_SIZE),
166 1.34 jmcneill DEVMAP_ENTRY(SUN9I_A80_PRCM_VBASE,
167 1.34 jmcneill SUN9I_A80_PRCM_PBASE,
168 1.34 jmcneill SUN9I_A80_PRCM_SIZE),
169 1.34 jmcneill DEVMAP_ENTRY_END
170 1.34 jmcneill };
171 1.34 jmcneill
172 1.34 jmcneill return devmap;
173 1.34 jmcneill }
174 1.34 jmcneill
175 1.34 jmcneill
176 1.1 jmcneill static void
177 1.1 jmcneill sunxi_platform_init_attach_args(struct fdt_attach_args *faa)
178 1.1 jmcneill {
179 1.22 ryo faa->faa_bst = &sunxi_bs_tag;
180 1.22 ryo faa->faa_a4x_bst = &sunxi_a4x_bs_tag;
181 1.22 ryo faa->faa_dmat = &sunxi_dma_tag;
182 1.1 jmcneill }
183 1.1 jmcneill
184 1.22 ryo void sunxi_platform_early_putchar(char);
185 1.22 ryo
186 1.22 ryo void
187 1.1 jmcneill sunxi_platform_early_putchar(char c)
188 1.1 jmcneill {
189 1.1 jmcneill #ifdef CONSADDR
190 1.22 ryo #define CONSADDR_VA ((CONSADDR - SUNXI_CORE_PBASE) + SUNXI_CORE_VBASE)
191 1.22 ryo volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
192 1.22 ryo (volatile uint32_t *)CONSADDR_VA :
193 1.22 ryo (volatile uint32_t *)CONSADDR;
194 1.1 jmcneill
195 1.14 jakllsch while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0)
196 1.1 jmcneill ;
197 1.1 jmcneill
198 1.14 jakllsch uartaddr[com_data] = htole32(c);
199 1.1 jmcneill #endif
200 1.1 jmcneill }
201 1.1 jmcneill
202 1.1 jmcneill static void
203 1.1 jmcneill sunxi_platform_device_register(device_t self, void *aux)
204 1.1 jmcneill {
205 1.18 jmcneill prop_dictionary_t prop = device_properties(self);
206 1.35 jmcneill int val;
207 1.18 jmcneill
208 1.18 jmcneill if (device_is_a(self, "rgephy")) {
209 1.19 jmcneill /* Pine64+ and NanoPi NEO Plus2 gigabit ethernet workaround */
210 1.19 jmcneill const char * compat[] = {
211 1.19 jmcneill "pine64,pine64-plus",
212 1.19 jmcneill "friendlyarm,nanopi-neo-plus2",
213 1.19 jmcneill NULL
214 1.19 jmcneill };
215 1.18 jmcneill if (of_match_compatible(OF_finddevice("/"), compat)) {
216 1.18 jmcneill prop_dictionary_set_bool(prop, "no-rx-delay", true);
217 1.18 jmcneill }
218 1.18 jmcneill }
219 1.27 jmcneill
220 1.27 jmcneill if (device_is_a(self, "armgtmr")) {
221 1.27 jmcneill /* Allwinner A64 has an unstable architectural timer */
222 1.27 jmcneill const char * compat[] = {
223 1.27 jmcneill "allwinner,sun50i-a64",
224 1.36 mrg /* Cubietruck Plus triggers this problem as well. */
225 1.36 mrg "allwinner,sun8i-a83t",
226 1.27 jmcneill NULL
227 1.27 jmcneill };
228 1.27 jmcneill if (of_match_compatible(OF_finddevice("/"), compat)) {
229 1.27 jmcneill prop_dictionary_set_bool(prop, "sun50i-a64-unstable-timer", true);
230 1.27 jmcneill }
231 1.27 jmcneill }
232 1.35 jmcneill
233 1.35 jmcneill if (device_is_a(self, "sunxidrm")) {
234 1.35 jmcneill if (get_bootconf_option(boot_args, "nomodeset", BOOTOPT_TYPE_BOOLEAN, &val))
235 1.35 jmcneill if (val)
236 1.35 jmcneill prop_dictionary_set_bool(prop, "disabled", true);
237 1.35 jmcneill }
238 1.1 jmcneill }
239 1.1 jmcneill
240 1.3 jmcneill static u_int
241 1.3 jmcneill sunxi_platform_uart_freq(void)
242 1.3 jmcneill {
243 1.3 jmcneill return SUNXI_REF_FREQ;
244 1.3 jmcneill }
245 1.3 jmcneill
246 1.1 jmcneill static void
247 1.8 jmcneill sunxi_platform_bootstrap(void)
248 1.8 jmcneill {
249 1.30 skrll arm_fdt_cpu_bootstrap();
250 1.30 skrll
251 1.23 bouyer void *fdt_data = __UNCONST(fdtbus_get_data());
252 1.23 bouyer const int chosen_off = fdt_path_offset(fdt_data, "/chosen");
253 1.23 bouyer if (chosen_off < 0)
254 1.23 bouyer return;
255 1.23 bouyer
256 1.8 jmcneill if (match_bootconf_option(boot_args, "console", "fb")) {
257 1.8 jmcneill const int framebuffer_off =
258 1.8 jmcneill fdt_path_offset(fdt_data, "/chosen/framebuffer");
259 1.23 bouyer if (framebuffer_off >= 0) {
260 1.22 ryo const char *status = fdt_getprop(fdt_data,
261 1.22 ryo framebuffer_off, "status", NULL);
262 1.22 ryo if (status == NULL || strncmp(status, "ok", 2) == 0) {
263 1.22 ryo fdt_setprop_string(fdt_data, chosen_off,
264 1.22 ryo "stdout-path", "/chosen/framebuffer");
265 1.22 ryo }
266 1.22 ryo }
267 1.23 bouyer } else if (match_bootconf_option(boot_args, "console", "serial")) {
268 1.23 bouyer fdt_setprop_string(fdt_data, chosen_off,
269 1.23 bouyer "stdout-path", "serial0:115200n8");
270 1.8 jmcneill }
271 1.7 jmcneill }
272 1.7 jmcneill
273 1.37 mrg static void
274 1.37 mrg sun4i_platform_bootstrap(void)
275 1.37 mrg {
276 1.37 mrg bus_space_tag_t bst = &sunxi_bs_tag;
277 1.37 mrg
278 1.37 mrg sunxi_platform_bootstrap();
279 1.37 mrg bus_space_map(bst, SUN4I_WDT_BASE, SUN4I_WDT_SIZE, 0, &reset_bsh);
280 1.37 mrg }
281 1.37 mrg
282 1.37 mrg static void
283 1.37 mrg sun6i_platform_bootstrap(void)
284 1.37 mrg {
285 1.37 mrg bus_space_tag_t bst = &sunxi_bs_tag;
286 1.37 mrg
287 1.37 mrg sunxi_platform_bootstrap();
288 1.37 mrg bus_space_map(bst, SUN6I_WDT_BASE, SUN6I_WDT_SIZE, 0, &reset_bsh);
289 1.37 mrg }
290 1.37 mrg
291 1.37 mrg static void
292 1.37 mrg sun9i_platform_bootstrap(void)
293 1.37 mrg {
294 1.37 mrg bus_space_tag_t bst = &sunxi_bs_tag;
295 1.37 mrg
296 1.37 mrg sunxi_platform_bootstrap();
297 1.37 mrg bus_space_map(bst, SUN9I_WDT_BASE, SUN9I_WDT_SIZE, 0, &reset_bsh);
298 1.37 mrg }
299 1.37 mrg
300 1.37 mrg static void
301 1.37 mrg sun50i_h6_platform_bootstrap(void)
302 1.37 mrg {
303 1.37 mrg bus_space_tag_t bst = &sunxi_bs_tag;
304 1.37 mrg
305 1.37 mrg sunxi_platform_bootstrap();
306 1.37 mrg bus_space_map(bst, SUN50I_H6_WDT_BASE, SUN50I_H6_WDT_SIZE, 0, &reset_bsh);
307 1.37 mrg }
308 1.37 mrg
309 1.33 jmcneill #if defined(SOC_SUNXI_MC)
310 1.33 jmcneill static int
311 1.34 jmcneill cpu_enable_sun8i_a83t(int phandle)
312 1.32 jmcneill {
313 1.33 jmcneill uint64_t mpidr;
314 1.32 jmcneill
315 1.33 jmcneill fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
316 1.32 jmcneill
317 1.34 jmcneill return sun8i_a83t_smp_enable(mpidr);
318 1.33 jmcneill }
319 1.34 jmcneill ARM_CPU_METHOD(sun8i_a83t, "allwinner,sun8i-a83t-smp", cpu_enable_sun8i_a83t);
320 1.34 jmcneill
321 1.34 jmcneill static int
322 1.34 jmcneill cpu_enable_sun9i_a80(int phandle)
323 1.34 jmcneill {
324 1.34 jmcneill uint64_t mpidr;
325 1.34 jmcneill
326 1.34 jmcneill fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
327 1.34 jmcneill
328 1.34 jmcneill return sun9i_a80_smp_enable(mpidr);
329 1.34 jmcneill }
330 1.34 jmcneill ARM_CPU_METHOD(sun9i_a80, "allwinner,sun9i-a80-smp", cpu_enable_sun9i_a80);
331 1.32 jmcneill #endif
332 1.32 jmcneill
333 1.7 jmcneill static void
334 1.7 jmcneill sun4i_platform_reset(void)
335 1.7 jmcneill {
336 1.22 ryo bus_space_tag_t bst = &sunxi_bs_tag;
337 1.7 jmcneill
338 1.37 mrg bus_space_write_4(bst, reset_bsh, SUN4I_WDT_CTRL,
339 1.7 jmcneill SUN4I_WDT_CTRL_KEY | SUN4I_WDT_CTRL_RESTART);
340 1.7 jmcneill for (;;) {
341 1.37 mrg bus_space_write_4(bst, reset_bsh, SUN4I_WDT_MODE,
342 1.7 jmcneill SUN4I_WDT_MODE_EN | SUN4I_WDT_MODE_RST_EN);
343 1.7 jmcneill }
344 1.7 jmcneill }
345 1.7 jmcneill
346 1.7 jmcneill static void
347 1.7 jmcneill sun4i_platform_delay(u_int n)
348 1.7 jmcneill {
349 1.22 ryo static bus_space_tag_t bst = &sunxi_bs_tag;
350 1.7 jmcneill static bus_space_handle_t bsh = 0;
351 1.12 jmcneill const long incs_per_us = SUNXI_REF_FREQ / 1000000;
352 1.12 jmcneill long ticks = n * incs_per_us;
353 1.7 jmcneill uint32_t cur, prev;
354 1.7 jmcneill
355 1.15 jmcneill if (bsh == 0) {
356 1.7 jmcneill bus_space_map(bst, SUN4I_TIMER_BASE, SUN4I_TIMER_SIZE, 0, &bsh);
357 1.7 jmcneill
358 1.15 jmcneill /* Enable Timer 1 */
359 1.15 jmcneill bus_space_write_4(bst, bsh, SUN4I_TIMER_1_INTV_VALUE, ~0U);
360 1.15 jmcneill bus_space_write_4(bst, bsh, SUN4I_TIMER_1_CTRL,
361 1.15 jmcneill SUN4I_TIMER_1_CTRL_EN |
362 1.15 jmcneill SUN4I_TIMER_1_CTRL_RELOAD |
363 1.15 jmcneill __SHIFTIN(SUN4I_TIMER_1_CTRL_CLK_SRC_OSC24M,
364 1.15 jmcneill SUN4I_TIMER_1_CTRL_CLK_SRC));
365 1.15 jmcneill }
366 1.15 jmcneill
367 1.15 jmcneill prev = ~bus_space_read_4(bst, bsh, SUN4I_TIMER_1_VAL);
368 1.7 jmcneill while (ticks > 0) {
369 1.15 jmcneill cur = ~bus_space_read_4(bst, bsh, SUN4I_TIMER_1_VAL);
370 1.7 jmcneill if (cur > prev)
371 1.7 jmcneill ticks -= (cur - prev);
372 1.7 jmcneill else
373 1.7 jmcneill ticks -= (~0U - cur + prev);
374 1.7 jmcneill prev = cur;
375 1.7 jmcneill }
376 1.7 jmcneill }
377 1.7 jmcneill
378 1.7 jmcneill static void
379 1.3 jmcneill sun6i_platform_reset(void)
380 1.1 jmcneill {
381 1.22 ryo bus_space_tag_t bst = &sunxi_bs_tag;
382 1.1 jmcneill
383 1.37 mrg bus_space_write_4(bst, reset_bsh, SUN6I_WDT_CFG, SUN6I_WDT_CFG_SYS);
384 1.37 mrg bus_space_write_4(bst, reset_bsh, SUN6I_WDT_MODE, SUN6I_WDT_MODE_EN);
385 1.1 jmcneill }
386 1.1 jmcneill
387 1.10 jmcneill static void
388 1.10 jmcneill sun9i_platform_reset(void)
389 1.10 jmcneill {
390 1.22 ryo bus_space_tag_t bst = &sunxi_bs_tag;
391 1.10 jmcneill
392 1.37 mrg bus_space_write_4(bst, reset_bsh, SUN9I_WDT_CFG, SUN9I_WDT_CFG_SYS);
393 1.37 mrg bus_space_write_4(bst, reset_bsh, SUN9I_WDT_MODE, SUN9I_WDT_MODE_EN);
394 1.10 jmcneill }
395 1.10 jmcneill
396 1.20 jmcneill static void
397 1.20 jmcneill sun50i_h6_platform_reset(void)
398 1.20 jmcneill {
399 1.22 ryo bus_space_tag_t bst = &sunxi_bs_tag;
400 1.20 jmcneill
401 1.37 mrg bus_space_write_4(bst, reset_bsh, SUN50I_H6_WDT_CFG, SUN50I_H6_WDT_CFG_SYS);
402 1.37 mrg bus_space_write_4(bst, reset_bsh, SUN50I_H6_WDT_MODE, SUN50I_H6_WDT_MODE_EN);
403 1.20 jmcneill }
404 1.20 jmcneill
405 1.9 jmcneill static const struct arm_platform sun4i_platform = {
406 1.25 skrll .ap_devmap = sunxi_platform_devmap,
407 1.37 mrg .ap_bootstrap = sun4i_platform_bootstrap,
408 1.25 skrll .ap_init_attach_args = sunxi_platform_init_attach_args,
409 1.25 skrll .ap_device_register = sunxi_platform_device_register,
410 1.25 skrll .ap_reset = sun4i_platform_reset,
411 1.25 skrll .ap_delay = sun4i_platform_delay,
412 1.25 skrll .ap_uart_freq = sunxi_platform_uart_freq,
413 1.9 jmcneill };
414 1.9 jmcneill
415 1.9 jmcneill ARM_PLATFORM(sun4i_a10, "allwinner,sun4i-a10", &sun4i_platform);
416 1.9 jmcneill
417 1.7 jmcneill static const struct arm_platform sun5i_platform = {
418 1.25 skrll .ap_devmap = sunxi_platform_devmap,
419 1.37 mrg .ap_bootstrap = sun4i_platform_bootstrap,
420 1.25 skrll .ap_init_attach_args = sunxi_platform_init_attach_args,
421 1.25 skrll .ap_device_register = sunxi_platform_device_register,
422 1.25 skrll .ap_reset = sun4i_platform_reset,
423 1.25 skrll .ap_delay = sun4i_platform_delay,
424 1.25 skrll .ap_uart_freq = sunxi_platform_uart_freq,
425 1.7 jmcneill };
426 1.7 jmcneill
427 1.7 jmcneill ARM_PLATFORM(sun5i_a13, "allwinner,sun5i-a13", &sun5i_platform);
428 1.16 jmcneill ARM_PLATFORM(sun5i_gr8, "nextthing,gr8", &sun5i_platform);
429 1.6 jmcneill
430 1.6 jmcneill static const struct arm_platform sun6i_platform = {
431 1.25 skrll .ap_devmap = sunxi_platform_devmap,
432 1.37 mrg .ap_bootstrap = sun6i_platform_bootstrap,
433 1.25 skrll .ap_init_attach_args = sunxi_platform_init_attach_args,
434 1.25 skrll .ap_device_register = sunxi_platform_device_register,
435 1.25 skrll .ap_reset = sun6i_platform_reset,
436 1.25 skrll .ap_delay = gtmr_delay,
437 1.25 skrll .ap_uart_freq = sunxi_platform_uart_freq,
438 1.29 skrll .ap_mpstart = arm_fdt_cpu_mpstart,
439 1.6 jmcneill };
440 1.6 jmcneill
441 1.6 jmcneill ARM_PLATFORM(sun6i_a31, "allwinner,sun6i-a31", &sun6i_platform);
442 1.6 jmcneill
443 1.9 jmcneill static const struct arm_platform sun7i_platform = {
444 1.25 skrll .ap_devmap = sunxi_platform_devmap,
445 1.37 mrg .ap_bootstrap = sun4i_platform_bootstrap,
446 1.25 skrll .ap_init_attach_args = sunxi_platform_init_attach_args,
447 1.25 skrll .ap_device_register = sunxi_platform_device_register,
448 1.25 skrll .ap_reset = sun4i_platform_reset,
449 1.25 skrll .ap_delay = sun4i_platform_delay,
450 1.25 skrll .ap_uart_freq = sunxi_platform_uart_freq,
451 1.29 skrll .ap_mpstart = arm_fdt_cpu_mpstart,
452 1.9 jmcneill };
453 1.9 jmcneill
454 1.9 jmcneill ARM_PLATFORM(sun7i_a20, "allwinner,sun7i-a20", &sun7i_platform);
455 1.9 jmcneill
456 1.3 jmcneill static const struct arm_platform sun8i_platform = {
457 1.25 skrll .ap_devmap = sunxi_platform_devmap,
458 1.37 mrg .ap_bootstrap = sun6i_platform_bootstrap,
459 1.25 skrll .ap_init_attach_args = sunxi_platform_init_attach_args,
460 1.25 skrll .ap_device_register = sunxi_platform_device_register,
461 1.25 skrll .ap_reset = sun6i_platform_reset,
462 1.25 skrll .ap_delay = gtmr_delay,
463 1.25 skrll .ap_uart_freq = sunxi_platform_uart_freq,
464 1.29 skrll .ap_mpstart = arm_fdt_cpu_mpstart,
465 1.3 jmcneill };
466 1.3 jmcneill
467 1.5 jmcneill ARM_PLATFORM(sun8i_h2plus, "allwinner,sun8i-h2-plus", &sun8i_platform);
468 1.3 jmcneill ARM_PLATFORM(sun8i_h3, "allwinner,sun8i-h3", &sun8i_platform);
469 1.32 jmcneill
470 1.32 jmcneill static const struct arm_platform sun8i_a83t_platform = {
471 1.32 jmcneill .ap_devmap = sun8i_a83t_platform_devmap,
472 1.37 mrg .ap_bootstrap = sun6i_platform_bootstrap,
473 1.32 jmcneill .ap_init_attach_args = sunxi_platform_init_attach_args,
474 1.32 jmcneill .ap_device_register = sunxi_platform_device_register,
475 1.32 jmcneill .ap_reset = sun6i_platform_reset,
476 1.32 jmcneill .ap_delay = gtmr_delay,
477 1.32 jmcneill .ap_uart_freq = sunxi_platform_uart_freq,
478 1.33 jmcneill .ap_mpstart = arm_fdt_cpu_mpstart,
479 1.32 jmcneill };
480 1.32 jmcneill
481 1.32 jmcneill ARM_PLATFORM(sun8i_a83t, "allwinner,sun8i-a83t", &sun8i_a83t_platform);
482 1.1 jmcneill
483 1.10 jmcneill static const struct arm_platform sun9i_platform = {
484 1.34 jmcneill .ap_devmap = sun9i_a80_platform_devmap,
485 1.37 mrg .ap_bootstrap = sun9i_platform_bootstrap,
486 1.25 skrll .ap_init_attach_args = sunxi_platform_init_attach_args,
487 1.25 skrll .ap_device_register = sunxi_platform_device_register,
488 1.25 skrll .ap_reset = sun9i_platform_reset,
489 1.25 skrll .ap_delay = gtmr_delay,
490 1.25 skrll .ap_uart_freq = sunxi_platform_uart_freq,
491 1.29 skrll .ap_mpstart = arm_fdt_cpu_mpstart,
492 1.10 jmcneill };
493 1.10 jmcneill
494 1.10 jmcneill ARM_PLATFORM(sun9i_a80, "allwinner,sun9i-a80", &sun9i_platform);
495 1.10 jmcneill
496 1.6 jmcneill static const struct arm_platform sun50i_platform = {
497 1.25 skrll .ap_devmap = sunxi_platform_devmap,
498 1.37 mrg .ap_bootstrap = sun6i_platform_bootstrap,
499 1.25 skrll .ap_init_attach_args = sunxi_platform_init_attach_args,
500 1.25 skrll .ap_device_register = sunxi_platform_device_register,
501 1.25 skrll .ap_reset = sun6i_platform_reset,
502 1.25 skrll .ap_delay = gtmr_delay,
503 1.25 skrll .ap_uart_freq = sunxi_platform_uart_freq,
504 1.29 skrll .ap_mpstart = arm_fdt_cpu_mpstart,
505 1.1 jmcneill };
506 1.1 jmcneill
507 1.6 jmcneill ARM_PLATFORM(sun50i_a64, "allwinner,sun50i-a64", &sun50i_platform);
508 1.11 jmcneill ARM_PLATFORM(sun50i_h5, "allwinner,sun50i-h5", &sun50i_platform);
509 1.20 jmcneill
510 1.20 jmcneill static const struct arm_platform sun50i_h6_platform = {
511 1.25 skrll .ap_devmap = sunxi_platform_devmap,
512 1.37 mrg .ap_bootstrap = sun50i_h6_platform_bootstrap,
513 1.25 skrll .ap_init_attach_args = sunxi_platform_init_attach_args,
514 1.25 skrll .ap_device_register = sunxi_platform_device_register,
515 1.25 skrll .ap_reset = sun50i_h6_platform_reset,
516 1.25 skrll .ap_delay = gtmr_delay,
517 1.25 skrll .ap_uart_freq = sunxi_platform_uart_freq,
518 1.29 skrll .ap_mpstart = arm_fdt_cpu_mpstart,
519 1.20 jmcneill };
520 1.20 jmcneill
521 1.20 jmcneill ARM_PLATFORM(sun50i_h6, "allwinner,sun50i-h6", &sun50i_h6_platform);
522