sunxi_platform.c revision 1.36
1 /* $NetBSD: sunxi_platform.c,v 1.36 2019/04/30 10:10:45 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 #include "opt_multiprocessor.h" 31 #include "opt_console.h" 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: sunxi_platform.c,v 1.36 2019/04/30 10:10:45 mrg Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/cpu.h> 39 #include <sys/device.h> 40 #include <sys/termios.h> 41 42 #include <dev/fdt/fdtvar.h> 43 #include <arm/fdt/arm_fdtvar.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <machine/bootconfig.h> 48 #include <arm/cpufunc.h> 49 50 #include <arm/cortex/gtmr_var.h> 51 #include <arm/cortex/gic_reg.h> 52 53 #include <dev/ic/ns16550reg.h> 54 #include <dev/ic/comreg.h> 55 56 #include <arm/arm/psci.h> 57 #include <arm/fdt/psci_fdtvar.h> 58 59 #include <arm/sunxi/sunxi_platform.h> 60 61 #if defined(SOC_SUNXI_MC) 62 #include <arm/sunxi/sunxi_mc_smp.h> 63 #endif 64 65 #include <libfdt.h> 66 67 #define SUNXI_REF_FREQ 24000000 68 69 #define SUN4I_TIMER_BASE 0x01c20c00 70 #define SUN4I_TIMER_SIZE 0x90 71 #define SUN4I_TIMER_1_CTRL 0x20 72 #define SUN4I_TIMER_1_CTRL_CLK_SRC __BITS(3,2) 73 #define SUN4I_TIMER_1_CTRL_CLK_SRC_OSC24M 1 74 #define SUN4I_TIMER_1_CTRL_RELOAD __BIT(1) 75 #define SUN4I_TIMER_1_CTRL_EN __BIT(0) 76 #define SUN4I_TIMER_1_INTV_VALUE 0x24 77 #define SUN4I_TIMER_1_VAL 0x28 78 79 #define SUN4I_WDT_BASE 0x01c20c90 80 #define SUN4I_WDT_SIZE 0x10 81 #define SUN4I_WDT_CTRL 0x00 82 #define SUN4I_WDT_CTRL_KEY (0x333 << 1) 83 #define SUN4I_WDT_CTRL_RESTART __BIT(0) 84 #define SUN4I_WDT_MODE 0x04 85 #define SUN4I_WDT_MODE_RST_EN __BIT(1) 86 #define SUN4I_WDT_MODE_EN __BIT(0) 87 88 #define SUN6I_WDT_BASE 0x01c20ca0 89 #define SUN6I_WDT_SIZE 0x20 90 #define SUN6I_WDT_CFG 0x14 91 #define SUN6I_WDT_CFG_SYS __BIT(0) 92 #define SUN6I_WDT_MODE 0x18 93 #define SUN6I_WDT_MODE_EN __BIT(0) 94 95 #define SUN9I_WDT_BASE 0x06000ca0 96 #define SUN9I_WDT_SIZE 0x20 97 #define SUN9I_WDT_CFG 0x14 98 #define SUN9I_WDT_CFG_SYS __BIT(0) 99 #define SUN9I_WDT_MODE 0x18 100 #define SUN9I_WDT_MODE_EN __BIT(0) 101 102 #define SUN50I_H6_WDT_BASE 0x01c20ca0 103 #define SUN50I_H6_WDT_SIZE 0x20 104 #define SUN50I_H6_WDT_CFG 0x14 105 #define SUN50I_H6_WDT_CFG_SYS __BIT(0) 106 #define SUN50I_H6_WDT_MODE 0x18 107 #define SUN50I_H6_WDT_MODE_EN __BIT(0) 108 109 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 110 extern struct bus_space arm_generic_bs_tag; 111 extern struct bus_space arm_generic_a4x_bs_tag; 112 113 #define sunxi_dma_tag arm_generic_dma_tag 114 #define sunxi_bs_tag arm_generic_bs_tag 115 #define sunxi_a4x_bs_tag arm_generic_a4x_bs_tag 116 117 static const struct pmap_devmap * 118 sunxi_platform_devmap(void) 119 { 120 static const struct pmap_devmap devmap[] = { 121 DEVMAP_ENTRY(SUNXI_CORE_VBASE, 122 SUNXI_CORE_PBASE, 123 SUNXI_CORE_SIZE), 124 DEVMAP_ENTRY_END 125 }; 126 127 return devmap; 128 } 129 130 #define SUNXI_MC_CPU_VBASE (SUNXI_CORE_VBASE + SUNXI_CORE_SIZE) 131 #define SUNXI_MC_CPU_PBASE 0x01700000 132 #define SUNXI_MC_CPU_SIZE 0x00100000 133 134 static const struct pmap_devmap * 135 sun8i_a83t_platform_devmap(void) 136 { 137 static const struct pmap_devmap devmap[] = { 138 DEVMAP_ENTRY(SUNXI_CORE_VBASE, 139 SUNXI_CORE_PBASE, 140 SUNXI_CORE_SIZE), 141 DEVMAP_ENTRY(SUNXI_MC_CPU_VBASE, 142 SUNXI_MC_CPU_PBASE, 143 SUNXI_MC_CPU_SIZE), 144 DEVMAP_ENTRY_END 145 }; 146 147 return devmap; 148 } 149 150 #define SUN9I_A80_PRCM_VBASE (SUNXI_MC_CPU_VBASE + SUNXI_MC_CPU_PBASE) 151 #define SUN9I_A80_PRCM_PBASE 0x08000000 152 #define SUN9I_A80_PRCM_SIZE 0x00100000 153 154 static const struct pmap_devmap * 155 sun9i_a80_platform_devmap(void) 156 { 157 static const struct pmap_devmap devmap[] = { 158 DEVMAP_ENTRY(SUNXI_CORE_VBASE, 159 SUNXI_CORE_PBASE, 160 SUNXI_CORE_SIZE), 161 DEVMAP_ENTRY(SUNXI_MC_CPU_VBASE, 162 SUNXI_MC_CPU_PBASE, 163 SUNXI_MC_CPU_SIZE), 164 DEVMAP_ENTRY(SUN9I_A80_PRCM_VBASE, 165 SUN9I_A80_PRCM_PBASE, 166 SUN9I_A80_PRCM_SIZE), 167 DEVMAP_ENTRY_END 168 }; 169 170 return devmap; 171 } 172 173 174 static void 175 sunxi_platform_init_attach_args(struct fdt_attach_args *faa) 176 { 177 faa->faa_bst = &sunxi_bs_tag; 178 faa->faa_a4x_bst = &sunxi_a4x_bs_tag; 179 faa->faa_dmat = &sunxi_dma_tag; 180 } 181 182 void sunxi_platform_early_putchar(char); 183 184 void 185 sunxi_platform_early_putchar(char c) 186 { 187 #ifdef CONSADDR 188 #define CONSADDR_VA ((CONSADDR - SUNXI_CORE_PBASE) + SUNXI_CORE_VBASE) 189 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 190 (volatile uint32_t *)CONSADDR_VA : 191 (volatile uint32_t *)CONSADDR; 192 193 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 194 ; 195 196 uartaddr[com_data] = htole32(c); 197 #endif 198 } 199 200 static void 201 sunxi_platform_device_register(device_t self, void *aux) 202 { 203 prop_dictionary_t prop = device_properties(self); 204 int val; 205 206 if (device_is_a(self, "rgephy")) { 207 /* Pine64+ and NanoPi NEO Plus2 gigabit ethernet workaround */ 208 const char * compat[] = { 209 "pine64,pine64-plus", 210 "friendlyarm,nanopi-neo-plus2", 211 NULL 212 }; 213 if (of_match_compatible(OF_finddevice("/"), compat)) { 214 prop_dictionary_set_bool(prop, "no-rx-delay", true); 215 } 216 } 217 218 if (device_is_a(self, "armgtmr")) { 219 /* Allwinner A64 has an unstable architectural timer */ 220 const char * compat[] = { 221 "allwinner,sun50i-a64", 222 /* Cubietruck Plus triggers this problem as well. */ 223 "allwinner,sun8i-a83t", 224 NULL 225 }; 226 if (of_match_compatible(OF_finddevice("/"), compat)) { 227 prop_dictionary_set_bool(prop, "sun50i-a64-unstable-timer", true); 228 } 229 } 230 231 if (device_is_a(self, "sunxidrm")) { 232 if (get_bootconf_option(boot_args, "nomodeset", BOOTOPT_TYPE_BOOLEAN, &val)) 233 if (val) 234 prop_dictionary_set_bool(prop, "disabled", true); 235 } 236 } 237 238 static u_int 239 sunxi_platform_uart_freq(void) 240 { 241 return SUNXI_REF_FREQ; 242 } 243 244 static void 245 sunxi_platform_bootstrap(void) 246 { 247 arm_fdt_cpu_bootstrap(); 248 249 void *fdt_data = __UNCONST(fdtbus_get_data()); 250 const int chosen_off = fdt_path_offset(fdt_data, "/chosen"); 251 if (chosen_off < 0) 252 return; 253 254 if (match_bootconf_option(boot_args, "console", "fb")) { 255 const int framebuffer_off = 256 fdt_path_offset(fdt_data, "/chosen/framebuffer"); 257 if (framebuffer_off >= 0) { 258 const char *status = fdt_getprop(fdt_data, 259 framebuffer_off, "status", NULL); 260 if (status == NULL || strncmp(status, "ok", 2) == 0) { 261 fdt_setprop_string(fdt_data, chosen_off, 262 "stdout-path", "/chosen/framebuffer"); 263 } 264 } 265 } else if (match_bootconf_option(boot_args, "console", "serial")) { 266 fdt_setprop_string(fdt_data, chosen_off, 267 "stdout-path", "serial0:115200n8"); 268 } 269 } 270 271 #if defined(SOC_SUNXI_MC) 272 static int 273 cpu_enable_sun8i_a83t(int phandle) 274 { 275 uint64_t mpidr; 276 277 fdtbus_get_reg64(phandle, 0, &mpidr, NULL); 278 279 return sun8i_a83t_smp_enable(mpidr); 280 } 281 ARM_CPU_METHOD(sun8i_a83t, "allwinner,sun8i-a83t-smp", cpu_enable_sun8i_a83t); 282 283 static int 284 cpu_enable_sun9i_a80(int phandle) 285 { 286 uint64_t mpidr; 287 288 fdtbus_get_reg64(phandle, 0, &mpidr, NULL); 289 290 return sun9i_a80_smp_enable(mpidr); 291 } 292 ARM_CPU_METHOD(sun9i_a80, "allwinner,sun9i-a80-smp", cpu_enable_sun9i_a80); 293 #endif 294 295 static void 296 sun4i_platform_reset(void) 297 { 298 bus_space_tag_t bst = &sunxi_bs_tag; 299 bus_space_handle_t bsh; 300 301 bus_space_map(bst, SUN4I_WDT_BASE, SUN4I_WDT_SIZE, 0, &bsh); 302 303 bus_space_write_4(bst, bsh, SUN4I_WDT_CTRL, 304 SUN4I_WDT_CTRL_KEY | SUN4I_WDT_CTRL_RESTART); 305 for (;;) { 306 bus_space_write_4(bst, bsh, SUN4I_WDT_MODE, 307 SUN4I_WDT_MODE_EN | SUN4I_WDT_MODE_RST_EN); 308 } 309 } 310 311 static void 312 sun4i_platform_delay(u_int n) 313 { 314 static bus_space_tag_t bst = &sunxi_bs_tag; 315 static bus_space_handle_t bsh = 0; 316 const long incs_per_us = SUNXI_REF_FREQ / 1000000; 317 long ticks = n * incs_per_us; 318 uint32_t cur, prev; 319 320 if (bsh == 0) { 321 bus_space_map(bst, SUN4I_TIMER_BASE, SUN4I_TIMER_SIZE, 0, &bsh); 322 323 /* Enable Timer 1 */ 324 bus_space_write_4(bst, bsh, SUN4I_TIMER_1_INTV_VALUE, ~0U); 325 bus_space_write_4(bst, bsh, SUN4I_TIMER_1_CTRL, 326 SUN4I_TIMER_1_CTRL_EN | 327 SUN4I_TIMER_1_CTRL_RELOAD | 328 __SHIFTIN(SUN4I_TIMER_1_CTRL_CLK_SRC_OSC24M, 329 SUN4I_TIMER_1_CTRL_CLK_SRC)); 330 } 331 332 prev = ~bus_space_read_4(bst, bsh, SUN4I_TIMER_1_VAL); 333 while (ticks > 0) { 334 cur = ~bus_space_read_4(bst, bsh, SUN4I_TIMER_1_VAL); 335 if (cur > prev) 336 ticks -= (cur - prev); 337 else 338 ticks -= (~0U - cur + prev); 339 prev = cur; 340 } 341 } 342 343 static void 344 sun6i_platform_reset(void) 345 { 346 bus_space_tag_t bst = &sunxi_bs_tag; 347 bus_space_handle_t bsh; 348 349 bus_space_map(bst, SUN6I_WDT_BASE, SUN6I_WDT_SIZE, 0, &bsh); 350 351 bus_space_write_4(bst, bsh, SUN6I_WDT_CFG, SUN6I_WDT_CFG_SYS); 352 bus_space_write_4(bst, bsh, SUN6I_WDT_MODE, SUN6I_WDT_MODE_EN); 353 } 354 355 static void 356 sun9i_platform_reset(void) 357 { 358 bus_space_tag_t bst = &sunxi_bs_tag; 359 bus_space_handle_t bsh; 360 361 bus_space_map(bst, SUN9I_WDT_BASE, SUN9I_WDT_SIZE, 0, &bsh); 362 363 bus_space_write_4(bst, bsh, SUN9I_WDT_CFG, SUN9I_WDT_CFG_SYS); 364 bus_space_write_4(bst, bsh, SUN9I_WDT_MODE, SUN9I_WDT_MODE_EN); 365 } 366 367 static void 368 sun50i_h6_platform_reset(void) 369 { 370 bus_space_tag_t bst = &sunxi_bs_tag; 371 bus_space_handle_t bsh; 372 373 bus_space_map(bst, SUN50I_H6_WDT_BASE, SUN50I_H6_WDT_SIZE, 0, &bsh); 374 375 bus_space_write_4(bst, bsh, SUN50I_H6_WDT_CFG, SUN50I_H6_WDT_CFG_SYS); 376 bus_space_write_4(bst, bsh, SUN50I_H6_WDT_MODE, SUN50I_H6_WDT_MODE_EN); 377 } 378 379 static const struct arm_platform sun4i_platform = { 380 .ap_devmap = sunxi_platform_devmap, 381 .ap_bootstrap = sunxi_platform_bootstrap, 382 .ap_init_attach_args = sunxi_platform_init_attach_args, 383 .ap_device_register = sunxi_platform_device_register, 384 .ap_reset = sun4i_platform_reset, 385 .ap_delay = sun4i_platform_delay, 386 .ap_uart_freq = sunxi_platform_uart_freq, 387 }; 388 389 ARM_PLATFORM(sun4i_a10, "allwinner,sun4i-a10", &sun4i_platform); 390 391 static const struct arm_platform sun5i_platform = { 392 .ap_devmap = sunxi_platform_devmap, 393 .ap_bootstrap = sunxi_platform_bootstrap, 394 .ap_init_attach_args = sunxi_platform_init_attach_args, 395 .ap_device_register = sunxi_platform_device_register, 396 .ap_reset = sun4i_platform_reset, 397 .ap_delay = sun4i_platform_delay, 398 .ap_uart_freq = sunxi_platform_uart_freq, 399 }; 400 401 ARM_PLATFORM(sun5i_a13, "allwinner,sun5i-a13", &sun5i_platform); 402 ARM_PLATFORM(sun5i_gr8, "nextthing,gr8", &sun5i_platform); 403 404 static const struct arm_platform sun6i_platform = { 405 .ap_devmap = sunxi_platform_devmap, 406 .ap_bootstrap = sunxi_platform_bootstrap, 407 .ap_init_attach_args = sunxi_platform_init_attach_args, 408 .ap_device_register = sunxi_platform_device_register, 409 .ap_reset = sun6i_platform_reset, 410 .ap_delay = gtmr_delay, 411 .ap_uart_freq = sunxi_platform_uart_freq, 412 .ap_mpstart = arm_fdt_cpu_mpstart, 413 }; 414 415 ARM_PLATFORM(sun6i_a31, "allwinner,sun6i-a31", &sun6i_platform); 416 417 static const struct arm_platform sun7i_platform = { 418 .ap_devmap = sunxi_platform_devmap, 419 .ap_bootstrap = sunxi_platform_bootstrap, 420 .ap_init_attach_args = sunxi_platform_init_attach_args, 421 .ap_device_register = sunxi_platform_device_register, 422 .ap_reset = sun4i_platform_reset, 423 .ap_delay = sun4i_platform_delay, 424 .ap_uart_freq = sunxi_platform_uart_freq, 425 .ap_mpstart = arm_fdt_cpu_mpstart, 426 }; 427 428 ARM_PLATFORM(sun7i_a20, "allwinner,sun7i-a20", &sun7i_platform); 429 430 static const struct arm_platform sun8i_platform = { 431 .ap_devmap = sunxi_platform_devmap, 432 .ap_bootstrap = sunxi_platform_bootstrap, 433 .ap_init_attach_args = sunxi_platform_init_attach_args, 434 .ap_device_register = sunxi_platform_device_register, 435 .ap_reset = sun6i_platform_reset, 436 .ap_delay = gtmr_delay, 437 .ap_uart_freq = sunxi_platform_uart_freq, 438 .ap_mpstart = arm_fdt_cpu_mpstart, 439 }; 440 441 ARM_PLATFORM(sun8i_h2plus, "allwinner,sun8i-h2-plus", &sun8i_platform); 442 ARM_PLATFORM(sun8i_h3, "allwinner,sun8i-h3", &sun8i_platform); 443 444 static const struct arm_platform sun8i_a83t_platform = { 445 .ap_devmap = sun8i_a83t_platform_devmap, 446 .ap_bootstrap = sunxi_platform_bootstrap, 447 .ap_init_attach_args = sunxi_platform_init_attach_args, 448 .ap_device_register = sunxi_platform_device_register, 449 .ap_reset = sun6i_platform_reset, 450 .ap_delay = gtmr_delay, 451 .ap_uart_freq = sunxi_platform_uart_freq, 452 .ap_mpstart = arm_fdt_cpu_mpstart, 453 }; 454 455 ARM_PLATFORM(sun8i_a83t, "allwinner,sun8i-a83t", &sun8i_a83t_platform); 456 457 static const struct arm_platform sun9i_platform = { 458 .ap_devmap = sun9i_a80_platform_devmap, 459 .ap_bootstrap = sunxi_platform_bootstrap, 460 .ap_init_attach_args = sunxi_platform_init_attach_args, 461 .ap_device_register = sunxi_platform_device_register, 462 .ap_reset = sun9i_platform_reset, 463 .ap_delay = gtmr_delay, 464 .ap_uart_freq = sunxi_platform_uart_freq, 465 .ap_mpstart = arm_fdt_cpu_mpstart, 466 }; 467 468 ARM_PLATFORM(sun9i_a80, "allwinner,sun9i-a80", &sun9i_platform); 469 470 static const struct arm_platform sun50i_platform = { 471 .ap_devmap = sunxi_platform_devmap, 472 .ap_bootstrap = sunxi_platform_bootstrap, 473 .ap_init_attach_args = sunxi_platform_init_attach_args, 474 .ap_device_register = sunxi_platform_device_register, 475 .ap_reset = sun6i_platform_reset, 476 .ap_delay = gtmr_delay, 477 .ap_uart_freq = sunxi_platform_uart_freq, 478 .ap_mpstart = arm_fdt_cpu_mpstart, 479 }; 480 481 ARM_PLATFORM(sun50i_a64, "allwinner,sun50i-a64", &sun50i_platform); 482 ARM_PLATFORM(sun50i_h5, "allwinner,sun50i-h5", &sun50i_platform); 483 484 static const struct arm_platform sun50i_h6_platform = { 485 .ap_devmap = sunxi_platform_devmap, 486 .ap_bootstrap = sunxi_platform_bootstrap, 487 .ap_init_attach_args = sunxi_platform_init_attach_args, 488 .ap_device_register = sunxi_platform_device_register, 489 .ap_reset = sun50i_h6_platform_reset, 490 .ap_delay = gtmr_delay, 491 .ap_uart_freq = sunxi_platform_uart_freq, 492 .ap_mpstart = arm_fdt_cpu_mpstart, 493 }; 494 495 ARM_PLATFORM(sun50i_h6, "allwinner,sun50i-h6", &sun50i_h6_platform); 496
Indexes created Tue Sep 23 07:09:52 GMT 2025