sunxi_platform.c revision 1.37
1 /* $NetBSD: sunxi_platform.c,v 1.37 2019/06/17 05:27:01 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_soc.h" 30 #include "opt_multiprocessor.h" 31 #include "opt_console.h" 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: sunxi_platform.c,v 1.37 2019/06/17 05:27:01 mrg Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/cpu.h> 39 #include <sys/device.h> 40 #include <sys/termios.h> 41 42 #include <dev/fdt/fdtvar.h> 43 #include <arm/fdt/arm_fdtvar.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <machine/bootconfig.h> 48 #include <arm/cpufunc.h> 49 50 #include <arm/cortex/gtmr_var.h> 51 #include <arm/cortex/gic_reg.h> 52 53 #include <dev/ic/ns16550reg.h> 54 #include <dev/ic/comreg.h> 55 56 #include <arm/arm/psci.h> 57 #include <arm/fdt/psci_fdtvar.h> 58 59 #include <arm/sunxi/sunxi_platform.h> 60 61 #if defined(SOC_SUNXI_MC) 62 #include <arm/sunxi/sunxi_mc_smp.h> 63 #endif 64 65 #include <libfdt.h> 66 67 #define SUNXI_REF_FREQ 24000000 68 69 #define SUN4I_TIMER_BASE 0x01c20c00 70 #define SUN4I_TIMER_SIZE 0x90 71 #define SUN4I_TIMER_1_CTRL 0x20 72 #define SUN4I_TIMER_1_CTRL_CLK_SRC __BITS(3,2) 73 #define SUN4I_TIMER_1_CTRL_CLK_SRC_OSC24M 1 74 #define SUN4I_TIMER_1_CTRL_RELOAD __BIT(1) 75 #define SUN4I_TIMER_1_CTRL_EN __BIT(0) 76 #define SUN4I_TIMER_1_INTV_VALUE 0x24 77 #define SUN4I_TIMER_1_VAL 0x28 78 79 #define SUN4I_WDT_BASE 0x01c20c90 80 #define SUN4I_WDT_SIZE 0x10 81 #define SUN4I_WDT_CTRL 0x00 82 #define SUN4I_WDT_CTRL_KEY (0x333 << 1) 83 #define SUN4I_WDT_CTRL_RESTART __BIT(0) 84 #define SUN4I_WDT_MODE 0x04 85 #define SUN4I_WDT_MODE_RST_EN __BIT(1) 86 #define SUN4I_WDT_MODE_EN __BIT(0) 87 88 #define SUN6I_WDT_BASE 0x01c20ca0 89 #define SUN6I_WDT_SIZE 0x20 90 #define SUN6I_WDT_CFG 0x14 91 #define SUN6I_WDT_CFG_SYS __BIT(0) 92 #define SUN6I_WDT_MODE 0x18 93 #define SUN6I_WDT_MODE_EN __BIT(0) 94 95 #define SUN9I_WDT_BASE 0x06000ca0 96 #define SUN9I_WDT_SIZE 0x20 97 #define SUN9I_WDT_CFG 0x14 98 #define SUN9I_WDT_CFG_SYS __BIT(0) 99 #define SUN9I_WDT_MODE 0x18 100 #define SUN9I_WDT_MODE_EN __BIT(0) 101 102 #define SUN50I_H6_WDT_BASE 0x01c20ca0 103 #define SUN50I_H6_WDT_SIZE 0x20 104 #define SUN50I_H6_WDT_CFG 0x14 105 #define SUN50I_H6_WDT_CFG_SYS __BIT(0) 106 #define SUN50I_H6_WDT_MODE 0x18 107 #define SUN50I_H6_WDT_MODE_EN __BIT(0) 108 109 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 110 extern struct bus_space arm_generic_bs_tag; 111 extern struct bus_space arm_generic_a4x_bs_tag; 112 113 #define sunxi_dma_tag arm_generic_dma_tag 114 #define sunxi_bs_tag arm_generic_bs_tag 115 #define sunxi_a4x_bs_tag arm_generic_a4x_bs_tag 116 117 static bus_space_handle_t reset_bsh; 118 119 static const struct pmap_devmap * 120 sunxi_platform_devmap(void) 121 { 122 static const struct pmap_devmap devmap[] = { 123 DEVMAP_ENTRY(SUNXI_CORE_VBASE, 124 SUNXI_CORE_PBASE, 125 SUNXI_CORE_SIZE), 126 DEVMAP_ENTRY_END 127 }; 128 129 return devmap; 130 } 131 132 #define SUNXI_MC_CPU_VBASE (SUNXI_CORE_VBASE + SUNXI_CORE_SIZE) 133 #define SUNXI_MC_CPU_PBASE 0x01700000 134 #define SUNXI_MC_CPU_SIZE 0x00100000 135 136 static const struct pmap_devmap * 137 sun8i_a83t_platform_devmap(void) 138 { 139 static const struct pmap_devmap devmap[] = { 140 DEVMAP_ENTRY(SUNXI_CORE_VBASE, 141 SUNXI_CORE_PBASE, 142 SUNXI_CORE_SIZE), 143 DEVMAP_ENTRY(SUNXI_MC_CPU_VBASE, 144 SUNXI_MC_CPU_PBASE, 145 SUNXI_MC_CPU_SIZE), 146 DEVMAP_ENTRY_END 147 }; 148 149 return devmap; 150 } 151 152 #define SUN9I_A80_PRCM_VBASE (SUNXI_MC_CPU_VBASE + SUNXI_MC_CPU_PBASE) 153 #define SUN9I_A80_PRCM_PBASE 0x08000000 154 #define SUN9I_A80_PRCM_SIZE 0x00100000 155 156 static const struct pmap_devmap * 157 sun9i_a80_platform_devmap(void) 158 { 159 static const struct pmap_devmap devmap[] = { 160 DEVMAP_ENTRY(SUNXI_CORE_VBASE, 161 SUNXI_CORE_PBASE, 162 SUNXI_CORE_SIZE), 163 DEVMAP_ENTRY(SUNXI_MC_CPU_VBASE, 164 SUNXI_MC_CPU_PBASE, 165 SUNXI_MC_CPU_SIZE), 166 DEVMAP_ENTRY(SUN9I_A80_PRCM_VBASE, 167 SUN9I_A80_PRCM_PBASE, 168 SUN9I_A80_PRCM_SIZE), 169 DEVMAP_ENTRY_END 170 }; 171 172 return devmap; 173 } 174 175 176 static void 177 sunxi_platform_init_attach_args(struct fdt_attach_args *faa) 178 { 179 faa->faa_bst = &sunxi_bs_tag; 180 faa->faa_a4x_bst = &sunxi_a4x_bs_tag; 181 faa->faa_dmat = &sunxi_dma_tag; 182 } 183 184 void sunxi_platform_early_putchar(char); 185 186 void 187 sunxi_platform_early_putchar(char c) 188 { 189 #ifdef CONSADDR 190 #define CONSADDR_VA ((CONSADDR - SUNXI_CORE_PBASE) + SUNXI_CORE_VBASE) 191 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 192 (volatile uint32_t *)CONSADDR_VA : 193 (volatile uint32_t *)CONSADDR; 194 195 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 196 ; 197 198 uartaddr[com_data] = htole32(c); 199 #endif 200 } 201 202 static void 203 sunxi_platform_device_register(device_t self, void *aux) 204 { 205 prop_dictionary_t prop = device_properties(self); 206 int val; 207 208 if (device_is_a(self, "rgephy")) { 209 /* Pine64+ and NanoPi NEO Plus2 gigabit ethernet workaround */ 210 const char * compat[] = { 211 "pine64,pine64-plus", 212 "friendlyarm,nanopi-neo-plus2", 213 NULL 214 }; 215 if (of_match_compatible(OF_finddevice("/"), compat)) { 216 prop_dictionary_set_bool(prop, "no-rx-delay", true); 217 } 218 } 219 220 if (device_is_a(self, "armgtmr")) { 221 /* Allwinner A64 has an unstable architectural timer */ 222 const char * compat[] = { 223 "allwinner,sun50i-a64", 224 /* Cubietruck Plus triggers this problem as well. */ 225 "allwinner,sun8i-a83t", 226 NULL 227 }; 228 if (of_match_compatible(OF_finddevice("/"), compat)) { 229 prop_dictionary_set_bool(prop, "sun50i-a64-unstable-timer", true); 230 } 231 } 232 233 if (device_is_a(self, "sunxidrm")) { 234 if (get_bootconf_option(boot_args, "nomodeset", BOOTOPT_TYPE_BOOLEAN, &val)) 235 if (val) 236 prop_dictionary_set_bool(prop, "disabled", true); 237 } 238 } 239 240 static u_int 241 sunxi_platform_uart_freq(void) 242 { 243 return SUNXI_REF_FREQ; 244 } 245 246 static void 247 sunxi_platform_bootstrap(void) 248 { 249 arm_fdt_cpu_bootstrap(); 250 251 void *fdt_data = __UNCONST(fdtbus_get_data()); 252 const int chosen_off = fdt_path_offset(fdt_data, "/chosen"); 253 if (chosen_off < 0) 254 return; 255 256 if (match_bootconf_option(boot_args, "console", "fb")) { 257 const int framebuffer_off = 258 fdt_path_offset(fdt_data, "/chosen/framebuffer"); 259 if (framebuffer_off >= 0) { 260 const char *status = fdt_getprop(fdt_data, 261 framebuffer_off, "status", NULL); 262 if (status == NULL || strncmp(status, "ok", 2) == 0) { 263 fdt_setprop_string(fdt_data, chosen_off, 264 "stdout-path", "/chosen/framebuffer"); 265 } 266 } 267 } else if (match_bootconf_option(boot_args, "console", "serial")) { 268 fdt_setprop_string(fdt_data, chosen_off, 269 "stdout-path", "serial0:115200n8"); 270 } 271 } 272 273 static void 274 sun4i_platform_bootstrap(void) 275 { 276 bus_space_tag_t bst = &sunxi_bs_tag; 277 278 sunxi_platform_bootstrap(); 279 bus_space_map(bst, SUN4I_WDT_BASE, SUN4I_WDT_SIZE, 0, &reset_bsh); 280 } 281 282 static void 283 sun6i_platform_bootstrap(void) 284 { 285 bus_space_tag_t bst = &sunxi_bs_tag; 286 287 sunxi_platform_bootstrap(); 288 bus_space_map(bst, SUN6I_WDT_BASE, SUN6I_WDT_SIZE, 0, &reset_bsh); 289 } 290 291 static void 292 sun9i_platform_bootstrap(void) 293 { 294 bus_space_tag_t bst = &sunxi_bs_tag; 295 296 sunxi_platform_bootstrap(); 297 bus_space_map(bst, SUN9I_WDT_BASE, SUN9I_WDT_SIZE, 0, &reset_bsh); 298 } 299 300 static void 301 sun50i_h6_platform_bootstrap(void) 302 { 303 bus_space_tag_t bst = &sunxi_bs_tag; 304 305 sunxi_platform_bootstrap(); 306 bus_space_map(bst, SUN50I_H6_WDT_BASE, SUN50I_H6_WDT_SIZE, 0, &reset_bsh); 307 } 308 309 #if defined(SOC_SUNXI_MC) 310 static int 311 cpu_enable_sun8i_a83t(int phandle) 312 { 313 uint64_t mpidr; 314 315 fdtbus_get_reg64(phandle, 0, &mpidr, NULL); 316 317 return sun8i_a83t_smp_enable(mpidr); 318 } 319 ARM_CPU_METHOD(sun8i_a83t, "allwinner,sun8i-a83t-smp", cpu_enable_sun8i_a83t); 320 321 static int 322 cpu_enable_sun9i_a80(int phandle) 323 { 324 uint64_t mpidr; 325 326 fdtbus_get_reg64(phandle, 0, &mpidr, NULL); 327 328 return sun9i_a80_smp_enable(mpidr); 329 } 330 ARM_CPU_METHOD(sun9i_a80, "allwinner,sun9i-a80-smp", cpu_enable_sun9i_a80); 331 #endif 332 333 static void 334 sun4i_platform_reset(void) 335 { 336 bus_space_tag_t bst = &sunxi_bs_tag; 337 338 bus_space_write_4(bst, reset_bsh, SUN4I_WDT_CTRL, 339 SUN4I_WDT_CTRL_KEY | SUN4I_WDT_CTRL_RESTART); 340 for (;;) { 341 bus_space_write_4(bst, reset_bsh, SUN4I_WDT_MODE, 342 SUN4I_WDT_MODE_EN | SUN4I_WDT_MODE_RST_EN); 343 } 344 } 345 346 static void 347 sun4i_platform_delay(u_int n) 348 { 349 static bus_space_tag_t bst = &sunxi_bs_tag; 350 static bus_space_handle_t bsh = 0; 351 const long incs_per_us = SUNXI_REF_FREQ / 1000000; 352 long ticks = n * incs_per_us; 353 uint32_t cur, prev; 354 355 if (bsh == 0) { 356 bus_space_map(bst, SUN4I_TIMER_BASE, SUN4I_TIMER_SIZE, 0, &bsh); 357 358 /* Enable Timer 1 */ 359 bus_space_write_4(bst, bsh, SUN4I_TIMER_1_INTV_VALUE, ~0U); 360 bus_space_write_4(bst, bsh, SUN4I_TIMER_1_CTRL, 361 SUN4I_TIMER_1_CTRL_EN | 362 SUN4I_TIMER_1_CTRL_RELOAD | 363 __SHIFTIN(SUN4I_TIMER_1_CTRL_CLK_SRC_OSC24M, 364 SUN4I_TIMER_1_CTRL_CLK_SRC)); 365 } 366 367 prev = ~bus_space_read_4(bst, bsh, SUN4I_TIMER_1_VAL); 368 while (ticks > 0) { 369 cur = ~bus_space_read_4(bst, bsh, SUN4I_TIMER_1_VAL); 370 if (cur > prev) 371 ticks -= (cur - prev); 372 else 373 ticks -= (~0U - cur + prev); 374 prev = cur; 375 } 376 } 377 378 static void 379 sun6i_platform_reset(void) 380 { 381 bus_space_tag_t bst = &sunxi_bs_tag; 382 383 bus_space_write_4(bst, reset_bsh, SUN6I_WDT_CFG, SUN6I_WDT_CFG_SYS); 384 bus_space_write_4(bst, reset_bsh, SUN6I_WDT_MODE, SUN6I_WDT_MODE_EN); 385 } 386 387 static void 388 sun9i_platform_reset(void) 389 { 390 bus_space_tag_t bst = &sunxi_bs_tag; 391 392 bus_space_write_4(bst, reset_bsh, SUN9I_WDT_CFG, SUN9I_WDT_CFG_SYS); 393 bus_space_write_4(bst, reset_bsh, SUN9I_WDT_MODE, SUN9I_WDT_MODE_EN); 394 } 395 396 static void 397 sun50i_h6_platform_reset(void) 398 { 399 bus_space_tag_t bst = &sunxi_bs_tag; 400 401 bus_space_write_4(bst, reset_bsh, SUN50I_H6_WDT_CFG, SUN50I_H6_WDT_CFG_SYS); 402 bus_space_write_4(bst, reset_bsh, SUN50I_H6_WDT_MODE, SUN50I_H6_WDT_MODE_EN); 403 } 404 405 static const struct arm_platform sun4i_platform = { 406 .ap_devmap = sunxi_platform_devmap, 407 .ap_bootstrap = sun4i_platform_bootstrap, 408 .ap_init_attach_args = sunxi_platform_init_attach_args, 409 .ap_device_register = sunxi_platform_device_register, 410 .ap_reset = sun4i_platform_reset, 411 .ap_delay = sun4i_platform_delay, 412 .ap_uart_freq = sunxi_platform_uart_freq, 413 }; 414 415 ARM_PLATFORM(sun4i_a10, "allwinner,sun4i-a10", &sun4i_platform); 416 417 static const struct arm_platform sun5i_platform = { 418 .ap_devmap = sunxi_platform_devmap, 419 .ap_bootstrap = sun4i_platform_bootstrap, 420 .ap_init_attach_args = sunxi_platform_init_attach_args, 421 .ap_device_register = sunxi_platform_device_register, 422 .ap_reset = sun4i_platform_reset, 423 .ap_delay = sun4i_platform_delay, 424 .ap_uart_freq = sunxi_platform_uart_freq, 425 }; 426 427 ARM_PLATFORM(sun5i_a13, "allwinner,sun5i-a13", &sun5i_platform); 428 ARM_PLATFORM(sun5i_gr8, "nextthing,gr8", &sun5i_platform); 429 430 static const struct arm_platform sun6i_platform = { 431 .ap_devmap = sunxi_platform_devmap, 432 .ap_bootstrap = sun6i_platform_bootstrap, 433 .ap_init_attach_args = sunxi_platform_init_attach_args, 434 .ap_device_register = sunxi_platform_device_register, 435 .ap_reset = sun6i_platform_reset, 436 .ap_delay = gtmr_delay, 437 .ap_uart_freq = sunxi_platform_uart_freq, 438 .ap_mpstart = arm_fdt_cpu_mpstart, 439 }; 440 441 ARM_PLATFORM(sun6i_a31, "allwinner,sun6i-a31", &sun6i_platform); 442 443 static const struct arm_platform sun7i_platform = { 444 .ap_devmap = sunxi_platform_devmap, 445 .ap_bootstrap = sun4i_platform_bootstrap, 446 .ap_init_attach_args = sunxi_platform_init_attach_args, 447 .ap_device_register = sunxi_platform_device_register, 448 .ap_reset = sun4i_platform_reset, 449 .ap_delay = sun4i_platform_delay, 450 .ap_uart_freq = sunxi_platform_uart_freq, 451 .ap_mpstart = arm_fdt_cpu_mpstart, 452 }; 453 454 ARM_PLATFORM(sun7i_a20, "allwinner,sun7i-a20", &sun7i_platform); 455 456 static const struct arm_platform sun8i_platform = { 457 .ap_devmap = sunxi_platform_devmap, 458 .ap_bootstrap = sun6i_platform_bootstrap, 459 .ap_init_attach_args = sunxi_platform_init_attach_args, 460 .ap_device_register = sunxi_platform_device_register, 461 .ap_reset = sun6i_platform_reset, 462 .ap_delay = gtmr_delay, 463 .ap_uart_freq = sunxi_platform_uart_freq, 464 .ap_mpstart = arm_fdt_cpu_mpstart, 465 }; 466 467 ARM_PLATFORM(sun8i_h2plus, "allwinner,sun8i-h2-plus", &sun8i_platform); 468 ARM_PLATFORM(sun8i_h3, "allwinner,sun8i-h3", &sun8i_platform); 469 470 static const struct arm_platform sun8i_a83t_platform = { 471 .ap_devmap = sun8i_a83t_platform_devmap, 472 .ap_bootstrap = sun6i_platform_bootstrap, 473 .ap_init_attach_args = sunxi_platform_init_attach_args, 474 .ap_device_register = sunxi_platform_device_register, 475 .ap_reset = sun6i_platform_reset, 476 .ap_delay = gtmr_delay, 477 .ap_uart_freq = sunxi_platform_uart_freq, 478 .ap_mpstart = arm_fdt_cpu_mpstart, 479 }; 480 481 ARM_PLATFORM(sun8i_a83t, "allwinner,sun8i-a83t", &sun8i_a83t_platform); 482 483 static const struct arm_platform sun9i_platform = { 484 .ap_devmap = sun9i_a80_platform_devmap, 485 .ap_bootstrap = sun9i_platform_bootstrap, 486 .ap_init_attach_args = sunxi_platform_init_attach_args, 487 .ap_device_register = sunxi_platform_device_register, 488 .ap_reset = sun9i_platform_reset, 489 .ap_delay = gtmr_delay, 490 .ap_uart_freq = sunxi_platform_uart_freq, 491 .ap_mpstart = arm_fdt_cpu_mpstart, 492 }; 493 494 ARM_PLATFORM(sun9i_a80, "allwinner,sun9i-a80", &sun9i_platform); 495 496 static const struct arm_platform sun50i_platform = { 497 .ap_devmap = sunxi_platform_devmap, 498 .ap_bootstrap = sun6i_platform_bootstrap, 499 .ap_init_attach_args = sunxi_platform_init_attach_args, 500 .ap_device_register = sunxi_platform_device_register, 501 .ap_reset = sun6i_platform_reset, 502 .ap_delay = gtmr_delay, 503 .ap_uart_freq = sunxi_platform_uart_freq, 504 .ap_mpstart = arm_fdt_cpu_mpstart, 505 }; 506 507 ARM_PLATFORM(sun50i_a64, "allwinner,sun50i-a64", &sun50i_platform); 508 ARM_PLATFORM(sun50i_h5, "allwinner,sun50i-h5", &sun50i_platform); 509 510 static const struct arm_platform sun50i_h6_platform = { 511 .ap_devmap = sunxi_platform_devmap, 512 .ap_bootstrap = sun50i_h6_platform_bootstrap, 513 .ap_init_attach_args = sunxi_platform_init_attach_args, 514 .ap_device_register = sunxi_platform_device_register, 515 .ap_reset = sun50i_h6_platform_reset, 516 .ap_delay = gtmr_delay, 517 .ap_uart_freq = sunxi_platform_uart_freq, 518 .ap_mpstart = arm_fdt_cpu_mpstart, 519 }; 520 521 ARM_PLATFORM(sun50i_h6, "allwinner,sun50i-h6", &sun50i_h6_platform); 522
Indexes created Thu Sep 25 16:09:42 GMT 2025