sunxi_pwm.c revision 1.4 1 /* $NetBSD: sunxi_pwm.c,v 1.4 2021/01/18 02:35:49 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30
31 __KERNEL_RCSID(1, "$NetBSD: sunxi_pwm.c,v 1.4 2021/01/18 02:35:49 thorpej Exp $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/intr.h>
37 #include <sys/systm.h>
38 #include <sys/time.h>
39
40 #include <dev/pwm/pwmvar.h>
41
42 #include <dev/fdt/fdtvar.h>
43
44 #define PWM_CH_CTRL 0x00
45 #define PWM0_RDY __BIT(28)
46 #define PWM0_BYPASS __BIT(9)
47 #define PWM_CH0_PUL_START __BIT(8)
48 #define PWM_CHANNEL0_MODE __BIT(7)
49 #define SCLK_CH0_GATING __BIT(6)
50 #define PWM_CH0_ACT_STA __BIT(5)
51 #define PWM_CH0_EN __BIT(4)
52 #define PWM_CH0_PRESCAL __BITS(3,0)
53 #define PWM_CH0_PERIOD 0x04
54 #define PWM_CH0_ENTIRE_CYS __BITS(31,16)
55 #define PWM_CH0_ENTIRE_ACT_CYS __BITS(15,0)
56
57 enum sunxi_pwm_type {
58 PWM_A64 = 1,
59 };
60
61 static const struct device_compatible_entry compat_data[] = {
62 { .compat = "allwinner,sun50i-a64-pwm", .value = PWM_A64 },
63
64 { 0 }
65 };
66
67 struct sunxi_pwm_softc {
68 device_t sc_dev;
69 bus_space_tag_t sc_bst;
70 bus_space_handle_t sc_bsh;
71
72 struct pwm_controller sc_pwm;
73 struct pwm_config sc_conf;
74
75 u_int sc_clkfreq;
76 };
77
78 #define PWM_READ(sc, reg) \
79 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
80 #define PWM_WRITE(sc, reg, val) \
81 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
82
83 static pwm_tag_t
84 sunxi_pwm_get_tag(device_t dev, const void *data, size_t len)
85 {
86 struct sunxi_pwm_softc * const sc = device_private(dev);
87 const u_int *pwm = data;
88
89 if (len != 16)
90 return NULL;
91
92 const u_int index = be32toh(pwm[1]);
93 if (index != 0)
94 return NULL;
95
96 const u_int period = be32toh(pwm[2]);
97 const u_int polarity = be32toh(pwm[3]);
98
99 sc->sc_conf.period = period;
100 sc->sc_conf.polarity = polarity ? PWM_ACTIVE_LOW : PWM_ACTIVE_HIGH;
101
102 return &sc->sc_pwm;
103 }
104
105 static struct fdtbus_pwm_controller_func sunxi_pwm_funcs = {
106 .get_tag = sunxi_pwm_get_tag
107 };
108
109 static int
110 sunxi_pwm_enable(pwm_tag_t pwm, bool enable)
111 {
112 struct sunxi_pwm_softc * const sc = device_private(pwm->pwm_dev);
113 uint32_t ctrl, octrl;
114
115 octrl = ctrl = PWM_READ(sc, PWM_CH_CTRL);
116 if (enable)
117 ctrl |= (PWM_CH0_EN | SCLK_CH0_GATING);
118 else
119 ctrl &= ~(PWM_CH0_EN | SCLK_CH0_GATING);
120
121 if (ctrl != octrl)
122 PWM_WRITE(sc, PWM_CH_CTRL, ctrl);
123
124 return 0;
125 }
126
127 static int
128 sunxi_pwm_get_config(pwm_tag_t pwm, struct pwm_config *conf)
129 {
130 struct sunxi_pwm_softc * const sc = device_private(pwm->pwm_dev);
131 uint32_t ctrl, ch_period;
132
133 ctrl = PWM_READ(sc, PWM_CH_CTRL);
134 ch_period = PWM_READ(sc, PWM_CH0_PERIOD);
135
136 const uint64_t rate = sc->sc_clkfreq / 120;
137 const u_int cycles = __SHIFTOUT(ch_period, PWM_CH0_ENTIRE_CYS) + 1;
138 const u_int act_cycles = __SHIFTOUT(ch_period, PWM_CH0_ENTIRE_ACT_CYS);
139
140 conf->polarity = (ctrl & PWM_CH0_ACT_STA) ? PWM_ACTIVE_HIGH : PWM_ACTIVE_LOW;
141 conf->period = (u_int)(((uint64_t)cycles * 1000000000) / rate);
142 conf->duty_cycle = (u_int)(((uint64_t)act_cycles * 1000000000) / rate);
143
144 return 0;
145 }
146
147 static int
148 sunxi_pwm_set_config(pwm_tag_t pwm, const struct pwm_config *conf)
149 {
150 struct sunxi_pwm_softc * const sc = device_private(pwm->pwm_dev);
151 uint32_t ctrl, ch_period;
152
153 ctrl = PWM_READ(sc, PWM_CH_CTRL);
154 if (ctrl & PWM0_RDY)
155 return EBUSY;
156
157 ctrl &= ~PWM0_BYPASS; /* Prescaler /120 = 200 kHz */
158 ctrl &= ~PWM_CH0_PRESCAL;
159 ctrl |= __SHIFTIN(0, PWM_CH0_PRESCAL);
160
161 ctrl &= ~PWM_CHANNEL0_MODE; /* Cycle mode */
162 if (conf->polarity == PWM_ACTIVE_HIGH)
163 ctrl |= PWM_CH0_ACT_STA;
164 else
165 ctrl &= ~PWM_CH0_ACT_STA;
166
167 const uint64_t rate = sc->sc_clkfreq / 120;
168 const u_int cycles = (u_int)((conf->period * rate) / 1000000000);
169 const u_int act_cycles = (u_int)((conf->duty_cycle * rate) / 1000000000);
170
171 ch_period = __SHIFTIN(cycles - 1, PWM_CH0_ENTIRE_CYS);
172 ch_period |= __SHIFTIN(act_cycles, PWM_CH0_ENTIRE_ACT_CYS);
173
174 PWM_WRITE(sc, PWM_CH0_PERIOD, ch_period);
175 PWM_WRITE(sc, PWM_CH_CTRL, ctrl);
176
177 sc->sc_conf = *conf;
178
179 return 0;
180 }
181
182 static int
183 sunxi_pwm_match(device_t parent, cfdata_t cf, void *aux)
184 {
185 struct fdt_attach_args * const faa = aux;
186
187 return of_match_compat_data(faa->faa_phandle, compat_data);
188 }
189
190 static void
191 sunxi_pwm_attach(device_t parent, device_t self, void *aux)
192 {
193 struct sunxi_pwm_softc * const sc = device_private(self);
194 struct fdt_attach_args * const faa = aux;
195 const int phandle = faa->faa_phandle;
196 struct clk *clk;
197 bus_addr_t addr;
198 bus_size_t size;
199 int error;
200
201 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
202 aprint_error(": couldn't get registers\n");
203 return;
204 }
205
206 clk = fdtbus_clock_get_index(phandle, 0);
207 if (clk == NULL) {
208 aprint_error(": couldn't get clock\n");
209 return;
210 }
211
212 sc->sc_dev = self;
213 sc->sc_clkfreq = clk_get_rate(clk);
214 sc->sc_bst = faa->faa_bst;
215 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
216 if (error) {
217 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d",
218 addr, error);
219 return;
220 }
221
222 aprint_naive("\n");
223 aprint_normal(": PWM\n");
224
225 sc->sc_pwm.pwm_enable = sunxi_pwm_enable;
226 sc->sc_pwm.pwm_get_config = sunxi_pwm_get_config;
227 sc->sc_pwm.pwm_set_config = sunxi_pwm_set_config;
228 sc->sc_pwm.pwm_dev = self;
229
230 fdtbus_register_pwm_controller(self, phandle,
231 &sunxi_pwm_funcs);
232 }
233
234 CFATTACH_DECL_NEW(sunxi_pwm, sizeof(struct sunxi_pwm_softc),
235 sunxi_pwm_match, sunxi_pwm_attach, NULL, NULL);
236