sunxi_rsb.c revision 1.14.4.1
1 /* $NetBSD: sunxi_rsb.c,v 1.14.4.1 2021/05/19 03:14:24 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2014-2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_rsb.c,v 1.14.4.1 2021/05/19 03:14:24 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #include <arm/sunxi/sunxi_rsb.h> 46 47 enum sunxi_rsb_type { 48 SUNXI_P2WI, 49 SUNXI_RSB, 50 }; 51 52 static const struct device_compatible_entry compat_data[] = { 53 { .compat = "allwinner,sun6i-a31-p2wi", .value = SUNXI_P2WI }, 54 { .compat = "allwinner,sun8i-a23-rsb", .value = SUNXI_RSB }, 55 DEVICE_COMPAT_EOL 56 }; 57 58 #define RSB_ADDR_PMIC_PRIMARY 0x3a3 59 #define RSB_ADDR_PMIC_SECONDARY 0x745 60 #define RSB_ADDR_PERIPH_IC 0xe89 61 62 /* 63 * Device address to Run-time address mappings. 64 * 65 * Run-time address (RTA) is an 8-bit value used to address the device during 66 * a read or write transaction. The following are valid RTAs: 67 * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff 68 * 69 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC, 70 * and 0x4e for the peripheral IC (where applicable). 71 */ 72 static const struct { 73 uint16_t addr; 74 uint8_t rta; 75 } rsb_rtamap[] = { 76 { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d }, 77 { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a }, 78 { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e }, 79 { .addr = 0, .rta = 0 } 80 }; 81 82 struct sunxi_rsb_softc { 83 device_t sc_dev; 84 bus_space_tag_t sc_bst; 85 bus_space_handle_t sc_bsh; 86 enum sunxi_rsb_type sc_type; 87 struct i2c_controller sc_ic; 88 kmutex_t sc_intr_lock; 89 kcondvar_t sc_intr_wait; 90 device_t sc_i2cdev; 91 void *sc_ih; 92 uint32_t sc_stat; 93 bool sc_busy; 94 95 uint16_t sc_rsb_last_da; 96 }; 97 98 #define RSB_READ(sc, reg) \ 99 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 100 #define RSB_WRITE(sc, reg, val) \ 101 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 102 103 static int sunxi_rsb_exec(void *, i2c_op_t, i2c_addr_t, const void *, 104 size_t, void *, size_t, int); 105 106 static int sunxi_rsb_intr(void *); 107 static int sunxi_rsb_wait(struct sunxi_rsb_softc *, int); 108 static int sunxi_rsb_rsb_config(struct sunxi_rsb_softc *, 109 uint8_t, i2c_addr_t, int); 110 111 static int sunxi_rsb_match(device_t, cfdata_t, void *); 112 static void sunxi_rsb_attach(device_t, device_t, void *); 113 114 CFATTACH_DECL_NEW(sunxi_rsb, sizeof(struct sunxi_rsb_softc), 115 sunxi_rsb_match, sunxi_rsb_attach, NULL, NULL); 116 117 static int 118 sunxi_rsb_match(device_t parent, cfdata_t cf, void *aux) 119 { 120 struct fdt_attach_args * const faa = aux; 121 122 return of_compatible_match(faa->faa_phandle, compat_data); 123 } 124 125 static void 126 sunxi_rsb_attach(device_t parent, device_t self, void *aux) 127 { 128 struct sunxi_rsb_softc * const sc = device_private(self); 129 struct fdt_attach_args * const faa = aux; 130 const int phandle = faa->faa_phandle; 131 struct fdtbus_reset *rst; 132 struct clk *clk; 133 char intrstr[128]; 134 bus_addr_t addr; 135 bus_size_t size; 136 137 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 138 aprint_error(": couldn't get registers\n"); 139 return; 140 } 141 142 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 143 aprint_error(": couldn't decode interrupt\n"); 144 return; 145 } 146 147 if ((clk = fdtbus_clock_get_index(phandle, 0)) != NULL) 148 if (clk_enable(clk) != 0) { 149 aprint_error(": couldn't enable clock\n"); 150 return; 151 } 152 if ((rst = fdtbus_reset_get_index(phandle, 0)) != NULL) 153 if (fdtbus_reset_deassert(rst) != 0) { 154 aprint_error(": couldn't de-assert reset\n"); 155 return; 156 } 157 158 sc->sc_dev = self; 159 sc->sc_type = of_compatible_lookup(phandle, compat_data)->value; 160 sc->sc_bst = faa->faa_bst; 161 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 162 aprint_error(": couldn't map registers\n"); 163 return; 164 } 165 166 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 167 cv_init(&sc->sc_intr_wait, "sunxirsb"); 168 169 aprint_naive("\n"); 170 aprint_normal(": %s\n", sc->sc_type == SUNXI_P2WI ? "P2WI" : "RSB"); 171 172 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_VM, 0, 173 sunxi_rsb_intr, sc, device_xname(self)); 174 if (sc->sc_ih == NULL) { 175 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 176 intrstr); 177 return; 178 } 179 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 180 181 iic_tag_init(&sc->sc_ic); 182 sc->sc_ic.ic_cookie = sc; 183 sc->sc_ic.ic_exec = sunxi_rsb_exec; 184 185 fdtbus_register_i2c_controller(&sc->sc_ic, phandle); 186 187 struct i2cbus_attach_args iba = { 188 .iba_tag = &sc->sc_ic, 189 }; 190 config_found(self, &iba, iicbus_print, 191 CFARG_DEVHANDLE, device_handle(self), 192 CFARG_EOL); 193 } 194 195 static int 196 sunxi_rsb_intr(void *priv) 197 { 198 struct sunxi_rsb_softc *sc = priv; 199 uint32_t stat; 200 201 stat = RSB_READ(sc, RSB_STAT_REG); 202 if ((stat & RSB_STAT_MASK) == 0) 203 return 0; 204 205 RSB_WRITE(sc, RSB_STAT_REG, stat & RSB_STAT_MASK); 206 207 mutex_enter(&sc->sc_intr_lock); 208 sc->sc_stat |= stat; 209 cv_broadcast(&sc->sc_intr_wait); 210 mutex_exit(&sc->sc_intr_lock); 211 212 return 1; 213 } 214 215 static int 216 sunxi_rsb_soft_reset(struct sunxi_rsb_softc *sc) 217 { 218 int retry = 1000; 219 220 RSB_WRITE(sc, RSB_CTRL_REG, RSB_CTRL_SOFT_RESET); 221 while (--retry > 0) { 222 if ((RSB_READ(sc, RSB_CTRL_REG) & RSB_CTRL_SOFT_RESET) == 0) 223 break; 224 delay(10); 225 } 226 if (retry == 0) 227 return EIO; 228 229 return 0; 230 } 231 232 static int 233 sunxi_rsb_wait(struct sunxi_rsb_softc *sc, int flags) 234 { 235 int error = 0, retry; 236 237 /* Wait up to 5 seconds for a transfer to complete */ 238 sc->sc_stat = 0; 239 for (retry = (flags & I2C_F_POLL) ? 100 : 5; retry > 0; retry--) { 240 if (flags & I2C_F_POLL) { 241 sc->sc_stat |= RSB_READ(sc, RSB_STAT_REG); 242 } else { 243 error = cv_timedwait(&sc->sc_intr_wait, 244 &sc->sc_intr_lock, hz); 245 if (error && error != EWOULDBLOCK) { 246 break; 247 } 248 } 249 if (sc->sc_stat & RSB_STAT_MASK) { 250 break; 251 } 252 if (flags & I2C_F_POLL) { 253 delay(10000); 254 } 255 } 256 if (retry == 0) 257 error = EAGAIN; 258 259 if (flags & I2C_F_POLL) { 260 RSB_WRITE(sc, RSB_STAT_REG, 261 sc->sc_stat & RSB_STAT_MASK); 262 } 263 264 if (error) { 265 /* Abort transaction */ 266 device_printf(sc->sc_dev, "transfer timeout, error = %d\n", 267 error); 268 RSB_WRITE(sc, RSB_CTRL_REG, 269 RSB_CTRL_ABORT_TRANS); 270 return error; 271 } 272 273 if (sc->sc_stat & RSB_STAT_LOAD_BSY) { 274 device_printf(sc->sc_dev, "transfer busy\n"); 275 return EBUSY; 276 } 277 if (sc->sc_stat & RSB_STAT_TRANS_ERR) { 278 device_printf(sc->sc_dev, "transfer error, id 0x%02" PRIx64 279 "\n", __SHIFTOUT(sc->sc_stat, RSB_STAT_TRANS_ERR_ID)); 280 return EIO; 281 } 282 283 return 0; 284 } 285 286 static int 287 sunxi_rsb_rsb_config(struct sunxi_rsb_softc *sc, uint8_t rta, i2c_addr_t da, 288 int flags) 289 { 290 uint32_t dar, ctrl; 291 292 KASSERT(mutex_owned(&sc->sc_intr_lock)); 293 294 RSB_WRITE(sc, RSB_STAT_REG, 295 RSB_READ(sc, RSB_STAT_REG) & RSB_STAT_MASK); 296 297 dar = __SHIFTIN(rta, RSB_DAR_RTA); 298 dar |= __SHIFTIN(da, RSB_DAR_DA); 299 RSB_WRITE(sc, RSB_DAR_REG, dar); 300 RSB_WRITE(sc, RSB_CMD_REG, RSB_CMD_IDX_SRTA); 301 302 /* Make sure the controller is idle */ 303 ctrl = RSB_READ(sc, RSB_CTRL_REG); 304 if (ctrl & RSB_CTRL_START_TRANS) { 305 device_printf(sc->sc_dev, "device is busy\n"); 306 return EBUSY; 307 } 308 309 /* Start the transfer */ 310 RSB_WRITE(sc, RSB_CTRL_REG, 311 ctrl | RSB_CTRL_START_TRANS); 312 313 return sunxi_rsb_wait(sc, flags); 314 } 315 316 static int 317 sunxi_rsb_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 318 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 319 { 320 struct sunxi_rsb_softc *sc = priv; 321 uint32_t dlen, ctrl; 322 uint8_t rta; 323 int error, i; 324 325 if (cmdlen != 1 || (len != 1 && len != 2 && len != 4)) 326 return EINVAL; 327 328 mutex_enter(&sc->sc_intr_lock); 329 330 error = sunxi_rsb_soft_reset(sc); 331 if (error != 0) { 332 mutex_exit(&sc->sc_intr_lock); 333 device_printf(sc->sc_dev, "soft reset timed out\n"); 334 return error; 335 } 336 337 if ((flags & I2C_F_POLL) == 0) { 338 /* Enable interrupts */ 339 RSB_WRITE(sc, RSB_INTE_REG, 340 RSB_INTE_LOAD_BSY_ENB | 341 RSB_INTE_TRANS_ERR_ENB | 342 RSB_INTE_TRANS_OVER_ENB); 343 RSB_WRITE(sc, RSB_CTRL_REG, 344 RSB_CTRL_GLOBAL_INT_ENB); 345 } 346 347 if (sc->sc_type == SUNXI_RSB && sc->sc_rsb_last_da != addr) { 348 /* Lookup run-time address for given device address */ 349 for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++) 350 if (rsb_rtamap[i].addr == addr) { 351 rta = rsb_rtamap[i].rta; 352 break; 353 } 354 if (rta == 0) { 355 mutex_exit(&sc->sc_intr_lock); 356 device_printf(sc->sc_dev, 357 "RTA not known for address %#x\n", addr); 358 return ENXIO; 359 } 360 error = sunxi_rsb_rsb_config(sc, rta, addr, flags); 361 if (error) { 362 device_printf(sc->sc_dev, 363 "SRTA failed, flags = %x, error = %d\n", 364 flags, error); 365 sc->sc_rsb_last_da = 0; 366 goto done; 367 } 368 369 sc->sc_rsb_last_da = addr; 370 } 371 372 /* Data byte register */ 373 RSB_WRITE(sc, RSB_DADDR0_REG, *(const uint8_t *)cmdbuf); 374 375 if (I2C_OP_WRITE_P(op)) { 376 uint8_t *pbuf = buf; 377 uint32_t data; 378 /* Write data */ 379 switch (len) { 380 case 1: 381 data = pbuf[0]; 382 break; 383 case 2: 384 data = pbuf[0] | (pbuf[1] << 8); 385 break; 386 case 4: 387 data = pbuf[0] | (pbuf[1] << 8) | 388 (pbuf[2] << 16) | (pbuf[3] << 24); 389 break; 390 default: 391 error = EINVAL; 392 goto done; 393 } 394 RSB_WRITE(sc, RSB_DATA0_REG, data); 395 } 396 397 if (sc->sc_type == SUNXI_RSB) { 398 uint8_t cmd; 399 if (I2C_OP_WRITE_P(op)) { 400 switch (len) { 401 case 1: cmd = RSB_CMD_IDX_WR8; break; 402 case 2: cmd = RSB_CMD_IDX_WR16; break; 403 case 4: cmd = RSB_CMD_IDX_WR32; break; 404 default: error = EINVAL; goto done; 405 } 406 } else { 407 switch (len) { 408 case 1: cmd = RSB_CMD_IDX_RD8; break; 409 case 2: cmd = RSB_CMD_IDX_RD16; break; 410 case 4: cmd = RSB_CMD_IDX_RD32; break; 411 default: error = EINVAL; goto done; 412 } 413 } 414 RSB_WRITE(sc, RSB_CMD_REG, cmd); 415 } 416 417 /* Program data length register; if reading, set read/write bit */ 418 dlen = __SHIFTIN(len - 1, RSB_DLEN_ACCESS_LENGTH); 419 if (I2C_OP_READ_P(op)) { 420 dlen |= RSB_DLEN_READ_WRITE_FLAG; 421 } 422 RSB_WRITE(sc, RSB_DLEN_REG, dlen); 423 424 /* Make sure the controller is idle */ 425 ctrl = RSB_READ(sc, RSB_CTRL_REG); 426 if (ctrl & RSB_CTRL_START_TRANS) { 427 device_printf(sc->sc_dev, "device is busy\n"); 428 error = EBUSY; 429 goto done; 430 } 431 432 /* Start the transfer */ 433 RSB_WRITE(sc, RSB_CTRL_REG, 434 ctrl | RSB_CTRL_START_TRANS); 435 436 error = sunxi_rsb_wait(sc, flags); 437 if (error) 438 goto done; 439 440 if (I2C_OP_READ_P(op)) { 441 uint32_t data = RSB_READ(sc, RSB_DATA0_REG); 442 switch (len) { 443 case 4: 444 *(uint32_t *)buf = data; 445 break; 446 case 2: 447 *(uint16_t *)buf = data & 0xffff; 448 break; 449 case 1: 450 *(uint8_t *)buf = data & 0xff; 451 break; 452 default: 453 error = EINVAL; 454 goto done; 455 } 456 } 457 458 error = 0; 459 460 done: 461 RSB_WRITE(sc, RSB_CTRL_REG, 0); 462 mutex_exit(&sc->sc_intr_lock); 463 464 return error; 465 } 466
Indexes created Wed Oct 22 13:09:56 GMT 2025