sunxi_sramc.c revision 1.1.2.2
1 /* $NetBSD: sunxi_sramc.c,v 1.1.2.2 2017/12/03 11:35:56 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_sramc.c,v 1.1.2.2 2017/12/03 11:35:56 jdolecek Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kmem.h> 38 39 #include <dev/fdt/fdtvar.h> 40 41 #include <arm/sunxi/sunxi_sramc.h> 42 43 static const char * compatible[] = { 44 "allwinner,sun4i-a10-sram-controller", 45 NULL 46 }; 47 48 static const struct sunxi_sramc_area { 49 const char *compatible; 50 const char *desc; 51 bus_size_t reg; 52 uint32_t mask; 53 } sunxi_sramc_areas[] = { 54 { "allwinner,sun4i-a10-sram-a3-a4", 55 "SRAM A3/A4", 56 0x04, __BITS(5,4) }, 57 { "allwinner,sun4i-a10-sram-d", 58 "SRAM D", 59 0x04, __BIT(0) } 60 }; 61 62 struct sunxi_sramc_node { 63 int phandle; 64 const struct sunxi_sramc_area *area; 65 TAILQ_ENTRY(sunxi_sramc_node) nodes; 66 }; 67 68 struct sunxi_sramc_softc { 69 device_t sc_dev; 70 int sc_phandle; 71 bus_space_tag_t sc_bst; 72 bus_space_handle_t sc_bsh; 73 TAILQ_HEAD(, sunxi_sramc_node) sc_nodes; 74 }; 75 76 static struct sunxi_sramc_softc *sramc_softc = NULL; 77 78 #define SRAMC_READ(sc, reg) \ 79 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 80 #define SRAMC_WRITE(sc, reg, val) \ 81 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 82 83 static void 84 sunxi_sramc_init_mmio(struct sunxi_sramc_softc *sc, int phandle) 85 { 86 struct sunxi_sramc_node *node; 87 int child, i; 88 89 for (child = OF_child(phandle); child; child = OF_peer(child)) 90 for (i = 0; i < __arraycount(sunxi_sramc_areas); i++) { 91 const char * area_compatible[] = { sunxi_sramc_areas[i].compatible, NULL }; 92 if (of_match_compatible(child, area_compatible)) { 93 node = kmem_alloc(sizeof(*node), KM_SLEEP); 94 node->phandle = child; 95 node->area = &sunxi_sramc_areas[i]; 96 TAILQ_INSERT_TAIL(&sc->sc_nodes, node, nodes); 97 aprint_verbose_dev(sc->sc_dev, "area: %s\n", node->area->desc); 98 break; 99 } 100 } 101 } 102 103 static void 104 sunxi_sramc_init(struct sunxi_sramc_softc *sc) 105 { 106 const char * mmio_compatible[] = { "mmio-sram", NULL }; 107 int child; 108 109 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 110 if (!of_match_compatible(child, mmio_compatible)) 111 continue; 112 sunxi_sramc_init_mmio(sc, child); 113 } 114 } 115 116 static int 117 sunxi_sramc_match(device_t parent, cfdata_t cf, void *aux) 118 { 119 struct fdt_attach_args * const faa = aux; 120 121 return of_match_compatible(faa->faa_phandle, compatible); 122 } 123 124 static void 125 sunxi_sramc_attach(device_t parent, device_t self, void *aux) 126 { 127 struct sunxi_sramc_softc * const sc = device_private(self); 128 struct fdt_attach_args * const faa = aux; 129 const int phandle = faa->faa_phandle; 130 bus_addr_t addr; 131 bus_size_t size; 132 133 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 134 aprint_error(": couldn't get registers\n"); 135 return; 136 } 137 138 sc->sc_dev = self; 139 sc->sc_phandle = phandle; 140 sc->sc_bst = faa->faa_bst; 141 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 142 aprint_error(": couldn't map registers\n"); 143 return; 144 } 145 TAILQ_INIT(&sc->sc_nodes); 146 147 aprint_naive("\n"); 148 aprint_normal(": SRAM Controller\n"); 149 150 sunxi_sramc_init(sc); 151 152 KASSERT(sramc_softc == NULL); 153 sramc_softc = sc; 154 } 155 156 CFATTACH_DECL_NEW(sunxi_sramc, sizeof(struct sunxi_sramc_softc), 157 sunxi_sramc_match, sunxi_sramc_attach, NULL, NULL); 158 159 static int 160 sunxi_sramc_map(const int node_phandle, u_int config) 161 { 162 struct sunxi_sramc_softc * const sc = sramc_softc; 163 struct sunxi_sramc_node *node; 164 uint32_t val; 165 166 if (sc == NULL) 167 return ENXIO; 168 169 TAILQ_FOREACH(node, &sc->sc_nodes, nodes) 170 if (node->phandle == node_phandle) { 171 if (config > __SHIFTOUT_MASK(node->area->mask)) 172 return ERANGE; 173 val = SRAMC_READ(sc, node->area->reg); 174 val &= ~node->area->mask; 175 val |= __SHIFTIN(config, node->area->mask); 176 SRAMC_WRITE(sc, node->area->reg, val); 177 return 0; 178 } 179 180 return EINVAL; 181 } 182 183 int 184 sunxi_sramc_claim(const int phandle) 185 { 186 const u_int *data; 187 int len; 188 189 data = fdtbus_get_prop(phandle, "allwinner,sram", &len); 190 if (data == NULL) 191 return ENOENT; 192 if (len != 8) 193 return EIO; 194 195 const int node_phandle = fdtbus_get_phandle_from_native(be32toh(data[0])); 196 const u_int config = be32toh(data[1]); 197 198 return sunxi_sramc_map(node_phandle, config); 199 } 200
Indexes created Wed Oct 22 13:09:56 GMT 2025