sunxi_sramc.c revision 1.1.4.1
1 /* $NetBSD: sunxi_sramc.c,v 1.1.4.1 2019/01/26 22:00:01 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_sramc.c,v 1.1.4.1 2019/01/26 22:00:01 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kmem.h> 38 #include <sys/mutex.h> 39 40 #include <dev/fdt/fdtvar.h> 41 #include <dev/fdt/syscon.h> 42 43 #include <arm/sunxi/sunxi_sramc.h> 44 45 static const char * compatible[] = { 46 "allwinner,sun4i-a10-sram-controller", 47 "allwinner,sun50i-a64-system-control", 48 "allwinner,sun50i-h6-system-control", 49 NULL 50 }; 51 52 static const struct sunxi_sramc_area { 53 const char *compatible; 54 const char *desc; 55 bus_size_t reg; 56 uint32_t mask; 57 u_int flags; 58 #define SUNXI_SRAMC_F_SWAP __BIT(0) 59 } sunxi_sramc_areas[] = { 60 { "allwinner,sun4i-a10-sram-a3-a4", 61 "SRAM A3/A4", 62 0x04, __BITS(5,4), 0 }, 63 { "allwinner,sun4i-a10-sram-d", 64 "SRAM D", 65 0x04, __BIT(0), 0 }, 66 { "allwinner,sun50i-a64-sram-c", 67 "SRAM C", 68 0x04, __BIT(24), SUNXI_SRAMC_F_SWAP }, 69 }; 70 71 struct sunxi_sramc_node { 72 int phandle; 73 const struct sunxi_sramc_area *area; 74 TAILQ_ENTRY(sunxi_sramc_node) nodes; 75 }; 76 77 struct sunxi_sramc_softc { 78 device_t sc_dev; 79 int sc_phandle; 80 bus_space_tag_t sc_bst; 81 bus_space_handle_t sc_bsh; 82 kmutex_t sc_lock; 83 struct syscon sc_syscon; 84 TAILQ_HEAD(, sunxi_sramc_node) sc_nodes; 85 }; 86 87 static struct sunxi_sramc_softc *sramc_softc = NULL; 88 89 #define SRAMC_READ(sc, reg) \ 90 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 91 #define SRAMC_WRITE(sc, reg, val) \ 92 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 93 94 static void 95 sunxi_sramc_init_mmio(struct sunxi_sramc_softc *sc, int phandle) 96 { 97 struct sunxi_sramc_node *node; 98 int child, i; 99 100 for (child = OF_child(phandle); child; child = OF_peer(child)) 101 for (i = 0; i < __arraycount(sunxi_sramc_areas); i++) { 102 const char * area_compatible[] = { sunxi_sramc_areas[i].compatible, NULL }; 103 if (of_match_compatible(child, area_compatible)) { 104 node = kmem_alloc(sizeof(*node), KM_SLEEP); 105 node->phandle = child; 106 node->area = &sunxi_sramc_areas[i]; 107 TAILQ_INSERT_TAIL(&sc->sc_nodes, node, nodes); 108 aprint_verbose_dev(sc->sc_dev, "area: %s\n", node->area->desc); 109 break; 110 } 111 } 112 } 113 114 static void 115 sunxi_sramc_init(struct sunxi_sramc_softc *sc) 116 { 117 const char * mmio_compatible[] = { "mmio-sram", NULL }; 118 int child; 119 120 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 121 if (!of_match_compatible(child, mmio_compatible)) 122 continue; 123 sunxi_sramc_init_mmio(sc, child); 124 } 125 } 126 127 static void 128 sunxi_sramc_lock(void *priv) 129 { 130 struct sunxi_sramc_softc * const sc = priv; 131 132 mutex_enter(&sc->sc_lock); 133 } 134 135 static void 136 sunxi_sramc_unlock(void *priv) 137 { 138 struct sunxi_sramc_softc * const sc = priv; 139 140 mutex_exit(&sc->sc_lock); 141 } 142 143 static uint32_t 144 sunxi_sramc_read_4(void *priv, bus_size_t reg) 145 { 146 struct sunxi_sramc_softc * const sc = priv; 147 148 KASSERT(mutex_owned(&sc->sc_lock)); 149 150 return SRAMC_READ(sc, reg); 151 } 152 153 static void 154 sunxi_sramc_write_4(void *priv, bus_size_t reg, uint32_t val) 155 { 156 struct sunxi_sramc_softc * const sc = priv; 157 158 KASSERT(mutex_owned(&sc->sc_lock)); 159 160 SRAMC_WRITE(sc, reg, val); 161 } 162 163 static int 164 sunxi_sramc_match(device_t parent, cfdata_t cf, void *aux) 165 { 166 struct fdt_attach_args * const faa = aux; 167 168 return of_match_compatible(faa->faa_phandle, compatible); 169 } 170 171 static void 172 sunxi_sramc_attach(device_t parent, device_t self, void *aux) 173 { 174 struct sunxi_sramc_softc * const sc = device_private(self); 175 struct fdt_attach_args * const faa = aux; 176 const int phandle = faa->faa_phandle; 177 bus_addr_t addr; 178 bus_size_t size; 179 180 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 181 aprint_error(": couldn't get registers\n"); 182 return; 183 } 184 185 sc->sc_dev = self; 186 sc->sc_phandle = phandle; 187 sc->sc_bst = faa->faa_bst; 188 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 189 aprint_error(": couldn't map registers\n"); 190 return; 191 } 192 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 193 TAILQ_INIT(&sc->sc_nodes); 194 195 aprint_naive("\n"); 196 aprint_normal(": SRAM Controller\n"); 197 198 sunxi_sramc_init(sc); 199 200 KASSERT(sramc_softc == NULL); 201 sramc_softc = sc; 202 203 sc->sc_syscon.priv = sc; 204 sc->sc_syscon.lock = sunxi_sramc_lock; 205 sc->sc_syscon.unlock = sunxi_sramc_unlock; 206 sc->sc_syscon.read_4 = sunxi_sramc_read_4; 207 sc->sc_syscon.write_4 = sunxi_sramc_write_4; 208 fdtbus_register_syscon(self, phandle, &sc->sc_syscon); 209 } 210 211 CFATTACH_DECL_NEW(sunxi_sramc, sizeof(struct sunxi_sramc_softc), 212 sunxi_sramc_match, sunxi_sramc_attach, NULL, NULL); 213 214 static int 215 sunxi_sramc_map(const int node_phandle, u_int config) 216 { 217 struct sunxi_sramc_softc * const sc = sramc_softc; 218 struct sunxi_sramc_node *node; 219 uint32_t val; 220 221 if (sc == NULL) 222 return ENXIO; 223 224 TAILQ_FOREACH(node, &sc->sc_nodes, nodes) 225 if (node->phandle == node_phandle) { 226 if (config > __SHIFTOUT_MASK(node->area->mask)) 227 return ERANGE; 228 if ((node->area->flags & SUNXI_SRAMC_F_SWAP) != 0) 229 config = !config; 230 val = SRAMC_READ(sc, node->area->reg); 231 val &= ~node->area->mask; 232 val |= __SHIFTIN(config, node->area->mask); 233 SRAMC_WRITE(sc, node->area->reg, val); 234 return 0; 235 } 236 237 return EINVAL; 238 } 239 240 int 241 sunxi_sramc_claim(const int phandle) 242 { 243 const u_int *data; 244 int len; 245 246 data = fdtbus_get_prop(phandle, "allwinner,sram", &len); 247 if (data == NULL) 248 return ENOENT; 249 if (len != 8) 250 return EIO; 251 252 const int node_phandle = fdtbus_get_phandle_from_native(be32toh(data[0])); 253 const u_int config = be32toh(data[1]); 254 255 return sunxi_sramc_map(node_phandle, config); 256 } 257
Indexes created Wed Oct 22 00:09:40 GMT 2025