sunxi_sramc.c revision 1.1.6.1
1 /* $NetBSD: sunxi_sramc.c,v 1.1.6.1 2019/06/10 22:05:57 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_sramc.c,v 1.1.6.1 2019/06/10 22:05:57 christos Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kmem.h> 38 #include <sys/mutex.h> 39 40 #include <dev/fdt/fdtvar.h> 41 #include <dev/fdt/syscon.h> 42 43 #include <arm/sunxi/sunxi_sramc.h> 44 45 static const char * compatible[] = { 46 "allwinner,sun4i-a10-sram-controller", /* old compat string */ 47 "allwinner,sun4i-a10-system-control", 48 "allwinner,sun8i-h3-system-control", 49 "allwinner,sun50i-a64-system-control", 50 "allwinner,sun50i-h6-system-control", 51 NULL 52 }; 53 54 static const struct sunxi_sramc_area { 55 const char *compatible; 56 const char *desc; 57 bus_size_t reg; 58 uint32_t mask; 59 u_int flags; 60 #define SUNXI_SRAMC_F_SWAP __BIT(0) 61 } sunxi_sramc_areas[] = { 62 { "allwinner,sun4i-a10-sram-a3-a4", 63 "SRAM A3/A4", 64 0x04, __BITS(5,4), 0 }, 65 { "allwinner,sun4i-a10-sram-d", 66 "SRAM D", 67 0x04, __BIT(0), 0 }, 68 { "allwinner,sun50i-a64-sram-c", 69 "SRAM C", 70 0x04, __BIT(24), SUNXI_SRAMC_F_SWAP }, 71 }; 72 73 struct sunxi_sramc_node { 74 int phandle; 75 const struct sunxi_sramc_area *area; 76 TAILQ_ENTRY(sunxi_sramc_node) nodes; 77 }; 78 79 struct sunxi_sramc_softc { 80 device_t sc_dev; 81 int sc_phandle; 82 bus_space_tag_t sc_bst; 83 bus_space_handle_t sc_bsh; 84 kmutex_t sc_lock; 85 struct syscon sc_syscon; 86 TAILQ_HEAD(, sunxi_sramc_node) sc_nodes; 87 }; 88 89 static struct sunxi_sramc_softc *sramc_softc = NULL; 90 91 #define SRAMC_READ(sc, reg) \ 92 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 93 #define SRAMC_WRITE(sc, reg, val) \ 94 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 95 96 static void 97 sunxi_sramc_init_mmio(struct sunxi_sramc_softc *sc, int phandle) 98 { 99 struct sunxi_sramc_node *node; 100 int child, i; 101 102 for (child = OF_child(phandle); child; child = OF_peer(child)) 103 for (i = 0; i < __arraycount(sunxi_sramc_areas); i++) { 104 const char * area_compatible[] = { sunxi_sramc_areas[i].compatible, NULL }; 105 if (of_match_compatible(child, area_compatible)) { 106 node = kmem_alloc(sizeof(*node), KM_SLEEP); 107 node->phandle = child; 108 node->area = &sunxi_sramc_areas[i]; 109 TAILQ_INSERT_TAIL(&sc->sc_nodes, node, nodes); 110 aprint_verbose_dev(sc->sc_dev, "area: %s\n", node->area->desc); 111 break; 112 } 113 } 114 } 115 116 static void 117 sunxi_sramc_init(struct sunxi_sramc_softc *sc) 118 { 119 const char * mmio_compatible[] = { "mmio-sram", NULL }; 120 int child; 121 122 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 123 if (!of_match_compatible(child, mmio_compatible)) 124 continue; 125 sunxi_sramc_init_mmio(sc, child); 126 } 127 } 128 129 static void 130 sunxi_sramc_lock(void *priv) 131 { 132 struct sunxi_sramc_softc * const sc = priv; 133 134 mutex_enter(&sc->sc_lock); 135 } 136 137 static void 138 sunxi_sramc_unlock(void *priv) 139 { 140 struct sunxi_sramc_softc * const sc = priv; 141 142 mutex_exit(&sc->sc_lock); 143 } 144 145 static uint32_t 146 sunxi_sramc_read_4(void *priv, bus_size_t reg) 147 { 148 struct sunxi_sramc_softc * const sc = priv; 149 150 KASSERT(mutex_owned(&sc->sc_lock)); 151 152 return SRAMC_READ(sc, reg); 153 } 154 155 static void 156 sunxi_sramc_write_4(void *priv, bus_size_t reg, uint32_t val) 157 { 158 struct sunxi_sramc_softc * const sc = priv; 159 160 KASSERT(mutex_owned(&sc->sc_lock)); 161 162 SRAMC_WRITE(sc, reg, val); 163 } 164 165 static int 166 sunxi_sramc_match(device_t parent, cfdata_t cf, void *aux) 167 { 168 struct fdt_attach_args * const faa = aux; 169 170 return of_match_compatible(faa->faa_phandle, compatible); 171 } 172 173 static void 174 sunxi_sramc_attach(device_t parent, device_t self, void *aux) 175 { 176 struct sunxi_sramc_softc * const sc = device_private(self); 177 struct fdt_attach_args * const faa = aux; 178 const int phandle = faa->faa_phandle; 179 bus_addr_t addr; 180 bus_size_t size; 181 182 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 183 aprint_error(": couldn't get registers\n"); 184 return; 185 } 186 187 sc->sc_dev = self; 188 sc->sc_phandle = phandle; 189 sc->sc_bst = faa->faa_bst; 190 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 191 aprint_error(": couldn't map registers\n"); 192 return; 193 } 194 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 195 TAILQ_INIT(&sc->sc_nodes); 196 197 aprint_naive("\n"); 198 aprint_normal(": SRAM Controller\n"); 199 200 sunxi_sramc_init(sc); 201 202 KASSERT(sramc_softc == NULL); 203 sramc_softc = sc; 204 205 sc->sc_syscon.priv = sc; 206 sc->sc_syscon.lock = sunxi_sramc_lock; 207 sc->sc_syscon.unlock = sunxi_sramc_unlock; 208 sc->sc_syscon.read_4 = sunxi_sramc_read_4; 209 sc->sc_syscon.write_4 = sunxi_sramc_write_4; 210 fdtbus_register_syscon(self, phandle, &sc->sc_syscon); 211 } 212 213 CFATTACH_DECL_NEW(sunxi_sramc, sizeof(struct sunxi_sramc_softc), 214 sunxi_sramc_match, sunxi_sramc_attach, NULL, NULL); 215 216 static int 217 sunxi_sramc_map(const int node_phandle, u_int config) 218 { 219 struct sunxi_sramc_softc * const sc = sramc_softc; 220 struct sunxi_sramc_node *node; 221 uint32_t val; 222 223 if (sc == NULL) 224 return ENXIO; 225 226 TAILQ_FOREACH(node, &sc->sc_nodes, nodes) 227 if (node->phandle == node_phandle) { 228 if (config > __SHIFTOUT_MASK(node->area->mask)) 229 return ERANGE; 230 if ((node->area->flags & SUNXI_SRAMC_F_SWAP) != 0) 231 config = !config; 232 val = SRAMC_READ(sc, node->area->reg); 233 val &= ~node->area->mask; 234 val |= __SHIFTIN(config, node->area->mask); 235 SRAMC_WRITE(sc, node->area->reg, val); 236 return 0; 237 } 238 239 return EINVAL; 240 } 241 242 int 243 sunxi_sramc_claim(const int phandle) 244 { 245 const u_int *data; 246 int len; 247 248 data = fdtbus_get_prop(phandle, "allwinner,sram", &len); 249 if (data == NULL) 250 return ENOENT; 251 if (len != 8) 252 return EIO; 253 254 const int node_phandle = fdtbus_get_phandle_from_native(be32toh(data[0])); 255 const u_int config = be32toh(data[1]); 256 257 return sunxi_sramc_map(node_phandle, config); 258 } 259
Indexes created Wed Oct 22 00:09:40 GMT 2025