sunxi_sramc.c revision 1.5
1 /* $NetBSD: sunxi_sramc.c,v 1.5 2019/07/11 18:22:14 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_sramc.c,v 1.5 2019/07/11 18:22:14 macallan Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kmem.h> 38 #include <sys/mutex.h> 39 40 #include <dev/fdt/fdtvar.h> 41 #include <dev/fdt/syscon.h> 42 43 #include <arm/sunxi/sunxi_sramc.h> 44 45 static const char * compatible[] = { 46 "allwinner,sun4i-a10-sram-controller", /* old compat string */ 47 "allwinner,sun4i-a10-system-control", 48 "allwinner,sun8i-h3-system-control", 49 "allwinner,sun50i-a64-system-control", 50 "allwinner,sun50i-h5-system-control", 51 "allwinner,sun50i-h6-system-control", 52 NULL 53 }; 54 55 static const struct sunxi_sramc_area { 56 const char *compatible; 57 const char *desc; 58 bus_size_t reg; 59 uint32_t mask; 60 u_int flags; 61 #define SUNXI_SRAMC_F_SWAP __BIT(0) 62 } sunxi_sramc_areas[] = { 63 { "allwinner,sun4i-a10-sram-a3-a4", 64 "SRAM A3/A4", 65 0x04, __BITS(5,4), 0 }, 66 { "allwinner,sun4i-a10-sram-d", 67 "SRAM D", 68 0x04, __BIT(0), 0 }, 69 { "allwinner,sun50i-a64-sram-c", 70 "SRAM C", 71 0x04, __BIT(24), SUNXI_SRAMC_F_SWAP }, 72 }; 73 74 struct sunxi_sramc_node { 75 int phandle; 76 const struct sunxi_sramc_area *area; 77 TAILQ_ENTRY(sunxi_sramc_node) nodes; 78 }; 79 80 struct sunxi_sramc_softc { 81 device_t sc_dev; 82 int sc_phandle; 83 bus_space_tag_t sc_bst; 84 bus_space_handle_t sc_bsh; 85 kmutex_t sc_lock; 86 struct syscon sc_syscon; 87 TAILQ_HEAD(, sunxi_sramc_node) sc_nodes; 88 }; 89 90 static struct sunxi_sramc_softc *sramc_softc = NULL; 91 92 #define SRAMC_READ(sc, reg) \ 93 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 94 #define SRAMC_WRITE(sc, reg, val) \ 95 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 96 97 static void 98 sunxi_sramc_init_mmio(struct sunxi_sramc_softc *sc, int phandle) 99 { 100 struct sunxi_sramc_node *node; 101 int child, i; 102 103 for (child = OF_child(phandle); child; child = OF_peer(child)) 104 for (i = 0; i < __arraycount(sunxi_sramc_areas); i++) { 105 const char * area_compatible[] = { sunxi_sramc_areas[i].compatible, NULL }; 106 if (of_match_compatible(child, area_compatible)) { 107 node = kmem_alloc(sizeof(*node), KM_SLEEP); 108 node->phandle = child; 109 node->area = &sunxi_sramc_areas[i]; 110 TAILQ_INSERT_TAIL(&sc->sc_nodes, node, nodes); 111 aprint_verbose_dev(sc->sc_dev, "area: %s\n", node->area->desc); 112 break; 113 } 114 } 115 } 116 117 static void 118 sunxi_sramc_init(struct sunxi_sramc_softc *sc) 119 { 120 const char * mmio_compatible[] = { "mmio-sram", NULL }; 121 int child; 122 123 for (child = OF_child(sc->sc_phandle); child; child = OF_peer(child)) { 124 if (!of_match_compatible(child, mmio_compatible)) 125 continue; 126 sunxi_sramc_init_mmio(sc, child); 127 } 128 } 129 130 static void 131 sunxi_sramc_lock(void *priv) 132 { 133 struct sunxi_sramc_softc * const sc = priv; 134 135 mutex_enter(&sc->sc_lock); 136 } 137 138 static void 139 sunxi_sramc_unlock(void *priv) 140 { 141 struct sunxi_sramc_softc * const sc = priv; 142 143 mutex_exit(&sc->sc_lock); 144 } 145 146 static uint32_t 147 sunxi_sramc_read_4(void *priv, bus_size_t reg) 148 { 149 struct sunxi_sramc_softc * const sc = priv; 150 151 KASSERT(mutex_owned(&sc->sc_lock)); 152 153 return SRAMC_READ(sc, reg); 154 } 155 156 static void 157 sunxi_sramc_write_4(void *priv, bus_size_t reg, uint32_t val) 158 { 159 struct sunxi_sramc_softc * const sc = priv; 160 161 KASSERT(mutex_owned(&sc->sc_lock)); 162 163 SRAMC_WRITE(sc, reg, val); 164 } 165 166 static int 167 sunxi_sramc_match(device_t parent, cfdata_t cf, void *aux) 168 { 169 struct fdt_attach_args * const faa = aux; 170 171 return of_match_compatible(faa->faa_phandle, compatible); 172 } 173 174 static void 175 sunxi_sramc_attach(device_t parent, device_t self, void *aux) 176 { 177 struct sunxi_sramc_softc * const sc = device_private(self); 178 struct fdt_attach_args * const faa = aux; 179 const int phandle = faa->faa_phandle; 180 bus_addr_t addr; 181 bus_size_t size; 182 183 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 184 aprint_error(": couldn't get registers\n"); 185 return; 186 } 187 188 sc->sc_dev = self; 189 sc->sc_phandle = phandle; 190 sc->sc_bst = faa->faa_bst; 191 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 192 aprint_error(": couldn't map registers\n"); 193 return; 194 } 195 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 196 TAILQ_INIT(&sc->sc_nodes); 197 198 aprint_naive("\n"); 199 aprint_normal(": SRAM Controller\n"); 200 201 sunxi_sramc_init(sc); 202 203 KASSERT(sramc_softc == NULL); 204 sramc_softc = sc; 205 206 sc->sc_syscon.priv = sc; 207 sc->sc_syscon.lock = sunxi_sramc_lock; 208 sc->sc_syscon.unlock = sunxi_sramc_unlock; 209 sc->sc_syscon.read_4 = sunxi_sramc_read_4; 210 sc->sc_syscon.write_4 = sunxi_sramc_write_4; 211 fdtbus_register_syscon(self, phandle, &sc->sc_syscon); 212 } 213 214 CFATTACH_DECL_NEW(sunxi_sramc, sizeof(struct sunxi_sramc_softc), 215 sunxi_sramc_match, sunxi_sramc_attach, NULL, NULL); 216 217 static int 218 sunxi_sramc_map(const int node_phandle, u_int config) 219 { 220 struct sunxi_sramc_softc * const sc = sramc_softc; 221 struct sunxi_sramc_node *node; 222 uint32_t val; 223 224 if (sc == NULL) 225 return ENXIO; 226 227 TAILQ_FOREACH(node, &sc->sc_nodes, nodes) 228 if (node->phandle == node_phandle) { 229 if (config > __SHIFTOUT_MASK(node->area->mask)) 230 return ERANGE; 231 if ((node->area->flags & SUNXI_SRAMC_F_SWAP) != 0) 232 config = !config; 233 val = SRAMC_READ(sc, node->area->reg); 234 val &= ~node->area->mask; 235 val |= __SHIFTIN(config, node->area->mask); 236 SRAMC_WRITE(sc, node->area->reg, val); 237 return 0; 238 } 239 240 return EINVAL; 241 } 242 243 int 244 sunxi_sramc_claim(const int phandle) 245 { 246 const u_int *data; 247 int len; 248 249 data = fdtbus_get_prop(phandle, "allwinner,sram", &len); 250 if (data == NULL) 251 return ENOENT; 252 if (len != 8) 253 return EIO; 254 255 const int node_phandle = fdtbus_get_phandle_from_native(be32toh(data[0])); 256 const u_int config = be32toh(data[1]); 257 258 return sunxi_sramc_map(node_phandle, config); 259 } 260
Indexes created Thu Oct 23 22:10:10 GMT 2025