sunxi_tcon.c revision 1.1
1 /* $NetBSD: sunxi_tcon.c,v 1.1 2018/04/03 12:52:16 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Manuel Bouyer <bouyer (at) antioche.eu.org> 5 * All rights reserved. 6 * 7 * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca> 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: sunxi_tcon.c,v 1.1 2018/04/03 12:52:16 bouyer Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 44 #include <dev/fdt/fdtvar.h> 45 #include <dev/fdt/fdt_port.h> 46 #include <dev/fdt/panel_fdt.h> 47 48 #include <dev/videomode/videomode.h> 49 50 #include <arm/sunxi/sunxi_tconreg.h> 51 #include <arm/sunxi/sunxi_display.h> 52 53 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 54 55 enum sunxi_tcon_type { 56 TCON_A10 = 1, 57 TCON_A20, 58 }; 59 60 struct sunxi_tcon_softc { 61 device_t sc_dev; 62 enum sunxi_tcon_type sc_type; 63 int sc_phandle; 64 bus_space_tag_t sc_bst; 65 bus_space_handle_t sc_bsh; 66 struct clk *sc_clk_ahb; 67 struct clk *sc_clk_ch0; 68 struct clk *sc_clk_ch1; 69 unsigned int sc_output_type; 70 #define OUTPUT_HDMI 0 71 #define OUTPUT_LVDS 1 72 #define OUTPUT_VGA 2 73 struct fdt_device_ports sc_ports; 74 int sc_unit; /* tcon0 or tcon1 */ 75 struct fdt_endpoint *sc_in_ep; 76 struct fdt_endpoint *sc_in_rep; 77 struct fdt_endpoint *sc_out_ep; 78 }; 79 80 static bus_space_handle_t tcon_mux_bsh; 81 static bool tcon_mux_inited = false; 82 83 static void sunxi_tcon_ep_connect(device_t, struct fdt_endpoint *, bool); 84 static int sunxi_tcon_ep_activate(device_t, struct fdt_endpoint *, bool); 85 static int sunxi_tcon_ep_enable(device_t, struct fdt_endpoint *, bool); 86 static int sunxi_tcon0_set_video(struct sunxi_tcon_softc *); 87 static int sunxi_tcon0_enable(struct sunxi_tcon_softc *, bool); 88 static int sunxi_tcon1_enable(struct sunxi_tcon_softc *, bool); 89 void sunxi_tcon_dump_regs(int); 90 91 #define TCON_READ(sc, reg) \ 92 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 93 #define TCON_WRITE(sc, reg, val) \ 94 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 95 96 static const struct of_compat_data compat_data[] = { 97 {"allwinner,sun4i-a10-tcon", TCON_A10}, 98 {"allwinner,sun7i-a20-tcon", TCON_A20}, 99 {NULL} 100 }; 101 102 static int sunxi_tcon_match(device_t, cfdata_t, void *); 103 static void sunxi_tcon_attach(device_t, device_t, void *); 104 105 CFATTACH_DECL_NEW(sunxi_tcon, sizeof(struct sunxi_tcon_softc), 106 sunxi_tcon_match, sunxi_tcon_attach, NULL, NULL); 107 108 static int 109 sunxi_tcon_match(device_t parent, cfdata_t cf, void *aux) 110 { 111 struct fdt_attach_args * const faa = aux; 112 113 return of_match_compat_data(faa->faa_phandle, compat_data); 114 } 115 116 static void 117 sunxi_tcon_attach(device_t parent, device_t self, void *aux) 118 { 119 struct sunxi_tcon_softc *sc = device_private(self); 120 struct fdt_attach_args * const faa = aux; 121 const int phandle = faa->faa_phandle; 122 bus_addr_t addr; 123 bus_size_t size; 124 struct fdtbus_reset *rst, *lvds_rst; 125 126 127 sc->sc_dev = self; 128 sc->sc_phandle = phandle; 129 sc->sc_bst = faa->faa_bst; 130 131 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 132 aprint_error(": couldn't get registers\n"); 133 } 134 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 135 aprint_error(": couldn't map registers\n"); 136 return; 137 } 138 139 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 140 sc->sc_clk_ch0 = fdtbus_clock_get(phandle, "tcon-ch0"); 141 sc->sc_clk_ch1 = fdtbus_clock_get(phandle, "tcon-ch1"); 142 143 if (sc->sc_clk_ahb == NULL || sc->sc_clk_ch0 == NULL 144 || sc->sc_clk_ch0 == NULL) { 145 aprint_error(": couldn't get clocks\n"); 146 aprint_debug_dev(self, "clk ahb %s tcon-ch0 %s tcon-ch1 %s\n", 147 sc->sc_clk_ahb == NULL ? "missing" : "present", 148 sc->sc_clk_ch0 == NULL ? "missing" : "present", 149 sc->sc_clk_ch1 == NULL ? "missing" : "present"); 150 return; 151 } 152 153 rst = fdtbus_reset_get(phandle, "lcd"); 154 if (rst == NULL) { 155 aprint_error(": couldn't get lcd reset\n"); 156 return; 157 } 158 159 lvds_rst = fdtbus_reset_get(phandle, "lvds"); 160 161 if (clk_disable(sc->sc_clk_ahb) != 0) { 162 aprint_error(": couldn't disable ahb clock\n"); 163 return; 164 } 165 if (clk_disable(sc->sc_clk_ch0) != 0) { 166 aprint_error(": couldn't disable ch0 clock\n"); 167 return; 168 } 169 170 if (clk_disable(sc->sc_clk_ch1) != 0) { 171 aprint_error(": couldn't disable ch1 clock\n"); 172 return; 173 } 174 175 if (fdtbus_reset_assert(rst) != 0) { 176 aprint_error(": couldn't assert lcd reset\n"); 177 return; 178 } 179 if (lvds_rst != NULL) { 180 if (fdtbus_reset_assert(lvds_rst) != 0) { 181 aprint_error(": couldn't assert lvds reset\n"); 182 return; 183 } 184 } 185 delay(1); 186 if (fdtbus_reset_deassert(rst) != 0) { 187 aprint_error(": couldn't de-assert lcd reset\n"); 188 return; 189 } 190 if (lvds_rst != NULL) { 191 if (fdtbus_reset_deassert(lvds_rst) != 0) { 192 aprint_error(": couldn't de-assert lvds reset\n"); 193 return; 194 } 195 } 196 197 if (clk_enable(sc->sc_clk_ahb) != 0) { 198 aprint_error(": couldn't enable ahb clock\n"); 199 return; 200 } 201 202 sc->sc_type = of_search_compatible(faa->faa_phandle, compat_data)->data; 203 204 aprint_naive("\n"); 205 aprint_normal(": LCD/TV timing controller (%s)\n", 206 fdtbus_get_string(phandle, "name")); 207 208 sc->sc_unit = -1; 209 sc->sc_ports.dp_ep_connect = sunxi_tcon_ep_connect; 210 sc->sc_ports.dp_ep_activate = sunxi_tcon_ep_activate; 211 sc->sc_ports.dp_ep_enable = sunxi_tcon_ep_enable; 212 fdt_ports_register(&sc->sc_ports, self, phandle, EP_OTHER); 213 214 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, 0); 215 TCON_WRITE(sc, SUNXI_TCON_GINT0_REG, 0); 216 TCON_WRITE(sc, SUNXI_TCON_GINT1_REG, 217 __SHIFTIN(0x20, SUNXI_TCON_GINT1_TCON0_LINENO)); 218 TCON_WRITE(sc, SUNXI_TCON0_DCLK_REG, 0xf0000000); 219 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, 0); 220 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0xffffffff); 221 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, 0); 222 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0xffffffff); 223 } 224 225 static void 226 sunxi_tcon_ep_connect(device_t self, struct fdt_endpoint *ep, bool connect) 227 { 228 struct sunxi_tcon_softc *sc = device_private(self); 229 struct fdt_endpoint *rep = fdt_endpoint_remote(ep); 230 int rep_idx = fdt_endpoint_index(rep); 231 232 KASSERT(device_is_a(self, "sunxitcon")); 233 if (!connect) { 234 aprint_error_dev(self, "endpoint disconnect not supported\n"); 235 return; 236 } 237 238 if (fdt_endpoint_port_index(ep) == 0) { 239 bool do_print = (sc->sc_unit == -1); 240 /* 241 * one of our input endpoints has been connected. 242 * the remote id is our unit number 243 */ 244 if (sc->sc_unit != -1 && rep_idx != -1 && 245 sc->sc_unit != rep_idx) { 246 aprint_error_dev(self, ": remote id %d doens't match" 247 " discovered unit number %d\n", 248 rep_idx, sc->sc_unit); 249 return; 250 } 251 if (!device_is_a(fdt_endpoint_device(rep), "sunxidebe")) { 252 aprint_error_dev(self, 253 ": input %d connected to unknown device\n", 254 fdt_endpoint_index(ep)); 255 return; 256 } 257 258 if (rep_idx != -1) 259 sc->sc_unit = rep_idx; 260 else { 261 /* assume only one tcon */ 262 sc->sc_unit = 0; 263 } 264 if (do_print) 265 aprint_verbose_dev(self, "tcon unit %d\n", sc->sc_unit); 266 if (!tcon_mux_inited && sc->sc_unit == 0) { 267 /* the mux register is only in LCD0 */ 268 bus_space_subregion(sc->sc_bst, sc->sc_bsh, 269 SUNXI_TCON_MUX_CTL_REG, 4, &tcon_mux_bsh); 270 tcon_mux_inited = true; 271 } 272 } else if (fdt_endpoint_port_index(ep) == 1) { 273 device_t rep_dev = fdt_endpoint_device(rep); 274 switch(fdt_endpoint_index(ep)) { 275 case 0: 276 break; 277 case 1: 278 if (!device_is_a(rep_dev, "sunxihdmi")) { 279 aprint_error_dev(self, 280 ": output 1 connected to unknown device\n"); 281 return; 282 } 283 break; 284 default: 285 break; 286 } 287 } 288 } 289 290 static int 291 sunxi_tcon_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 292 { 293 struct sunxi_tcon_softc *sc = device_private(dev); 294 struct fdt_endpoint *in_ep, *out_ep; 295 int outi; 296 int error = ENODEV; 297 298 KASSERT(device_is_a(dev, "sunxitcon")); 299 /* our input is activated by debe, we activate our output */ 300 if (fdt_endpoint_port_index(ep) != SUNXI_PORT_INPUT) { 301 panic("sunxi_tcon_ep_activate: port %d", 302 fdt_endpoint_port_index(ep)); 303 } 304 305 if (!activate) 306 return EOPNOTSUPP; 307 308 sc->sc_in_ep = ep; 309 sc->sc_in_rep = fdt_endpoint_remote(ep); 310 /* check that our other input is not active */ 311 switch (fdt_endpoint_index(ep)) { 312 case 0: 313 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 314 SUNXI_PORT_INPUT, 1); 315 break; 316 case 1: 317 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 318 SUNXI_PORT_INPUT, 0); 319 break; 320 default: 321 in_ep = NULL; 322 panic("sunxi_tcon_ep_activate: input index %d", 323 fdt_endpoint_index(ep)); 324 } 325 if (in_ep != NULL) { 326 if (fdt_endpoint_is_active(in_ep)) 327 return EBUSY; 328 } 329 /* try output 0 (RGB/LVDS) first, then ouput 1 (HDMI) if it fails */ 330 for (outi = 0; outi < 2; outi++) { 331 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 332 SUNXI_PORT_OUTPUT, outi); 333 if (out_ep == NULL) 334 continue; 335 error = fdt_endpoint_activate(out_ep, activate); 336 if (error == 0) { 337 struct fdt_endpoint *rep = fdt_endpoint_remote(out_ep); 338 aprint_verbose_dev(dev, "output to %s\n", 339 device_xname(fdt_endpoint_device(rep))); 340 sc->sc_out_ep = out_ep; 341 if (outi == 0) 342 return sunxi_tcon0_set_video(sc); 343 return 0; 344 } 345 } 346 if (out_ep == NULL) { 347 aprint_error_dev(dev, "no output endpoint\n"); 348 return ENODEV; 349 } 350 return error; 351 } 352 353 static int 354 sunxi_tcon_ep_enable(device_t dev, struct fdt_endpoint *ep, bool enable) 355 { 356 struct sunxi_tcon_softc *sc = device_private(dev); 357 int error; 358 KASSERT(device_is_a(dev, "sunxitcon")); 359 switch (fdt_endpoint_port_index(ep)) { 360 case SUNXI_PORT_INPUT: 361 KASSERT(ep == sc->sc_in_ep); 362 if (fdt_endpoint_index(sc->sc_out_ep) == 0) { 363 /* tcon0 active */ 364 return sunxi_tcon0_enable(sc, enable); 365 } 366 /* propagate to our output, it will get back to us */ 367 return fdt_endpoint_enable(sc->sc_out_ep, enable); 368 case SUNXI_PORT_OUTPUT: 369 KASSERT(ep == sc->sc_out_ep); 370 switch (fdt_endpoint_index(ep)) { 371 case 0: 372 panic("sunxi_tcon0_ep_enable"); 373 case 1: 374 error = sunxi_tcon1_enable(sc, enable); 375 break; 376 default: 377 panic("sunxi_tcon_ep_enable ep %d", 378 fdt_endpoint_index(ep)); 379 380 } 381 break; 382 default: 383 panic("sunxi_tcon_ep_enable port %d", fdt_endpoint_port_index(ep)); 384 } 385 #if defined(SUNXI_TCON_DEBUG) 386 sunxi_tcon_dump_regs(device_unit(dev)); 387 #endif 388 return error; 389 } 390 391 static int 392 sunxi_tcon0_set_video(struct sunxi_tcon_softc *sc) 393 { 394 const struct fdt_panel * panel; 395 int32_t lcd_x, lcd_y; 396 int32_t lcd_hbp, lcd_ht, lcd_vbp, lcd_vt; 397 int32_t lcd_hspw, lcd_vspw, lcd_io_cfg0; 398 uint32_t vblk, start_delay; 399 uint32_t val; 400 uint32_t best_div; 401 int best_diff, best_clk_freq, clk_freq, lcd_dclk_freq; 402 bool dualchan = false; 403 static struct videomode mode; 404 int error; 405 406 panel = fdt_endpoint_get_data(fdt_endpoint_remote(sc->sc_out_ep)); 407 KASSERT(panel != NULL); 408 KASSERT(panel->panel_type == PANEL_DUAL_LVDS || 409 panel->panel_type == PANEL_LVDS); 410 411 lcd_x = panel->panel_timing.hactive; 412 lcd_y = panel->panel_timing.vactive; 413 414 lcd_dclk_freq = panel->panel_timing.clock_freq; 415 416 lcd_hbp = panel->panel_timing.hback_porch; 417 lcd_hspw = panel->panel_timing.hsync_len; 418 lcd_ht = panel->panel_timing.hfront_porch + lcd_hspw + lcd_x + lcd_hbp; 419 420 lcd_vbp = panel->panel_timing.vback_porch; 421 lcd_vspw = panel->panel_timing.vsync_len; 422 lcd_vt = panel->panel_timing.vfront_porch + lcd_vspw + lcd_y + lcd_vbp; 423 424 lcd_io_cfg0 = 0x10000000; /* XXX */ 425 426 if (panel->panel_type == PANEL_DUAL_LVDS) 427 dualchan = true; 428 429 vblk = lcd_vt - lcd_y; 430 start_delay = (vblk >= 32) ? 30 : (vblk - 2); 431 432 if (lcd_dclk_freq > 150000000) /* hardware limit ? */ 433 lcd_dclk_freq = 150000000; 434 435 best_diff = INT_MAX; 436 best_div = 0; 437 best_clk_freq = 0; 438 for (u_int div = 7; div <= 15; div++) { 439 int dot_freq, diff; 440 clk_freq = clk_round_rate(sc->sc_clk_ch0, lcd_dclk_freq * div); 441 if (clk_freq == 0) 442 continue; 443 dot_freq = clk_freq / div; 444 diff = abs(lcd_dclk_freq - dot_freq); 445 if (best_diff > diff) { 446 best_diff = diff; 447 best_div = div; 448 best_clk_freq = clk_freq; 449 if (diff == 0) 450 break; 451 } 452 } 453 if (best_clk_freq == 0) { 454 device_printf(sc->sc_dev, 455 ": failed to find params for dot clock %d\n", 456 lcd_dclk_freq); 457 return EINVAL; 458 } 459 460 error = clk_set_rate(sc->sc_clk_ch0, best_clk_freq); 461 if (error) { 462 device_printf(sc->sc_dev, 463 ": failed to set ch0 clock to %d for %d: %d\n", 464 best_clk_freq, lcd_dclk_freq, error); 465 panic("tcon0 set clk"); 466 } 467 error = clk_enable(sc->sc_clk_ch0); 468 if (error) { 469 device_printf(sc->sc_dev, 470 ": failed to enable ch0 clock: %d\n", error); 471 return EIO; 472 } 473 474 val = __SHIFTIN(start_delay, SUNXI_TCONx_CTL_START_DELAY); 475 /* 476 * the DE selector selects the primary DEBE for this tcon: 477 * 0 selects debe0 for tcon0 and debe1 for tcon1 478 */ 479 val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_DE0, 480 SUNXI_TCONx_CTL_SRC_SEL); 481 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val); 482 483 val = (lcd_x - 1) << 16 | (lcd_y - 1); 484 TCON_WRITE(sc, SUNXI_TCON0_BASIC0_REG, val); 485 val = (lcd_ht - 1) << 16 | (lcd_hbp - 1); 486 TCON_WRITE(sc, SUNXI_TCON0_BASIC1_REG, val); 487 val = (lcd_vt * 2) << 16 | (lcd_vbp - 1); 488 TCON_WRITE(sc, SUNXI_TCON0_BASIC2_REG, val); 489 val = ((lcd_hspw > 0) ? (lcd_hspw - 1) : 0) << 16; 490 val |= ((lcd_vspw > 0) ? (lcd_vspw - 1) : 0); 491 TCON_WRITE(sc, SUNXI_TCON0_BASIC3_REG, val); 492 493 val = 0; 494 if (dualchan) 495 val |= SUNXI_TCON0_LVDS_IF_DUALCHAN; 496 if (panel->panel_lvds_format == LVDS_JEIDA_24) 497 val |= SUNXI_TCON0_LVDS_IF_MODE_JEIDA; 498 if (panel->panel_lvds_format == LVDS_JEIDA_18) 499 val |= SUNXI_TCON0_LVDS_IF_18BITS; 500 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val); 501 502 503 TCON_WRITE(sc, SUNXI_TCON0_IO_POL_REG, lcd_io_cfg0); 504 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0); 505 TCON_WRITE(sc, SUNXI_TCON_GINT1_REG, 506 __SHIFTIN(start_delay + 2, SUNXI_TCON_GINT1_TCON0_LINENO)); 507 508 val = 0xf0000000; 509 val &= ~SUNXI_TCON0_DCLK_DIV; 510 val |= __SHIFTIN(best_div, SUNXI_TCON0_DCLK_DIV); 511 TCON_WRITE(sc, SUNXI_TCON0_DCLK_REG, val); 512 513 mode.dot_clock = lcd_dclk_freq; 514 mode.hdisplay = lcd_x; 515 mode.hsync_start = lcd_ht - lcd_hbp; 516 mode.hsync_end = lcd_hspw + mode.hsync_start; 517 mode.htotal = lcd_ht; 518 mode.vdisplay = lcd_y; 519 mode.vsync_start = lcd_vt - lcd_vbp; 520 mode.vsync_end = lcd_vspw + mode.vsync_start; 521 mode.vtotal = lcd_vt; 522 mode.flags = 0; 523 mode.name = NULL; 524 525 sunxi_debe_set_videomode(fdt_endpoint_device(sc->sc_in_rep), &mode); 526 527 /* XXX 528 * magic values here from linux. these are not documented 529 * in the A20 user manual, and other Allwiner LVDS-capable SoC 530 * documentation don't make sense with these values 531 */ 532 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA0); 533 val |= 0x3F310000; 534 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val); 535 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA0); 536 val |= 1 << 22; 537 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val); 538 delay(2); 539 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA1); 540 val |= (0x1f << 26 | 0x1f << 10); 541 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA1, val); 542 delay(2); 543 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA1); 544 val |= (0x1f << 16 | 0x1f << 0); 545 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA1, val); 546 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA0); 547 val |= 1 << 22; 548 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val); 549 return 0; 550 } 551 552 static int 553 sunxi_tcon0_enable(struct sunxi_tcon_softc *sc, bool enable) 554 { 555 uint32_t val; 556 int error; 557 558 /* turn on/off backlight and lcd */ 559 error = fdt_endpoint_enable(sc->sc_out_ep, enable); 560 if (error) 561 return error; 562 563 /* and finally disable or enable the tcon */ 564 error = fdt_endpoint_enable(sc->sc_in_ep, enable); 565 if (error) 566 return error; 567 delay(20000); 568 if (enable) { 569 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 570 val |= SUNXI_TCON_GCTL_EN; 571 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 572 val = TCON_READ(sc, SUNXI_TCON0_CTL_REG); 573 val |= SUNXI_TCONx_CTL_EN; 574 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val); 575 val = TCON_READ(sc, SUNXI_TCON0_LVDS_IF_REG); 576 val |= SUNXI_TCON0_LVDS_IF_EN; 577 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val); 578 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0); 579 } else { 580 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0xffffffff); 581 val = TCON_READ(sc, SUNXI_TCON0_LVDS_IF_REG); 582 val &= ~SUNXI_TCON0_LVDS_IF_EN; 583 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val); 584 val = TCON_READ(sc, SUNXI_TCON0_CTL_REG); 585 val &= ~SUNXI_TCONx_CTL_EN; 586 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val); 587 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 588 val &= ~SUNXI_TCON_GCTL_EN; 589 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 590 } 591 #ifdef SUNXI_TCON_DEBUG 592 sunxi_tcon_dump_regs(device_unit(sc->sc_dev)); 593 #endif 594 return 0; 595 } 596 597 static int 598 sunxi_tcon1_enable(struct sunxi_tcon_softc *sc, bool enable) 599 { 600 uint32_t val; 601 602 KASSERT((sc->sc_output_type == OUTPUT_HDMI) || 603 (sc->sc_output_type == OUTPUT_VGA)); 604 605 fdt_endpoint_enable(sc->sc_in_ep, enable); 606 delay(20000); 607 if (enable) { 608 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 609 val |= SUNXI_TCON_GCTL_EN; 610 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 611 val = TCON_READ(sc, SUNXI_TCON1_CTL_REG); 612 val |= SUNXI_TCONx_CTL_EN; 613 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 614 if (sc->sc_output_type == OUTPUT_VGA) { 615 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0x0cffffff); 616 } else 617 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0); 618 } else { 619 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0xffffffff); 620 val = TCON_READ(sc, SUNXI_TCON1_CTL_REG); 621 val &= ~SUNXI_TCONx_CTL_EN; 622 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 623 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 624 val &= ~SUNXI_TCON_GCTL_EN; 625 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 626 } 627 628 KASSERT(tcon_mux_inited); 629 val = bus_space_read_4(sc->sc_bst, tcon_mux_bsh, 0); 630 #ifdef SUNXI_TCON_DEBUG 631 printf("sunxi_tcon1_enable(%d) %d val 0x%x", sc->sc_unit, enable, val); 632 #endif 633 val &= ~ SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC; 634 switch(sc->sc_unit) { 635 case 0: 636 val |= __SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_LCDC0_TCON1, 637 SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC); 638 break; 639 case 1: 640 val |= __SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_LCDC1_TCON1, 641 SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC); 642 break; 643 default: 644 panic("tcon: invalid unid %d\n", sc->sc_unit); 645 } 646 #ifdef SUNXI_TCON_DEBUG 647 printf(" -> 0x%x", val); 648 #endif 649 bus_space_write_4(sc->sc_bst, tcon_mux_bsh, 0, val); 650 #ifdef SUNXI_TCON_DEBUG 651 printf(": 0x%" PRIxBSH " 0x%" PRIxBSH " 0x%x 0x%x\n", sc->sc_bsh, 652 tcon_mux_bsh, bus_space_read_4(sc->sc_bst, tcon_mux_bsh, 0), 653 TCON_READ(sc, SUNXI_TCON_MUX_CTL_REG)); 654 #endif 655 return 0; 656 } 657 658 void 659 sunxi_tcon1_set_videomode(device_t dev, const struct videomode *mode) 660 { 661 struct sunxi_tcon_softc *sc = device_private(dev); 662 uint32_t val; 663 int error; 664 665 KASSERT(device_is_a(dev, "sunxitcon")); 666 sc = device_private(dev); 667 KASSERT((sc->sc_output_type == OUTPUT_HDMI) || 668 (sc->sc_output_type == OUTPUT_VGA)); 669 670 sunxi_debe_set_videomode(fdt_endpoint_device(sc->sc_in_rep), mode); 671 if (mode) { 672 const u_int interlace_p = !!(mode->flags & VID_INTERLACE); 673 const u_int phsync_p = !!(mode->flags & VID_PHSYNC); 674 const u_int pvsync_p = !!(mode->flags & VID_PVSYNC); 675 const u_int hspw = mode->hsync_end - mode->hsync_start; 676 const u_int hbp = mode->htotal - mode->hsync_start; 677 const u_int vspw = mode->vsync_end - mode->vsync_start; 678 const u_int vbp = mode->vtotal - mode->vsync_start; 679 const u_int vblank_len = 680 ((mode->vtotal << interlace_p) >> 1) - mode->vdisplay - 2; 681 const u_int start_delay = 682 vblank_len >= 32 ? 30 : vblank_len - 2; 683 684 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 685 val |= SUNXI_TCON_GCTL_IO_MAP_SEL; 686 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 687 688 /* enable */ 689 val = SUNXI_TCONx_CTL_EN; 690 if (interlace_p) 691 val |= SUNXI_TCONx_CTL_INTERLACE_EN; 692 val |= __SHIFTIN(start_delay, SUNXI_TCONx_CTL_START_DELAY); 693 #ifdef SUNXI_TCON1_BLUEDATA 694 val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_BLUEDATA, 695 SUNXI_TCONx_CTL_SRC_SEL); 696 #else 697 /* 698 * the DE selector selects the primary DEBE for this tcon: 699 * 0 selects debe0 for tcon0 and debe1 for tcon1 700 */ 701 val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_DE0, 702 SUNXI_TCONx_CTL_SRC_SEL); 703 #endif 704 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 705 706 /* Source width/height */ 707 TCON_WRITE(sc, SUNXI_TCON1_BASIC0_REG, 708 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 709 /* Scaler width/height */ 710 TCON_WRITE(sc, SUNXI_TCON1_BASIC1_REG, 711 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 712 /* Output width/height */ 713 TCON_WRITE(sc, SUNXI_TCON1_BASIC2_REG, 714 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 715 /* Horizontal total + back porch */ 716 TCON_WRITE(sc, SUNXI_TCON1_BASIC3_REG, 717 ((mode->htotal - 1) << 16) | (hbp - 1)); 718 /* Vertical total + back porch */ 719 u_int vtotal = mode->vtotal * 2; 720 if (interlace_p) { 721 u_int framerate = 722 DIVIDE(DIVIDE(mode->dot_clock * 1000, mode->htotal), 723 mode->vtotal); 724 u_int clk = mode->htotal * (mode->vtotal * 2 + 1) * 725 framerate; 726 if ((clk / 2) == mode->dot_clock * 1000) 727 vtotal += 1; 728 } 729 TCON_WRITE(sc, SUNXI_TCON1_BASIC4_REG, 730 (vtotal << 16) | (vbp - 1)); 731 732 /* Sync */ 733 TCON_WRITE(sc, SUNXI_TCON1_BASIC5_REG, 734 ((hspw - 1) << 16) | (vspw - 1)); 735 /* Polarity */ 736 val = SUNXI_TCON_IO_POL_IO2_INV; 737 if (phsync_p) 738 val |= SUNXI_TCON_IO_POL_PHSYNC; 739 if (pvsync_p) 740 val |= SUNXI_TCON_IO_POL_PVSYNC; 741 TCON_WRITE(sc, SUNXI_TCON1_IO_POL_REG, val); 742 743 TCON_WRITE(sc, SUNXI_TCON_GINT1_REG, 744 __SHIFTIN(start_delay + 2, SUNXI_TCON_GINT1_TCON1_LINENO)); 745 746 /* Setup LCDx CH1 PLL */ 747 error = clk_set_rate(sc->sc_clk_ch1, mode->dot_clock * 1000); 748 if (error) { 749 device_printf(sc->sc_dev, 750 ": failed to set ch1 clock to %d: %d\n", 751 mode->dot_clock, error); 752 } 753 error = clk_enable(sc->sc_clk_ch1); 754 if (error) { 755 device_printf(sc->sc_dev, 756 ": failed to enable ch1 clock: %d\n", 757 error); 758 } 759 } else { 760 /* disable */ 761 val = TCON_READ(sc, SUNXI_TCON1_CTL_REG); 762 val &= ~SUNXI_TCONx_CTL_EN; 763 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 764 error = clk_disable(sc->sc_clk_ch1); 765 if (error) { 766 device_printf(sc->sc_dev, 767 ": failed to disable ch1 clock: %d\n", 768 error); 769 } 770 } 771 } 772 773 #if defined(DDB) || defined(SUNXI_TCON_DEBUG) 774 void 775 sunxi_tcon_dump_regs(int u) 776 { 777 static const struct { 778 const char *name; 779 uint16_t reg; 780 } regs[] = { 781 { "TCON0_BASIC0_REG", SUNXI_TCON0_BASIC0_REG }, 782 { "TCON0_BASIC1_REG", SUNXI_TCON0_BASIC1_REG }, 783 { "TCON0_BASIC2_REG", SUNXI_TCON0_BASIC2_REG }, 784 { "TCON0_BASIC3_REG", SUNXI_TCON0_BASIC3_REG }, 785 { "TCON0_CTL_REG", SUNXI_TCON0_CTL_REG }, 786 { "TCON0_DCLK_REG", SUNXI_TCON0_DCLK_REG }, 787 { "TCON0_IO_POL_REG", SUNXI_TCON0_IO_POL_REG }, 788 { "TCON0_IO_TRI_REG", SUNXI_TCON0_IO_TRI_REG }, 789 { "TCON0_LVDS_IF_REG", SUNXI_TCON0_LVDS_IF_REG }, 790 { "TCON1_BASIC0_REG", SUNXI_TCON1_BASIC0_REG }, 791 { "TCON1_BASIC1_REG", SUNXI_TCON1_BASIC1_REG }, 792 { "TCON1_BASIC2_REG", SUNXI_TCON1_BASIC2_REG }, 793 { "TCON1_BASIC3_REG", SUNXI_TCON1_BASIC3_REG }, 794 { "TCON1_BASIC4_REG", SUNXI_TCON1_BASIC4_REG }, 795 { "TCON1_BASIC5_REG", SUNXI_TCON1_BASIC5_REG }, 796 { "TCON1_CTL_REG", SUNXI_TCON1_CTL_REG }, 797 { "TCON1_IO_POL_REG", SUNXI_TCON1_IO_POL_REG }, 798 { "TCON1_IO_TRI_REG", SUNXI_TCON1_IO_TRI_REG }, 799 { "TCON_GCTL_REG", SUNXI_TCON_GCTL_REG }, 800 { "TCON_GINT0_REG", SUNXI_TCON_GINT0_REG }, 801 { "TCON_GINT1_REG", SUNXI_TCON_GINT1_REG }, 802 { "TCON_MUX_CTL_REG", SUNXI_TCON_MUX_CTL_REG }, 803 }; 804 struct sunxi_tcon_softc *sc; 805 device_t dev; 806 807 dev = device_find_by_driver_unit("sunxitcon", u); 808 if (dev == NULL) 809 return; 810 sc = device_private(dev); 811 812 for (int i = 0; i < __arraycount(regs); i++) { 813 printf("%s: 0x%08x\n", regs[i].name, 814 TCON_READ(sc, regs[i].reg)); 815 } 816 } 817 #endif 818
Indexes created Tue Sep 30 20:09:53 GMT 2025