sunxi_tcon.c revision 1.13.2.3
1 /* $NetBSD: sunxi_tcon.c,v 1.13.2.3 2022/10/16 17:23:40 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Manuel Bouyer <bouyer (at) antioche.eu.org> 5 * All rights reserved. 6 * 7 * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca> 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: sunxi_tcon.c,v 1.13.2.3 2022/10/16 17:23:40 bouyer Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 44 #include <dev/fdt/fdtvar.h> 45 #include <dev/fdt/fdt_port.h> 46 #include <dev/fdt/panel_fdt.h> 47 48 #include <arm/sunxi/sunxi_tconreg.h> 49 #include <arm/sunxi/sunxi_display.h> 50 51 #include <drm/drm_bridge.h> 52 #include <drm/drm_connector.h> 53 #include <drm/drm_drv.h> 54 #include <drm/drm_modes.h> 55 56 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 57 58 enum sunxi_tcon_type { 59 TCON_A10 = 1, 60 }; 61 62 struct sunxi_tcon_softc { 63 device_t sc_dev; 64 enum sunxi_tcon_type sc_type; 65 int sc_phandle; 66 bus_space_tag_t sc_bst; 67 bus_space_handle_t sc_bsh; 68 struct clk *sc_clk_ahb; 69 struct clk *sc_clk_ch0; 70 struct clk *sc_clk_ch1; 71 struct fdtbus_reset *sc_rst, *sc_lvds_rst; 72 unsigned int sc_output_type; 73 #define OUTPUT_HDMI 0 74 #define OUTPUT_LVDS 1 75 #define OUTPUT_VGA 2 76 struct fdt_device_ports sc_ports; 77 int sc_unit; /* tcon0 or tcon1 */ 78 struct fdt_endpoint *sc_in_ep; 79 struct fdt_endpoint *sc_in_rep; 80 struct fdt_endpoint *sc_out_ep; 81 struct drm_encoder sc_encoder; 82 struct drm_connector sc_connector; 83 }; 84 85 static bus_space_handle_t tcon_mux_bsh; 86 static bool tcon_mux_inited = false; 87 88 static void sunxi_tcon_ep_connect(device_t, struct fdt_endpoint *, bool); 89 static int sunxi_tcon_ep_activate(device_t, struct fdt_endpoint *, bool); 90 static int sunxi_tcon_ep_enable(device_t, struct fdt_endpoint *, bool); 91 static int sunxi_tcon0_set_video(struct sunxi_tcon_softc *); 92 static int sunxi_tcon0_enable(struct sunxi_tcon_softc *, bool); 93 static int sunxi_tcon1_enable(struct sunxi_tcon_softc *, bool); 94 void sunxi_tcon_dump_regs(int); 95 96 #define encoder_to_tcon(x) container_of(x, struct sunxi_tcon_softc, sc_encoder) 97 #define connector_to_tcon(x) container_of(x, struct sunxi_tcon_softc, sc_connector) 98 99 static void 100 sunxi_tcon_destroy(struct drm_encoder *encoder) 101 { 102 drm_encoder_cleanup(encoder); 103 } 104 105 static const struct drm_encoder_funcs sunxi_tcon_enc_funcs = { 106 .destroy = sunxi_tcon_destroy, 107 }; 108 109 static int sunxi_tcon_atomic_check(struct drm_encoder *, 110 struct drm_crtc_state *, struct drm_connector_state *); 111 static void sunxi_tcon_disable(struct drm_encoder *); 112 static void sunxi_tcon_enable(struct drm_encoder *); 113 static void sunxi_tcon_mode_set(struct drm_encoder *, 114 struct drm_display_mode *, struct drm_display_mode *); 115 static void sunxi_tcon_mode_valid(struct drm_encoder *, 116 struct drm_display_mode *); 117 118 static void 119 sunxi_tcon_encoder_disable(struct drm_encoder *encoder) 120 { 121 int ret; 122 struct sunxi_tcon_softc *sc = encoder_to_tcon(encoder); 123 ret = sunxi_tcon0_enable(sc, false); 124 if (ret) 125 device_printf(sc->sc_dev, "failed to disable tcon0: %d\n", ret); 126 } 127 static void 128 sunci_tcon_encoder_enable(struct drm_encoder *encoder) 129 { 130 int ret; 131 struct sunxi_tcon_softc *sc = encoder_to_tcon(encoder); 132 ret = sunxi_tcon0_enable(sc, true); 133 if (ret) 134 device_printf(sc->sc_dev, "failed to enable tcon0: %d\n", ret); 135 } 136 137 static const struct drm_encoder_helper_funcs sunxi_tcon_enc_helper_funcs = { 138 .disable = sunxi_tcon_disable, 139 .enable = sunxi_tcon_enable, 140 }; 141 142 static enum drm_connector_status sunxi_tcon_connector_detect( 143 struct drm_connector *, bool); 144 145 static const struct drm_connector_funcs sunxi_tcon_connector_funcs = { 146 .fill_modes = drm_helper_probe_single_connector_modes, 147 .destroy = drm_connector_cleanup, 148 .reset = drm_atomic_helper_connector_reset, 149 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 150 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 151 }; 152 153 static int sunxi_tcon_get_modes(struct drm_connector *); 154 155 static const struct drm_connector_helper_funcs sunxi_tcon_connector_helper_funcs 156 = { 157 .get_modes = sunxi_tcon_get_modes, 158 }; 159 160 #define TCON_READ(sc, reg) \ 161 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 162 #define TCON_WRITE(sc, reg, val) \ 163 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 164 165 static const struct device_compatible_entry compat_data[] = { 166 { .compat = "allwinner,sun4i-a10-tcon", .value = TCON_A10}, 167 { .compat = "allwinner,sun7i-a20-tcon", .value = TCON_A10}, 168 { .compat = "allwinner,sun7i-a20-tcon0", .value = TCON_A10 }, 169 { .compat = "allwinner,sun7i-a20-tcon1", .value = TCON_A10 }, 170 DEVICE_COMPAT_EOL 171 }; 172 173 static int sunxi_tcon_match(device_t, cfdata_t, void *); 174 static void sunxi_tcon_attach(device_t, device_t, void *); 175 176 CFATTACH_DECL_NEW(sunxi_tcon, sizeof(struct sunxi_tcon_softc), 177 sunxi_tcon_match, sunxi_tcon_attach, NULL, NULL); 178 179 static int 180 sunxi_tcon_match(device_t parent, cfdata_t cf, void *aux) 181 { 182 struct fdt_attach_args * const faa = aux; 183 184 return of_compatible_match(faa->faa_phandle, compat_data); 185 } 186 187 static void 188 sunxi_tcon_attach(device_t parent, device_t self, void *aux) 189 { 190 struct sunxi_tcon_softc *sc = device_private(self); 191 struct fdt_attach_args * const faa = aux; 192 const int phandle = faa->faa_phandle; 193 bus_addr_t addr; 194 bus_size_t size; 195 196 sc->sc_dev = self; 197 sc->sc_phandle = phandle; 198 sc->sc_bst = faa->faa_bst; 199 200 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 201 aprint_error(": couldn't get registers\n"); 202 } 203 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 204 aprint_error(": couldn't map registers\n"); 205 return; 206 } 207 208 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 209 sc->sc_clk_ch0 = fdtbus_clock_get(phandle, "tcon-ch0"); 210 sc->sc_clk_ch1 = fdtbus_clock_get(phandle, "tcon-ch1"); 211 212 if (sc->sc_clk_ahb == NULL || sc->sc_clk_ch0 == NULL 213 || sc->sc_clk_ch1 == NULL) { 214 aprint_error(": couldn't get clocks\n"); 215 aprint_debug_dev(self, "clk ahb %s tcon-ch0 %s tcon-ch1 %s\n", 216 sc->sc_clk_ahb == NULL ? "missing" : "present", 217 sc->sc_clk_ch0 == NULL ? "missing" : "present", 218 sc->sc_clk_ch1 == NULL ? "missing" : "present"); 219 return; 220 } 221 222 sc->sc_rst = fdtbus_reset_get(phandle, "lcd"); 223 if (sc->sc_rst == NULL) { 224 aprint_error(": couldn't get lcd reset\n"); 225 return; 226 } 227 228 sc->sc_lvds_rst = fdtbus_reset_get(phandle, "lvds"); 229 230 sc->sc_type = 231 of_compatible_lookup(faa->faa_phandle, compat_data)->value; 232 233 aprint_naive("\n"); 234 aprint_normal(": LCD/TV timing controller (%s)\n", 235 fdtbus_get_string(phandle, "name")); 236 237 sc->sc_unit = -1; 238 sc->sc_ports.dp_ep_connect = sunxi_tcon_ep_connect; 239 sc->sc_ports.dp_ep_activate = sunxi_tcon_ep_activate; 240 sc->sc_ports.dp_ep_enable = sunxi_tcon_ep_enable; 241 fdt_ports_register(&sc->sc_ports, self, phandle, EP_OTHER); 242 } 243 244 void 245 sunxi_tcon_doreset(void) 246 { 247 device_t dev; 248 struct sunxi_tcon_softc *sc; 249 for (int i = 0;;i++) { 250 dev = device_find_by_driver_unit("sunxitcon", i); 251 if (dev == NULL) 252 return; 253 sc = device_private(dev); 254 255 if (clk_disable(sc->sc_clk_ahb) != 0) { 256 aprint_error_dev(dev, ": couldn't disable ahb clock\n"); 257 return; 258 } 259 if (clk_disable(sc->sc_clk_ch0) != 0) { 260 aprint_error_dev(dev, ": couldn't disable ch0 clock\n"); 261 return; 262 } 263 264 if (clk_disable(sc->sc_clk_ch1) != 0) { 265 aprint_error_dev(dev, ": couldn't disable ch1 clock\n"); 266 return; 267 } 268 269 if (fdtbus_reset_assert(sc->sc_rst) != 0) { 270 aprint_error_dev(dev, ": couldn't assert lcd reset\n"); 271 return; 272 } 273 if (sc->sc_lvds_rst != NULL) { 274 if (fdtbus_reset_assert(sc->sc_lvds_rst) != 0) { 275 aprint_error_dev(dev, 276 ": couldn't assert lvds reset\n"); 277 return; 278 } 279 } 280 delay(1); 281 if (fdtbus_reset_deassert(sc->sc_rst) != 0) { 282 aprint_error_dev(dev, 283 ": couldn't de-assert lcd reset\n"); 284 return; 285 } 286 if (sc->sc_lvds_rst != NULL) { 287 if (fdtbus_reset_deassert(sc->sc_lvds_rst) != 0) { 288 aprint_error_dev(dev, 289 ": couldn't de-assert lvds reset\n"); 290 return; 291 } 292 } 293 294 if (clk_enable(sc->sc_clk_ahb) != 0) { 295 aprint_error_dev(dev, ": couldn't enable ahb clock\n"); 296 return; 297 } 298 299 TCON_WRITE(sc, SUNXI_TCON_GINT0_REG, 0); 300 TCON_WRITE(sc, SUNXI_TCON_GINT1_REG, 301 __SHIFTIN(0x20, SUNXI_TCON_GINT1_TCON0_LINENO)); 302 TCON_WRITE(sc, SUNXI_TCON0_DCLK_REG, 0xf0000000); 303 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, 0x0); 304 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, 0); 305 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0xffffffff); 306 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, 0); 307 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0xffffffff); 308 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, 0); 309 310 /* clock needed for the mux in unit 0 */ 311 if (sc->sc_unit != 0) { 312 if (clk_disable(sc->sc_clk_ahb) != 0) { 313 aprint_error_dev(dev, 314 ": couldn't disable ahb clock\n"); 315 return; 316 } 317 } 318 } 319 } 320 321 static void 322 sunxi_tcon_ep_connect(device_t self, struct fdt_endpoint *ep, bool connect) 323 { 324 struct sunxi_tcon_softc *sc = device_private(self); 325 struct fdt_endpoint *rep = fdt_endpoint_remote(ep); 326 int rep_idx = fdt_endpoint_index(rep); 327 328 KASSERT(device_is_a(self, "sunxitcon")); 329 if (!connect) { 330 aprint_error_dev(self, "endpoint disconnect not supported\n"); 331 return; 332 } 333 334 if (fdt_endpoint_port_index(ep) == 0) { 335 bool do_print = (sc->sc_unit == -1); 336 /* 337 * one of our input endpoints has been connected. 338 * the remote id is our unit number 339 */ 340 if (sc->sc_unit != -1 && rep_idx != -1 && 341 sc->sc_unit != rep_idx) { 342 aprint_error_dev(self, ": remote id %d doesn't match" 343 " discovered unit number %d\n", 344 rep_idx, sc->sc_unit); 345 return; 346 } 347 if (!device_is_a(fdt_endpoint_device(rep), "sunxidebe")) { 348 aprint_error_dev(self, 349 ": input %d connected to unknown device\n", 350 fdt_endpoint_index(ep)); 351 return; 352 } 353 354 if (rep_idx != -1) 355 sc->sc_unit = rep_idx; 356 else { 357 /* assume only one tcon */ 358 sc->sc_unit = 0; 359 } 360 if (do_print) 361 aprint_verbose_dev(self, "tcon unit %d\n", sc->sc_unit); 362 if (!tcon_mux_inited && sc->sc_unit == 0) { 363 /* the mux register is only in LCD0 */ 364 if (clk_enable(sc->sc_clk_ahb) != 0) { 365 aprint_error_dev(self, 366 "couldn't enable ahb clock\n"); 367 return; 368 } 369 bus_space_subregion(sc->sc_bst, sc->sc_bsh, 370 SUNXI_TCON_MUX_CTL_REG, 4, &tcon_mux_bsh); 371 tcon_mux_inited = true; 372 bus_space_write_4(sc->sc_bst, tcon_mux_bsh, 0, 373 __SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_CLOSE, 374 SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC)); 375 } 376 } else if (fdt_endpoint_port_index(ep) == 1) { 377 device_t rep_dev = fdt_endpoint_device(rep); 378 switch(fdt_endpoint_index(ep)) { 379 case 0: 380 break; 381 case 1: 382 if (!device_is_a(rep_dev, "sunxihdmi")) { 383 aprint_error_dev(self, 384 ": output 1 connected to unknown device\n"); 385 return; 386 } 387 break; 388 default: 389 break; 390 } 391 } 392 } 393 394 static int 395 sunxi_tcon0_drm_register(struct sunxi_tcon_softc *sc) 396 { 397 struct drm_crtc *crtc = sunxi_tcon_get_crtc(sc->sc_dev); 398 KASSERT(crtc != NULL); 399 int error; 400 401 sc->sc_encoder.possible_crtcs = 1 << drm_crtc_index(crtc); 402 drm_encoder_helper_add(&sc->sc_encoder, sunxi_tcon_enc_helper_funcs); 403 error = drm_encoder_init(crtc->dev, &sc->sc_encoder, 404 sunxi_tcon_enc_funcs, DRM_MODE_ENCODER_LVDS, NULL); 405 if (error) 406 return -error; 407 drm_connector_helper_add(&sc->sc_connector, 408 &sunxi_tcon_connector_helper_funcs); 409 error = drm_connector_init(crtc->dev, &sc->sc_connector, 410 DRM_MODE_CONNECTOR_LVDS); 411 if (error) 412 return -error; 413 drm_connector_attach_encoder(&sc->sc_connector, &sc->sc_encoder.base); 414 return sunxi_tcon0_set_video(sc); 415 } 416 417 static int 418 sunxi_tcon_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 419 { 420 struct sunxi_tcon_softc *sc = device_private(dev); 421 struct fdt_endpoint *in_ep, *out_ep; 422 int outi; 423 int error = ENODEV; 424 425 KASSERT(device_is_a(dev, "sunxitcon")); 426 /* our input is activated by debe, we activate our output */ 427 if (fdt_endpoint_port_index(ep) != SUNXI_PORT_INPUT) { 428 panic("sunxi_tcon_ep_activate: port %d", 429 fdt_endpoint_port_index(ep)); 430 } 431 432 if (!activate) 433 return EOPNOTSUPP; 434 435 if (clk_enable(sc->sc_clk_ahb) != 0) { 436 aprint_error_dev(dev, "couldn't enable ahb clock\n"); 437 return EIO; 438 } 439 sc->sc_in_ep = ep; 440 sc->sc_in_rep = fdt_endpoint_remote(ep); 441 /* check that our other input is not active */ 442 switch (fdt_endpoint_index(ep)) { 443 case 0: 444 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 445 SUNXI_PORT_INPUT, 1); 446 break; 447 case 1: 448 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 449 SUNXI_PORT_INPUT, 0); 450 break; 451 default: 452 in_ep = NULL; 453 panic("sunxi_tcon_ep_activate: input index %d", 454 fdt_endpoint_index(ep)); 455 } 456 if (in_ep != NULL) { 457 if (fdt_endpoint_is_active(in_ep)) 458 return EBUSY; 459 } 460 /* try output 0 (RGB/LVDS) first, then output 1 (HDMI) if it fails */ 461 for (outi = 0; outi < 2; outi++) { 462 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 463 SUNXI_PORT_OUTPUT, outi); 464 if (out_ep == NULL) 465 continue; 466 error = fdt_endpoint_activate(out_ep, activate); 467 if (error == 0) { 468 struct fdt_endpoint *rep = fdt_endpoint_remote(out_ep); 469 aprint_verbose_dev(dev, "output to %s\n", 470 device_xname(fdt_endpoint_device(rep))); 471 sc->sc_out_ep = out_ep; 472 if (outi == 0) 473 return sunxi_tcon0_drm_register(sc); 474 /* XXX should check VGA here */ 475 sc->sc_output_type = OUTPUT_HDMI; 476 return 0; 477 } 478 } 479 if (out_ep == NULL) { 480 aprint_error_dev(dev, "no output endpoint\n"); 481 return ENODEV; 482 } 483 return error; 484 } 485 486 static int 487 sunxi_tcon_ep_enable(device_t dev, struct fdt_endpoint *ep, bool enable) 488 { 489 struct sunxi_tcon_softc *sc = device_private(dev); 490 int error; 491 KASSERT(device_is_a(dev, "sunxitcon")); 492 switch (fdt_endpoint_port_index(ep)) { 493 case SUNXI_PORT_INPUT: 494 KASSERT(ep == sc->sc_in_ep); 495 if (fdt_endpoint_index(sc->sc_out_ep) == 0) { 496 /* tcon0 active */ 497 return sunxi_tcon0_enable(sc, enable); 498 } 499 /* propagate to our output, it will get back to us */ 500 return fdt_endpoint_enable(sc->sc_out_ep, enable); 501 case SUNXI_PORT_OUTPUT: 502 KASSERT(ep == sc->sc_out_ep); 503 switch (fdt_endpoint_index(ep)) { 504 case 0: 505 panic("sunxi_tcon0_ep_enable"); 506 case 1: 507 error = sunxi_tcon1_enable(sc, enable); 508 break; 509 default: 510 panic("sunxi_tcon_ep_enable ep %d", 511 fdt_endpoint_index(ep)); 512 513 } 514 break; 515 default: 516 panic("sunxi_tcon_ep_enable port %d", fdt_endpoint_port_index(ep)); 517 } 518 #if defined(SUNXI_TCON_DEBUG) 519 sunxi_tcon_dump_regs(device_unit(dev)); 520 #endif 521 return error; 522 } 523 524 static int 525 sunxi_tcon0_set_video(struct sunxi_tcon_softc *sc) 526 { 527 const struct fdt_panel * panel; 528 int32_t lcd_x, lcd_y; 529 int32_t lcd_hbp, lcd_ht, lcd_vbp, lcd_vt; 530 int32_t lcd_hspw, lcd_vspw, lcd_io_cfg0; 531 uint32_t vblk, start_delay; 532 uint32_t val; 533 uint32_t best_div; 534 int best_diff, best_clk_freq, clk_freq, lcd_dclk_freq; 535 bool dualchan = false; 536 static struct videomode mode; 537 int error; 538 539 panel = fdt_endpoint_get_data(fdt_endpoint_remote(sc->sc_out_ep)); 540 KASSERT(panel != NULL); 541 KASSERT(panel->panel_type == PANEL_DUAL_LVDS || 542 panel->panel_type == PANEL_LVDS); 543 sc->sc_output_type = OUTPUT_LVDS; 544 545 lcd_x = panel->panel_timing.hactive; 546 lcd_y = panel->panel_timing.vactive; 547 548 lcd_dclk_freq = panel->panel_timing.clock_freq; 549 550 lcd_hbp = panel->panel_timing.hback_porch; 551 lcd_hspw = panel->panel_timing.hsync_len; 552 lcd_ht = panel->panel_timing.hfront_porch + lcd_hspw + lcd_x + lcd_hbp; 553 554 lcd_vbp = panel->panel_timing.vback_porch; 555 lcd_vspw = panel->panel_timing.vsync_len; 556 lcd_vt = panel->panel_timing.vfront_porch + lcd_vspw + lcd_y + lcd_vbp; 557 558 lcd_io_cfg0 = 0x10000000; /* XXX */ 559 560 if (panel->panel_type == PANEL_DUAL_LVDS) 561 dualchan = true; 562 563 vblk = lcd_vt - lcd_y; 564 start_delay = (vblk >= 32) ? 30 : (vblk - 2); 565 566 if (lcd_dclk_freq > 150000000) /* hardware limit ? */ 567 lcd_dclk_freq = 150000000; 568 569 best_diff = INT_MAX; 570 best_div = 0; 571 best_clk_freq = 0; 572 for (u_int div = 7; div <= 15; div++) { 573 int dot_freq, diff; 574 clk_freq = clk_round_rate(sc->sc_clk_ch0, lcd_dclk_freq * div); 575 if (clk_freq == 0) 576 continue; 577 dot_freq = clk_freq / div; 578 diff = abs(lcd_dclk_freq - dot_freq); 579 if (best_diff > diff) { 580 best_diff = diff; 581 best_div = div; 582 best_clk_freq = clk_freq; 583 if (diff == 0) 584 break; 585 } 586 } 587 if (best_clk_freq == 0) { 588 device_printf(sc->sc_dev, 589 ": failed to find params for dot clock %d\n", 590 lcd_dclk_freq); 591 return EINVAL; 592 } 593 594 error = clk_set_rate(sc->sc_clk_ch0, best_clk_freq); 595 if (error) { 596 device_printf(sc->sc_dev, 597 ": failed to set ch0 clock to %d for %d: %d\n", 598 best_clk_freq, lcd_dclk_freq, error); 599 panic("tcon0 set clk"); 600 } 601 error = clk_enable(sc->sc_clk_ch0); 602 if (error) { 603 device_printf(sc->sc_dev, 604 ": failed to enable ch0 clock: %d\n", error); 605 return EIO; 606 } 607 608 val = __SHIFTIN(start_delay, SUNXI_TCONx_CTL_START_DELAY); 609 /* 610 * the DE selector selects the primary DEBE for this tcon: 611 * 0 selects debe0 for tcon0 and debe1 for tcon1 612 */ 613 val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_DE0, 614 SUNXI_TCONx_CTL_SRC_SEL); 615 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val); 616 617 val = (lcd_x - 1) << 16 | (lcd_y - 1); 618 TCON_WRITE(sc, SUNXI_TCON0_BASIC0_REG, val); 619 val = (lcd_ht - 1) << 16 | (lcd_hbp - 1); 620 TCON_WRITE(sc, SUNXI_TCON0_BASIC1_REG, val); 621 val = (lcd_vt * 2) << 16 | (lcd_vbp - 1); 622 TCON_WRITE(sc, SUNXI_TCON0_BASIC2_REG, val); 623 val = ((lcd_hspw > 0) ? (lcd_hspw - 1) : 0) << 16; 624 val |= ((lcd_vspw > 0) ? (lcd_vspw - 1) : 0); 625 TCON_WRITE(sc, SUNXI_TCON0_BASIC3_REG, val); 626 627 val = 0; 628 if (dualchan) 629 val |= SUNXI_TCON0_LVDS_IF_DUALCHAN; 630 if (panel->panel_lvds_format == LVDS_JEIDA_24) 631 val |= SUNXI_TCON0_LVDS_IF_MODE_JEIDA; 632 if (panel->panel_lvds_format == LVDS_JEIDA_18) 633 val |= SUNXI_TCON0_LVDS_IF_18BITS; 634 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val); 635 636 TCON_WRITE(sc, SUNXI_TCON0_IO_POL_REG, lcd_io_cfg0); 637 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0); 638 TCON_WRITE(sc, SUNXI_TCON_GINT1_REG, 639 __SHIFTIN(start_delay + 2, SUNXI_TCON_GINT1_TCON0_LINENO)); 640 641 val = 0xf0000000; 642 val &= ~SUNXI_TCON0_DCLK_DIV; 643 val |= __SHIFTIN(best_div, SUNXI_TCON0_DCLK_DIV); 644 TCON_WRITE(sc, SUNXI_TCON0_DCLK_REG, val); 645 646 mode.dot_clock = lcd_dclk_freq; 647 mode.hdisplay = lcd_x; 648 mode.hsync_start = lcd_ht - lcd_hbp; 649 mode.hsync_end = lcd_hspw + mode.hsync_start; 650 mode.htotal = lcd_ht; 651 mode.vdisplay = lcd_y; 652 mode.vsync_start = lcd_vt - lcd_vbp; 653 mode.vsync_end = lcd_vspw + mode.vsync_start; 654 mode.vtotal = lcd_vt; 655 mode.flags = 0; 656 mode.name = NULL; 657 658 sunxi_debe_set_videomode(fdt_endpoint_device(sc->sc_in_rep), &mode); 659 660 /* XXX 661 * magic values here from linux. these are not documented 662 * in the A20 user manual, and other Allwiner LVDS-capable SoC 663 * documentation don't make sense with these values 664 */ 665 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA0); 666 val |= 0x3F310000; 667 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val); 668 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA0); 669 val |= 1 << 22; 670 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val); 671 delay(2); 672 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA1); 673 val |= (0x1f << 26 | 0x1f << 10); 674 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA1, val); 675 delay(2); 676 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA1); 677 val |= (0x1f << 16 | 0x1f << 0); 678 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA1, val); 679 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA0); 680 val |= 1 << 22; 681 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val); 682 return 0; 683 } 684 685 static int 686 sunxi_tcon0_enable(struct sunxi_tcon_softc *sc, bool enable) 687 { 688 uint32_t val; 689 int error; 690 691 /* turn on/off backlight and lcd */ 692 error = fdt_endpoint_enable(sc->sc_out_ep, enable); 693 if (error) 694 return error; 695 696 /* and finally disable or enable the tcon */ 697 error = fdt_endpoint_enable(sc->sc_in_ep, enable); 698 if (error) 699 return error; 700 delay(20000); 701 if (enable) { 702 if ((error = clk_enable(sc->sc_clk_ch0)) != 0) { 703 device_printf(sc->sc_dev, 704 ": couldn't enable ch0 clock\n"); 705 return error; 706 } 707 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 708 val |= SUNXI_TCON_GCTL_EN; 709 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 710 val = TCON_READ(sc, SUNXI_TCON0_CTL_REG); 711 val |= SUNXI_TCONx_CTL_EN; 712 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val); 713 val = TCON_READ(sc, SUNXI_TCON0_LVDS_IF_REG); 714 val |= SUNXI_TCON0_LVDS_IF_EN; 715 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val); 716 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0); 717 } else { 718 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0xffffffff); 719 val = TCON_READ(sc, SUNXI_TCON0_LVDS_IF_REG); 720 val &= ~SUNXI_TCON0_LVDS_IF_EN; 721 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val); 722 val = TCON_READ(sc, SUNXI_TCON0_CTL_REG); 723 val &= ~SUNXI_TCONx_CTL_EN; 724 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val); 725 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 726 val &= ~SUNXI_TCON_GCTL_EN; 727 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 728 if ((error = clk_disable(sc->sc_clk_ch0)) != 0) { 729 device_printf(sc->sc_dev, 730 ": couldn't disable ch0 clock\n"); 731 return error; 732 } 733 } 734 #ifdef SUNXI_TCON_DEBUG 735 sunxi_tcon_dump_regs(device_unit(sc->sc_dev)); 736 #endif 737 return 0; 738 } 739 740 static int 741 sunxi_tcon1_enable(struct sunxi_tcon_softc *sc, bool enable) 742 { 743 uint32_t val; 744 int error; 745 746 KASSERT((sc->sc_output_type == OUTPUT_HDMI) || 747 (sc->sc_output_type == OUTPUT_VGA)); 748 749 fdt_endpoint_enable(sc->sc_in_ep, enable); 750 delay(20000); 751 if (enable) { 752 if ((error = clk_enable(sc->sc_clk_ch1)) != 0) { 753 device_printf(sc->sc_dev, 754 ": couldn't enable ch1 clock\n"); 755 return error; 756 } 757 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 758 val |= SUNXI_TCON_GCTL_EN; 759 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 760 val = TCON_READ(sc, SUNXI_TCON1_CTL_REG); 761 val |= SUNXI_TCONx_CTL_EN; 762 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 763 if (sc->sc_output_type == OUTPUT_VGA) { 764 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0x0cffffff); 765 } else 766 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0); 767 } else { 768 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0xffffffff); 769 val = TCON_READ(sc, SUNXI_TCON1_CTL_REG); 770 val &= ~SUNXI_TCONx_CTL_EN; 771 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 772 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 773 val &= ~SUNXI_TCON_GCTL_EN; 774 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 775 if ((error = clk_disable(sc->sc_clk_ch1)) != 0) { 776 device_printf(sc->sc_dev, 777 ": couldn't disable ch1 clock\n"); 778 return error; 779 } 780 } 781 782 KASSERT(tcon_mux_inited); 783 val = bus_space_read_4(sc->sc_bst, tcon_mux_bsh, 0); 784 #ifdef SUNXI_TCON_DEBUG 785 printf("sunxi_tcon1_enable(%d) %d val 0x%x", sc->sc_unit, enable, val); 786 #endif 787 val &= ~ SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC; 788 switch(sc->sc_unit) { 789 case 0: 790 val |= __SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_LCDC0_TCON1, 791 SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC); 792 break; 793 case 1: 794 val |= __SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_LCDC1_TCON1, 795 SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC); 796 break; 797 default: 798 panic("tcon: invalid unid %d\n", sc->sc_unit); 799 } 800 #ifdef SUNXI_TCON_DEBUG 801 printf(" -> 0x%x", val); 802 #endif 803 bus_space_write_4(sc->sc_bst, tcon_mux_bsh, 0, val); 804 #ifdef SUNXI_TCON_DEBUG 805 printf(": 0x%" PRIxBSH " 0x%" PRIxBSH " 0x%x 0x%x\n", sc->sc_bsh, 806 tcon_mux_bsh, bus_space_read_4(sc->sc_bst, tcon_mux_bsh, 0), 807 TCON_READ(sc, SUNXI_TCON_MUX_CTL_REG)); 808 #endif 809 return 0; 810 } 811 812 void 813 sunxi_tcon1_set_videomode(device_t dev, const struct drm_display_mode *mode) 814 { 815 struct sunxi_tcon_softc *sc = device_private(dev); 816 uint32_t val; 817 int error; 818 819 KASSERT(device_is_a(dev, "sunxitcon")); 820 KASSERT((sc->sc_output_type == OUTPUT_HDMI) || 821 (sc->sc_output_type == OUTPUT_VGA)); 822 823 sunxi_debe_set_videomode(fdt_endpoint_device(sc->sc_in_rep), mode); 824 if (mode) { 825 const u_int interlace_p = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 826 const u_int phsync_p = !!(mode->flags & DRM_MODE_FLAG_PHSYNC); 827 const u_int pvsync_p = !!(mode->flags & DRM_MODE_FLAG_PVSYNC); 828 const u_int hspw = mode->hsync_end - mode->hsync_start; 829 const u_int hbp = mode->htotal - mode->hsync_start; 830 const u_int vspw = mode->vsync_end - mode->vsync_start; 831 const u_int vbp = mode->vtotal - mode->vsync_start; 832 const u_int vblank_len = 833 ((mode->vtotal << interlace_p) >> 1) - mode->vdisplay - 2; 834 const u_int start_delay = 835 vblank_len >= 32 ? 30 : vblank_len - 2; 836 837 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 838 val |= SUNXI_TCON_GCTL_IO_MAP_SEL; 839 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 840 841 /* enable */ 842 val = SUNXI_TCONx_CTL_EN; 843 if (interlace_p) 844 val |= SUNXI_TCONx_CTL_INTERLACE_EN; 845 val |= __SHIFTIN(start_delay, SUNXI_TCONx_CTL_START_DELAY); 846 #ifdef SUNXI_TCON1_BLUEDATA 847 val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_BLUEDATA, 848 SUNXI_TCONx_CTL_SRC_SEL); 849 #else 850 /* 851 * the DE selector selects the primary DEBE for this tcon: 852 * 0 selects debe0 for tcon0 and debe1 for tcon1 853 */ 854 val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_DE0, 855 SUNXI_TCONx_CTL_SRC_SEL); 856 #endif 857 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 858 859 /* Source width/height */ 860 TCON_WRITE(sc, SUNXI_TCON1_BASIC0_REG, 861 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 862 /* Scaler width/height */ 863 TCON_WRITE(sc, SUNXI_TCON1_BASIC1_REG, 864 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 865 /* Output width/height */ 866 TCON_WRITE(sc, SUNXI_TCON1_BASIC2_REG, 867 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 868 /* Horizontal total + back porch */ 869 TCON_WRITE(sc, SUNXI_TCON1_BASIC3_REG, 870 ((mode->htotal - 1) << 16) | (hbp - 1)); 871 /* Vertical total + back porch */ 872 u_int vtotal = mode->vtotal * 2; 873 if (interlace_p) { 874 u_int framerate = 875 DIVIDE(DIVIDE(mode->dot_clock * 1000, mode->htotal), 876 mode->vtotal); 877 u_int clk = mode->htotal * (mode->vtotal * 2 + 1) * 878 framerate; 879 if ((clk / 2) == mode->dot_clock * 1000) 880 vtotal += 1; 881 } 882 TCON_WRITE(sc, SUNXI_TCON1_BASIC4_REG, 883 (vtotal << 16) | (vbp - 1)); 884 885 /* Sync */ 886 TCON_WRITE(sc, SUNXI_TCON1_BASIC5_REG, 887 ((hspw - 1) << 16) | (vspw - 1)); 888 /* Polarity */ 889 val = SUNXI_TCON_IO_POL_IO2_INV; 890 if (phsync_p) 891 val |= SUNXI_TCON_IO_POL_PHSYNC; 892 if (pvsync_p) 893 val |= SUNXI_TCON_IO_POL_PVSYNC; 894 TCON_WRITE(sc, SUNXI_TCON1_IO_POL_REG, val); 895 896 TCON_WRITE(sc, SUNXI_TCON_GINT1_REG, 897 __SHIFTIN(start_delay + 2, SUNXI_TCON_GINT1_TCON1_LINENO)); 898 899 /* Setup LCDx CH1 PLL */ 900 error = clk_set_rate(sc->sc_clk_ch1, mode->dot_clock * 1000); 901 if (error) { 902 device_printf(sc->sc_dev, 903 ": failed to set ch1 clock to %d: %d\n", 904 mode->dot_clock, error); 905 } 906 error = clk_enable(sc->sc_clk_ch1); 907 if (error) { 908 device_printf(sc->sc_dev, 909 ": failed to enable ch1 clock: %d\n", 910 error); 911 } 912 } else { 913 /* disable */ 914 val = TCON_READ(sc, SUNXI_TCON1_CTL_REG); 915 val &= ~SUNXI_TCONx_CTL_EN; 916 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 917 error = clk_disable(sc->sc_clk_ch1); 918 if (error) { 919 device_printf(sc->sc_dev, 920 ": failed to disable ch1 clock: %d\n", 921 error); 922 } 923 } 924 } 925 926 /* check if this tcon is the console chosen by firmware */ 927 bool 928 sunxi_tcon_is_console(device_t dev, const char *pipeline) 929 { 930 struct sunxi_tcon_softc *sc = device_private(dev); 931 char p[64]; 932 char *e, *n = p; 933 bool is_console = false; 934 935 KASSERT(device_is_a(dev, "sunxitcon")); 936 strncpy(p, pipeline, sizeof(p) - 1); 937 p[sizeof(p) - 1] = '\0'; 938 939 /* 940 * pipeline is like "de_be0-lcd0-hdmi" 941 * of "de_be0-lcd1". 942 * In the first case check output type 943 * In the second check tcon unit number 944 */ 945 n = p; 946 e = strsep(&n, "-"); 947 if (e == NULL || memcmp(e, "de_be", 5) != 0) 948 goto bad; 949 e = strsep(&n, "-"); 950 if (e == NULL) 951 goto bad; 952 if (n == NULL) { 953 /* second case */ 954 if (strcmp(e, "lcd0") == 0) { 955 if (sc->sc_unit == 0) 956 is_console = true; 957 } else if (strcmp(e, "lcd1") == 0) { 958 if (sc->sc_unit == 1) 959 is_console = true; 960 } else 961 goto bad; 962 return is_console; 963 } 964 /* first case */ 965 if (strcmp(n, "hdmi") == 0) { 966 if (sc->sc_output_type == OUTPUT_HDMI) 967 is_console = true; 968 return is_console; 969 } 970 bad: 971 aprint_error("warning: can't parse pipeline %s\n", pipeline); 972 return is_console; 973 } 974 975 struct drm_crtc * 976 sunxi_tcon_get_crtc(device_t dev) 977 { 978 struct sunxi_tcon_softc *sc = device_private(dev); 979 return sunxi_debe_get_crtc(fdt_endpoint_device(sc->sc_in_rep)); 980 } 981 982 static int 983 sunxi_tcon_get_modes(struct drm_connector * conn) 984 { 985 struct drm_display_mode *mode; 986 const struct fdt_panel * panel; 987 988 panel = fdt_endpoint_get_data(fdt_endpoint_remote(sc->sc_out_ep)); 989 KASSERT(panel != NULL); 990 KASSERT(panel->panel_type == PANEL_DUAL_LVDS || 991 panel->panel_type == PANEL_LVDS); 992 sc->sc_output_type = OUTPUT_LVDS; 993 994 mode = drm_mode_create(connector->dev); 995 if (mode == NULL) 996 return ENOMEM; 997 998 mode->hdisplay = panel->panel_timing.hactive; 999 mode->hsync_start = mode->hdisplay + panel->panel_timing.hfront_porch; 1000 mode->hsync_end = mode->hsync_start + panel->panel_timing.hsync_len; 1001 mode->htotal = mode->hsync_end + panel->panel_timing.back_porch; 1002 mode->vdisplay = panel->panel_timing.vactive; 1003 mode->vsync_start = mode->vdisplay + panel->panel_timing.vfront_porch; 1004 mode->vsync_end = mode->vsync_start + panel->panel_timing.vsync_len; 1005 mode->vtotal = mode->vsync_end + panel->panel_timing.vback_porch; 1006 1007 mode->clock = panel->panel_timing.clock_freq / 1000; 1008 1009 /* XXX */ 1010 mode->flags |= DRM_MODE_FLAG_PHSYNC; 1011 mode->flags |= DRM_MODE_FLAG_PVSYNC; 1012 drm_mode_set_name(mode); 1013 return 0; 1014 } 1015 1016 #if defined(DDB) || defined(SUNXI_TCON_DEBUG) 1017 void 1018 sunxi_tcon_dump_regs(int u) 1019 { 1020 static const struct { 1021 const char *name; 1022 uint16_t reg; 1023 } regs[] = { 1024 { "TCON0_BASIC0_REG", SUNXI_TCON0_BASIC0_REG }, 1025 { "TCON0_BASIC1_REG", SUNXI_TCON0_BASIC1_REG }, 1026 { "TCON0_BASIC2_REG", SUNXI_TCON0_BASIC2_REG }, 1027 { "TCON0_BASIC3_REG", SUNXI_TCON0_BASIC3_REG }, 1028 { "TCON0_CTL_REG", SUNXI_TCON0_CTL_REG }, 1029 { "TCON0_DCLK_REG", SUNXI_TCON0_DCLK_REG }, 1030 { "TCON0_IO_POL_REG", SUNXI_TCON0_IO_POL_REG }, 1031 { "TCON0_IO_TRI_REG", SUNXI_TCON0_IO_TRI_REG }, 1032 { "TCON0_LVDS_IF_REG", SUNXI_TCON0_LVDS_IF_REG }, 1033 { "TCON1_BASIC0_REG", SUNXI_TCON1_BASIC0_REG }, 1034 { "TCON1_BASIC1_REG", SUNXI_TCON1_BASIC1_REG }, 1035 { "TCON1_BASIC2_REG", SUNXI_TCON1_BASIC2_REG }, 1036 { "TCON1_BASIC3_REG", SUNXI_TCON1_BASIC3_REG }, 1037 { "TCON1_BASIC4_REG", SUNXI_TCON1_BASIC4_REG }, 1038 { "TCON1_BASIC5_REG", SUNXI_TCON1_BASIC5_REG }, 1039 { "TCON1_CTL_REG", SUNXI_TCON1_CTL_REG }, 1040 { "TCON1_IO_POL_REG", SUNXI_TCON1_IO_POL_REG }, 1041 { "TCON1_IO_TRI_REG", SUNXI_TCON1_IO_TRI_REG }, 1042 { "TCON_GCTL_REG", SUNXI_TCON_GCTL_REG }, 1043 { "TCON_GINT0_REG", SUNXI_TCON_GINT0_REG }, 1044 { "TCON_GINT1_REG", SUNXI_TCON_GINT1_REG }, 1045 { "TCON_MUX_CTL_REG", SUNXI_TCON_MUX_CTL_REG }, 1046 }; 1047 struct sunxi_tcon_softc *sc; 1048 device_t dev; 1049 1050 dev = device_find_by_driver_unit("sunxitcon", u); 1051 if (dev == NULL) 1052 return; 1053 sc = device_private(dev); 1054 1055 for (int i = 0; i < __arraycount(regs); i++) { 1056 printf("%s: 0x%08x\n", regs[i].name, 1057 TCON_READ(sc, regs[i].reg)); 1058 } 1059 } 1060 #endif 1061
Indexes created Wed Oct 22 06:10:02 GMT 2025