sunxi_tcon.c revision 1.2
1 /* $NetBSD: sunxi_tcon.c,v 1.2 2018/04/03 13:38:13 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Manuel Bouyer <bouyer (at) antioche.eu.org> 5 * All rights reserved. 6 * 7 * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca> 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: sunxi_tcon.c,v 1.2 2018/04/03 13:38:13 bouyer Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 44 #include <dev/fdt/fdtvar.h> 45 #include <dev/fdt/fdt_port.h> 46 #include <dev/fdt/panel_fdt.h> 47 48 #include <dev/videomode/videomode.h> 49 50 #include <arm/sunxi/sunxi_tconreg.h> 51 #include <arm/sunxi/sunxi_display.h> 52 53 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 54 55 enum sunxi_tcon_type { 56 TCON_A10 = 1, 57 }; 58 59 struct sunxi_tcon_softc { 60 device_t sc_dev; 61 enum sunxi_tcon_type sc_type; 62 int sc_phandle; 63 bus_space_tag_t sc_bst; 64 bus_space_handle_t sc_bsh; 65 struct clk *sc_clk_ahb; 66 struct clk *sc_clk_ch0; 67 struct clk *sc_clk_ch1; 68 unsigned int sc_output_type; 69 #define OUTPUT_HDMI 0 70 #define OUTPUT_LVDS 1 71 #define OUTPUT_VGA 2 72 struct fdt_device_ports sc_ports; 73 int sc_unit; /* tcon0 or tcon1 */ 74 struct fdt_endpoint *sc_in_ep; 75 struct fdt_endpoint *sc_in_rep; 76 struct fdt_endpoint *sc_out_ep; 77 }; 78 79 static bus_space_handle_t tcon_mux_bsh; 80 static bool tcon_mux_inited = false; 81 82 static void sunxi_tcon_ep_connect(device_t, struct fdt_endpoint *, bool); 83 static int sunxi_tcon_ep_activate(device_t, struct fdt_endpoint *, bool); 84 static int sunxi_tcon_ep_enable(device_t, struct fdt_endpoint *, bool); 85 static int sunxi_tcon0_set_video(struct sunxi_tcon_softc *); 86 static int sunxi_tcon0_enable(struct sunxi_tcon_softc *, bool); 87 static int sunxi_tcon1_enable(struct sunxi_tcon_softc *, bool); 88 void sunxi_tcon_dump_regs(int); 89 90 #define TCON_READ(sc, reg) \ 91 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 92 #define TCON_WRITE(sc, reg, val) \ 93 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 94 95 static const struct of_compat_data compat_data[] = { 96 {"allwinner,sun4i-a10-tcon", TCON_A10}, 97 {"allwinner,sun7i-a20-tcon", TCON_A10}, 98 {NULL} 99 }; 100 101 static int sunxi_tcon_match(device_t, cfdata_t, void *); 102 static void sunxi_tcon_attach(device_t, device_t, void *); 103 104 CFATTACH_DECL_NEW(sunxi_tcon, sizeof(struct sunxi_tcon_softc), 105 sunxi_tcon_match, sunxi_tcon_attach, NULL, NULL); 106 107 static int 108 sunxi_tcon_match(device_t parent, cfdata_t cf, void *aux) 109 { 110 struct fdt_attach_args * const faa = aux; 111 112 return of_match_compat_data(faa->faa_phandle, compat_data); 113 } 114 115 static void 116 sunxi_tcon_attach(device_t parent, device_t self, void *aux) 117 { 118 struct sunxi_tcon_softc *sc = device_private(self); 119 struct fdt_attach_args * const faa = aux; 120 const int phandle = faa->faa_phandle; 121 bus_addr_t addr; 122 bus_size_t size; 123 struct fdtbus_reset *rst, *lvds_rst; 124 125 126 sc->sc_dev = self; 127 sc->sc_phandle = phandle; 128 sc->sc_bst = faa->faa_bst; 129 130 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 131 aprint_error(": couldn't get registers\n"); 132 } 133 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 134 aprint_error(": couldn't map registers\n"); 135 return; 136 } 137 138 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 139 sc->sc_clk_ch0 = fdtbus_clock_get(phandle, "tcon-ch0"); 140 sc->sc_clk_ch1 = fdtbus_clock_get(phandle, "tcon-ch1"); 141 142 if (sc->sc_clk_ahb == NULL || sc->sc_clk_ch0 == NULL 143 || sc->sc_clk_ch0 == NULL) { 144 aprint_error(": couldn't get clocks\n"); 145 aprint_debug_dev(self, "clk ahb %s tcon-ch0 %s tcon-ch1 %s\n", 146 sc->sc_clk_ahb == NULL ? "missing" : "present", 147 sc->sc_clk_ch0 == NULL ? "missing" : "present", 148 sc->sc_clk_ch1 == NULL ? "missing" : "present"); 149 return; 150 } 151 152 rst = fdtbus_reset_get(phandle, "lcd"); 153 if (rst == NULL) { 154 aprint_error(": couldn't get lcd reset\n"); 155 return; 156 } 157 158 lvds_rst = fdtbus_reset_get(phandle, "lvds"); 159 160 if (clk_disable(sc->sc_clk_ahb) != 0) { 161 aprint_error(": couldn't disable ahb clock\n"); 162 return; 163 } 164 if (clk_disable(sc->sc_clk_ch0) != 0) { 165 aprint_error(": couldn't disable ch0 clock\n"); 166 return; 167 } 168 169 if (clk_disable(sc->sc_clk_ch1) != 0) { 170 aprint_error(": couldn't disable ch1 clock\n"); 171 return; 172 } 173 174 if (fdtbus_reset_assert(rst) != 0) { 175 aprint_error(": couldn't assert lcd reset\n"); 176 return; 177 } 178 if (lvds_rst != NULL) { 179 if (fdtbus_reset_assert(lvds_rst) != 0) { 180 aprint_error(": couldn't assert lvds reset\n"); 181 return; 182 } 183 } 184 delay(1); 185 if (fdtbus_reset_deassert(rst) != 0) { 186 aprint_error(": couldn't de-assert lcd reset\n"); 187 return; 188 } 189 if (lvds_rst != NULL) { 190 if (fdtbus_reset_deassert(lvds_rst) != 0) { 191 aprint_error(": couldn't de-assert lvds reset\n"); 192 return; 193 } 194 } 195 196 if (clk_enable(sc->sc_clk_ahb) != 0) { 197 aprint_error(": couldn't enable ahb clock\n"); 198 return; 199 } 200 201 sc->sc_type = of_search_compatible(faa->faa_phandle, compat_data)->data; 202 203 aprint_naive("\n"); 204 aprint_normal(": LCD/TV timing controller (%s)\n", 205 fdtbus_get_string(phandle, "name")); 206 207 sc->sc_unit = -1; 208 sc->sc_ports.dp_ep_connect = sunxi_tcon_ep_connect; 209 sc->sc_ports.dp_ep_activate = sunxi_tcon_ep_activate; 210 sc->sc_ports.dp_ep_enable = sunxi_tcon_ep_enable; 211 fdt_ports_register(&sc->sc_ports, self, phandle, EP_OTHER); 212 213 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, 0); 214 TCON_WRITE(sc, SUNXI_TCON_GINT0_REG, 0); 215 TCON_WRITE(sc, SUNXI_TCON_GINT1_REG, 216 __SHIFTIN(0x20, SUNXI_TCON_GINT1_TCON0_LINENO)); 217 TCON_WRITE(sc, SUNXI_TCON0_DCLK_REG, 0xf0000000); 218 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, 0); 219 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0xffffffff); 220 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, 0); 221 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0xffffffff); 222 } 223 224 static void 225 sunxi_tcon_ep_connect(device_t self, struct fdt_endpoint *ep, bool connect) 226 { 227 struct sunxi_tcon_softc *sc = device_private(self); 228 struct fdt_endpoint *rep = fdt_endpoint_remote(ep); 229 int rep_idx = fdt_endpoint_index(rep); 230 231 KASSERT(device_is_a(self, "sunxitcon")); 232 if (!connect) { 233 aprint_error_dev(self, "endpoint disconnect not supported\n"); 234 return; 235 } 236 237 if (fdt_endpoint_port_index(ep) == 0) { 238 bool do_print = (sc->sc_unit == -1); 239 /* 240 * one of our input endpoints has been connected. 241 * the remote id is our unit number 242 */ 243 if (sc->sc_unit != -1 && rep_idx != -1 && 244 sc->sc_unit != rep_idx) { 245 aprint_error_dev(self, ": remote id %d doens't match" 246 " discovered unit number %d\n", 247 rep_idx, sc->sc_unit); 248 return; 249 } 250 if (!device_is_a(fdt_endpoint_device(rep), "sunxidebe")) { 251 aprint_error_dev(self, 252 ": input %d connected to unknown device\n", 253 fdt_endpoint_index(ep)); 254 return; 255 } 256 257 if (rep_idx != -1) 258 sc->sc_unit = rep_idx; 259 else { 260 /* assume only one tcon */ 261 sc->sc_unit = 0; 262 } 263 if (do_print) 264 aprint_verbose_dev(self, "tcon unit %d\n", sc->sc_unit); 265 if (!tcon_mux_inited && sc->sc_unit == 0) { 266 /* the mux register is only in LCD0 */ 267 bus_space_subregion(sc->sc_bst, sc->sc_bsh, 268 SUNXI_TCON_MUX_CTL_REG, 4, &tcon_mux_bsh); 269 tcon_mux_inited = true; 270 } 271 } else if (fdt_endpoint_port_index(ep) == 1) { 272 device_t rep_dev = fdt_endpoint_device(rep); 273 switch(fdt_endpoint_index(ep)) { 274 case 0: 275 break; 276 case 1: 277 if (!device_is_a(rep_dev, "sunxihdmi")) { 278 aprint_error_dev(self, 279 ": output 1 connected to unknown device\n"); 280 return; 281 } 282 break; 283 default: 284 break; 285 } 286 } 287 } 288 289 static int 290 sunxi_tcon_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 291 { 292 struct sunxi_tcon_softc *sc = device_private(dev); 293 struct fdt_endpoint *in_ep, *out_ep; 294 int outi; 295 int error = ENODEV; 296 297 KASSERT(device_is_a(dev, "sunxitcon")); 298 /* our input is activated by debe, we activate our output */ 299 if (fdt_endpoint_port_index(ep) != SUNXI_PORT_INPUT) { 300 panic("sunxi_tcon_ep_activate: port %d", 301 fdt_endpoint_port_index(ep)); 302 } 303 304 if (!activate) 305 return EOPNOTSUPP; 306 307 sc->sc_in_ep = ep; 308 sc->sc_in_rep = fdt_endpoint_remote(ep); 309 /* check that our other input is not active */ 310 switch (fdt_endpoint_index(ep)) { 311 case 0: 312 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 313 SUNXI_PORT_INPUT, 1); 314 break; 315 case 1: 316 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 317 SUNXI_PORT_INPUT, 0); 318 break; 319 default: 320 in_ep = NULL; 321 panic("sunxi_tcon_ep_activate: input index %d", 322 fdt_endpoint_index(ep)); 323 } 324 if (in_ep != NULL) { 325 if (fdt_endpoint_is_active(in_ep)) 326 return EBUSY; 327 } 328 /* try output 0 (RGB/LVDS) first, then ouput 1 (HDMI) if it fails */ 329 for (outi = 0; outi < 2; outi++) { 330 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 331 SUNXI_PORT_OUTPUT, outi); 332 if (out_ep == NULL) 333 continue; 334 error = fdt_endpoint_activate(out_ep, activate); 335 if (error == 0) { 336 struct fdt_endpoint *rep = fdt_endpoint_remote(out_ep); 337 aprint_verbose_dev(dev, "output to %s\n", 338 device_xname(fdt_endpoint_device(rep))); 339 sc->sc_out_ep = out_ep; 340 if (outi == 0) 341 return sunxi_tcon0_set_video(sc); 342 return 0; 343 } 344 } 345 if (out_ep == NULL) { 346 aprint_error_dev(dev, "no output endpoint\n"); 347 return ENODEV; 348 } 349 return error; 350 } 351 352 static int 353 sunxi_tcon_ep_enable(device_t dev, struct fdt_endpoint *ep, bool enable) 354 { 355 struct sunxi_tcon_softc *sc = device_private(dev); 356 int error; 357 KASSERT(device_is_a(dev, "sunxitcon")); 358 switch (fdt_endpoint_port_index(ep)) { 359 case SUNXI_PORT_INPUT: 360 KASSERT(ep == sc->sc_in_ep); 361 if (fdt_endpoint_index(sc->sc_out_ep) == 0) { 362 /* tcon0 active */ 363 return sunxi_tcon0_enable(sc, enable); 364 } 365 /* propagate to our output, it will get back to us */ 366 return fdt_endpoint_enable(sc->sc_out_ep, enable); 367 case SUNXI_PORT_OUTPUT: 368 KASSERT(ep == sc->sc_out_ep); 369 switch (fdt_endpoint_index(ep)) { 370 case 0: 371 panic("sunxi_tcon0_ep_enable"); 372 case 1: 373 error = sunxi_tcon1_enable(sc, enable); 374 break; 375 default: 376 panic("sunxi_tcon_ep_enable ep %d", 377 fdt_endpoint_index(ep)); 378 379 } 380 break; 381 default: 382 panic("sunxi_tcon_ep_enable port %d", fdt_endpoint_port_index(ep)); 383 } 384 #if defined(SUNXI_TCON_DEBUG) 385 sunxi_tcon_dump_regs(device_unit(dev)); 386 #endif 387 return error; 388 } 389 390 static int 391 sunxi_tcon0_set_video(struct sunxi_tcon_softc *sc) 392 { 393 const struct fdt_panel * panel; 394 int32_t lcd_x, lcd_y; 395 int32_t lcd_hbp, lcd_ht, lcd_vbp, lcd_vt; 396 int32_t lcd_hspw, lcd_vspw, lcd_io_cfg0; 397 uint32_t vblk, start_delay; 398 uint32_t val; 399 uint32_t best_div; 400 int best_diff, best_clk_freq, clk_freq, lcd_dclk_freq; 401 bool dualchan = false; 402 static struct videomode mode; 403 int error; 404 405 panel = fdt_endpoint_get_data(fdt_endpoint_remote(sc->sc_out_ep)); 406 KASSERT(panel != NULL); 407 KASSERT(panel->panel_type == PANEL_DUAL_LVDS || 408 panel->panel_type == PANEL_LVDS); 409 410 lcd_x = panel->panel_timing.hactive; 411 lcd_y = panel->panel_timing.vactive; 412 413 lcd_dclk_freq = panel->panel_timing.clock_freq; 414 415 lcd_hbp = panel->panel_timing.hback_porch; 416 lcd_hspw = panel->panel_timing.hsync_len; 417 lcd_ht = panel->panel_timing.hfront_porch + lcd_hspw + lcd_x + lcd_hbp; 418 419 lcd_vbp = panel->panel_timing.vback_porch; 420 lcd_vspw = panel->panel_timing.vsync_len; 421 lcd_vt = panel->panel_timing.vfront_porch + lcd_vspw + lcd_y + lcd_vbp; 422 423 lcd_io_cfg0 = 0x10000000; /* XXX */ 424 425 if (panel->panel_type == PANEL_DUAL_LVDS) 426 dualchan = true; 427 428 vblk = lcd_vt - lcd_y; 429 start_delay = (vblk >= 32) ? 30 : (vblk - 2); 430 431 if (lcd_dclk_freq > 150000000) /* hardware limit ? */ 432 lcd_dclk_freq = 150000000; 433 434 best_diff = INT_MAX; 435 best_div = 0; 436 best_clk_freq = 0; 437 for (u_int div = 7; div <= 15; div++) { 438 int dot_freq, diff; 439 clk_freq = clk_round_rate(sc->sc_clk_ch0, lcd_dclk_freq * div); 440 if (clk_freq == 0) 441 continue; 442 dot_freq = clk_freq / div; 443 diff = abs(lcd_dclk_freq - dot_freq); 444 if (best_diff > diff) { 445 best_diff = diff; 446 best_div = div; 447 best_clk_freq = clk_freq; 448 if (diff == 0) 449 break; 450 } 451 } 452 if (best_clk_freq == 0) { 453 device_printf(sc->sc_dev, 454 ": failed to find params for dot clock %d\n", 455 lcd_dclk_freq); 456 return EINVAL; 457 } 458 459 error = clk_set_rate(sc->sc_clk_ch0, best_clk_freq); 460 if (error) { 461 device_printf(sc->sc_dev, 462 ": failed to set ch0 clock to %d for %d: %d\n", 463 best_clk_freq, lcd_dclk_freq, error); 464 panic("tcon0 set clk"); 465 } 466 error = clk_enable(sc->sc_clk_ch0); 467 if (error) { 468 device_printf(sc->sc_dev, 469 ": failed to enable ch0 clock: %d\n", error); 470 return EIO; 471 } 472 473 val = __SHIFTIN(start_delay, SUNXI_TCONx_CTL_START_DELAY); 474 /* 475 * the DE selector selects the primary DEBE for this tcon: 476 * 0 selects debe0 for tcon0 and debe1 for tcon1 477 */ 478 val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_DE0, 479 SUNXI_TCONx_CTL_SRC_SEL); 480 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val); 481 482 val = (lcd_x - 1) << 16 | (lcd_y - 1); 483 TCON_WRITE(sc, SUNXI_TCON0_BASIC0_REG, val); 484 val = (lcd_ht - 1) << 16 | (lcd_hbp - 1); 485 TCON_WRITE(sc, SUNXI_TCON0_BASIC1_REG, val); 486 val = (lcd_vt * 2) << 16 | (lcd_vbp - 1); 487 TCON_WRITE(sc, SUNXI_TCON0_BASIC2_REG, val); 488 val = ((lcd_hspw > 0) ? (lcd_hspw - 1) : 0) << 16; 489 val |= ((lcd_vspw > 0) ? (lcd_vspw - 1) : 0); 490 TCON_WRITE(sc, SUNXI_TCON0_BASIC3_REG, val); 491 492 val = 0; 493 if (dualchan) 494 val |= SUNXI_TCON0_LVDS_IF_DUALCHAN; 495 if (panel->panel_lvds_format == LVDS_JEIDA_24) 496 val |= SUNXI_TCON0_LVDS_IF_MODE_JEIDA; 497 if (panel->panel_lvds_format == LVDS_JEIDA_18) 498 val |= SUNXI_TCON0_LVDS_IF_18BITS; 499 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val); 500 501 502 TCON_WRITE(sc, SUNXI_TCON0_IO_POL_REG, lcd_io_cfg0); 503 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0); 504 TCON_WRITE(sc, SUNXI_TCON_GINT1_REG, 505 __SHIFTIN(start_delay + 2, SUNXI_TCON_GINT1_TCON0_LINENO)); 506 507 val = 0xf0000000; 508 val &= ~SUNXI_TCON0_DCLK_DIV; 509 val |= __SHIFTIN(best_div, SUNXI_TCON0_DCLK_DIV); 510 TCON_WRITE(sc, SUNXI_TCON0_DCLK_REG, val); 511 512 mode.dot_clock = lcd_dclk_freq; 513 mode.hdisplay = lcd_x; 514 mode.hsync_start = lcd_ht - lcd_hbp; 515 mode.hsync_end = lcd_hspw + mode.hsync_start; 516 mode.htotal = lcd_ht; 517 mode.vdisplay = lcd_y; 518 mode.vsync_start = lcd_vt - lcd_vbp; 519 mode.vsync_end = lcd_vspw + mode.vsync_start; 520 mode.vtotal = lcd_vt; 521 mode.flags = 0; 522 mode.name = NULL; 523 524 sunxi_debe_set_videomode(fdt_endpoint_device(sc->sc_in_rep), &mode); 525 526 /* XXX 527 * magic values here from linux. these are not documented 528 * in the A20 user manual, and other Allwiner LVDS-capable SoC 529 * documentation don't make sense with these values 530 */ 531 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA0); 532 val |= 0x3F310000; 533 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val); 534 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA0); 535 val |= 1 << 22; 536 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val); 537 delay(2); 538 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA1); 539 val |= (0x1f << 26 | 0x1f << 10); 540 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA1, val); 541 delay(2); 542 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA1); 543 val |= (0x1f << 16 | 0x1f << 0); 544 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA1, val); 545 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA0); 546 val |= 1 << 22; 547 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val); 548 return 0; 549 } 550 551 static int 552 sunxi_tcon0_enable(struct sunxi_tcon_softc *sc, bool enable) 553 { 554 uint32_t val; 555 int error; 556 557 /* turn on/off backlight and lcd */ 558 error = fdt_endpoint_enable(sc->sc_out_ep, enable); 559 if (error) 560 return error; 561 562 /* and finally disable or enable the tcon */ 563 error = fdt_endpoint_enable(sc->sc_in_ep, enable); 564 if (error) 565 return error; 566 delay(20000); 567 if (enable) { 568 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 569 val |= SUNXI_TCON_GCTL_EN; 570 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 571 val = TCON_READ(sc, SUNXI_TCON0_CTL_REG); 572 val |= SUNXI_TCONx_CTL_EN; 573 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val); 574 val = TCON_READ(sc, SUNXI_TCON0_LVDS_IF_REG); 575 val |= SUNXI_TCON0_LVDS_IF_EN; 576 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val); 577 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0); 578 } else { 579 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0xffffffff); 580 val = TCON_READ(sc, SUNXI_TCON0_LVDS_IF_REG); 581 val &= ~SUNXI_TCON0_LVDS_IF_EN; 582 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val); 583 val = TCON_READ(sc, SUNXI_TCON0_CTL_REG); 584 val &= ~SUNXI_TCONx_CTL_EN; 585 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val); 586 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 587 val &= ~SUNXI_TCON_GCTL_EN; 588 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 589 } 590 #ifdef SUNXI_TCON_DEBUG 591 sunxi_tcon_dump_regs(device_unit(sc->sc_dev)); 592 #endif 593 return 0; 594 } 595 596 static int 597 sunxi_tcon1_enable(struct sunxi_tcon_softc *sc, bool enable) 598 { 599 uint32_t val; 600 601 KASSERT((sc->sc_output_type == OUTPUT_HDMI) || 602 (sc->sc_output_type == OUTPUT_VGA)); 603 604 fdt_endpoint_enable(sc->sc_in_ep, enable); 605 delay(20000); 606 if (enable) { 607 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 608 val |= SUNXI_TCON_GCTL_EN; 609 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 610 val = TCON_READ(sc, SUNXI_TCON1_CTL_REG); 611 val |= SUNXI_TCONx_CTL_EN; 612 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 613 if (sc->sc_output_type == OUTPUT_VGA) { 614 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0x0cffffff); 615 } else 616 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0); 617 } else { 618 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0xffffffff); 619 val = TCON_READ(sc, SUNXI_TCON1_CTL_REG); 620 val &= ~SUNXI_TCONx_CTL_EN; 621 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 622 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 623 val &= ~SUNXI_TCON_GCTL_EN; 624 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 625 } 626 627 KASSERT(tcon_mux_inited); 628 val = bus_space_read_4(sc->sc_bst, tcon_mux_bsh, 0); 629 #ifdef SUNXI_TCON_DEBUG 630 printf("sunxi_tcon1_enable(%d) %d val 0x%x", sc->sc_unit, enable, val); 631 #endif 632 val &= ~ SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC; 633 switch(sc->sc_unit) { 634 case 0: 635 val |= __SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_LCDC0_TCON1, 636 SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC); 637 break; 638 case 1: 639 val |= __SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_LCDC1_TCON1, 640 SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC); 641 break; 642 default: 643 panic("tcon: invalid unid %d\n", sc->sc_unit); 644 } 645 #ifdef SUNXI_TCON_DEBUG 646 printf(" -> 0x%x", val); 647 #endif 648 bus_space_write_4(sc->sc_bst, tcon_mux_bsh, 0, val); 649 #ifdef SUNXI_TCON_DEBUG 650 printf(": 0x%" PRIxBSH " 0x%" PRIxBSH " 0x%x 0x%x\n", sc->sc_bsh, 651 tcon_mux_bsh, bus_space_read_4(sc->sc_bst, tcon_mux_bsh, 0), 652 TCON_READ(sc, SUNXI_TCON_MUX_CTL_REG)); 653 #endif 654 return 0; 655 } 656 657 void 658 sunxi_tcon1_set_videomode(device_t dev, const struct videomode *mode) 659 { 660 struct sunxi_tcon_softc *sc = device_private(dev); 661 uint32_t val; 662 int error; 663 664 KASSERT(device_is_a(dev, "sunxitcon")); 665 sc = device_private(dev); 666 KASSERT((sc->sc_output_type == OUTPUT_HDMI) || 667 (sc->sc_output_type == OUTPUT_VGA)); 668 669 sunxi_debe_set_videomode(fdt_endpoint_device(sc->sc_in_rep), mode); 670 if (mode) { 671 const u_int interlace_p = !!(mode->flags & VID_INTERLACE); 672 const u_int phsync_p = !!(mode->flags & VID_PHSYNC); 673 const u_int pvsync_p = !!(mode->flags & VID_PVSYNC); 674 const u_int hspw = mode->hsync_end - mode->hsync_start; 675 const u_int hbp = mode->htotal - mode->hsync_start; 676 const u_int vspw = mode->vsync_end - mode->vsync_start; 677 const u_int vbp = mode->vtotal - mode->vsync_start; 678 const u_int vblank_len = 679 ((mode->vtotal << interlace_p) >> 1) - mode->vdisplay - 2; 680 const u_int start_delay = 681 vblank_len >= 32 ? 30 : vblank_len - 2; 682 683 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 684 val |= SUNXI_TCON_GCTL_IO_MAP_SEL; 685 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 686 687 /* enable */ 688 val = SUNXI_TCONx_CTL_EN; 689 if (interlace_p) 690 val |= SUNXI_TCONx_CTL_INTERLACE_EN; 691 val |= __SHIFTIN(start_delay, SUNXI_TCONx_CTL_START_DELAY); 692 #ifdef SUNXI_TCON1_BLUEDATA 693 val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_BLUEDATA, 694 SUNXI_TCONx_CTL_SRC_SEL); 695 #else 696 /* 697 * the DE selector selects the primary DEBE for this tcon: 698 * 0 selects debe0 for tcon0 and debe1 for tcon1 699 */ 700 val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_DE0, 701 SUNXI_TCONx_CTL_SRC_SEL); 702 #endif 703 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 704 705 /* Source width/height */ 706 TCON_WRITE(sc, SUNXI_TCON1_BASIC0_REG, 707 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 708 /* Scaler width/height */ 709 TCON_WRITE(sc, SUNXI_TCON1_BASIC1_REG, 710 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 711 /* Output width/height */ 712 TCON_WRITE(sc, SUNXI_TCON1_BASIC2_REG, 713 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 714 /* Horizontal total + back porch */ 715 TCON_WRITE(sc, SUNXI_TCON1_BASIC3_REG, 716 ((mode->htotal - 1) << 16) | (hbp - 1)); 717 /* Vertical total + back porch */ 718 u_int vtotal = mode->vtotal * 2; 719 if (interlace_p) { 720 u_int framerate = 721 DIVIDE(DIVIDE(mode->dot_clock * 1000, mode->htotal), 722 mode->vtotal); 723 u_int clk = mode->htotal * (mode->vtotal * 2 + 1) * 724 framerate; 725 if ((clk / 2) == mode->dot_clock * 1000) 726 vtotal += 1; 727 } 728 TCON_WRITE(sc, SUNXI_TCON1_BASIC4_REG, 729 (vtotal << 16) | (vbp - 1)); 730 731 /* Sync */ 732 TCON_WRITE(sc, SUNXI_TCON1_BASIC5_REG, 733 ((hspw - 1) << 16) | (vspw - 1)); 734 /* Polarity */ 735 val = SUNXI_TCON_IO_POL_IO2_INV; 736 if (phsync_p) 737 val |= SUNXI_TCON_IO_POL_PHSYNC; 738 if (pvsync_p) 739 val |= SUNXI_TCON_IO_POL_PVSYNC; 740 TCON_WRITE(sc, SUNXI_TCON1_IO_POL_REG, val); 741 742 TCON_WRITE(sc, SUNXI_TCON_GINT1_REG, 743 __SHIFTIN(start_delay + 2, SUNXI_TCON_GINT1_TCON1_LINENO)); 744 745 /* Setup LCDx CH1 PLL */ 746 error = clk_set_rate(sc->sc_clk_ch1, mode->dot_clock * 1000); 747 if (error) { 748 device_printf(sc->sc_dev, 749 ": failed to set ch1 clock to %d: %d\n", 750 mode->dot_clock, error); 751 } 752 error = clk_enable(sc->sc_clk_ch1); 753 if (error) { 754 device_printf(sc->sc_dev, 755 ": failed to enable ch1 clock: %d\n", 756 error); 757 } 758 } else { 759 /* disable */ 760 val = TCON_READ(sc, SUNXI_TCON1_CTL_REG); 761 val &= ~SUNXI_TCONx_CTL_EN; 762 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 763 error = clk_disable(sc->sc_clk_ch1); 764 if (error) { 765 device_printf(sc->sc_dev, 766 ": failed to disable ch1 clock: %d\n", 767 error); 768 } 769 } 770 } 771 772 #if defined(DDB) || defined(SUNXI_TCON_DEBUG) 773 void 774 sunxi_tcon_dump_regs(int u) 775 { 776 static const struct { 777 const char *name; 778 uint16_t reg; 779 } regs[] = { 780 { "TCON0_BASIC0_REG", SUNXI_TCON0_BASIC0_REG }, 781 { "TCON0_BASIC1_REG", SUNXI_TCON0_BASIC1_REG }, 782 { "TCON0_BASIC2_REG", SUNXI_TCON0_BASIC2_REG }, 783 { "TCON0_BASIC3_REG", SUNXI_TCON0_BASIC3_REG }, 784 { "TCON0_CTL_REG", SUNXI_TCON0_CTL_REG }, 785 { "TCON0_DCLK_REG", SUNXI_TCON0_DCLK_REG }, 786 { "TCON0_IO_POL_REG", SUNXI_TCON0_IO_POL_REG }, 787 { "TCON0_IO_TRI_REG", SUNXI_TCON0_IO_TRI_REG }, 788 { "TCON0_LVDS_IF_REG", SUNXI_TCON0_LVDS_IF_REG }, 789 { "TCON1_BASIC0_REG", SUNXI_TCON1_BASIC0_REG }, 790 { "TCON1_BASIC1_REG", SUNXI_TCON1_BASIC1_REG }, 791 { "TCON1_BASIC2_REG", SUNXI_TCON1_BASIC2_REG }, 792 { "TCON1_BASIC3_REG", SUNXI_TCON1_BASIC3_REG }, 793 { "TCON1_BASIC4_REG", SUNXI_TCON1_BASIC4_REG }, 794 { "TCON1_BASIC5_REG", SUNXI_TCON1_BASIC5_REG }, 795 { "TCON1_CTL_REG", SUNXI_TCON1_CTL_REG }, 796 { "TCON1_IO_POL_REG", SUNXI_TCON1_IO_POL_REG }, 797 { "TCON1_IO_TRI_REG", SUNXI_TCON1_IO_TRI_REG }, 798 { "TCON_GCTL_REG", SUNXI_TCON_GCTL_REG }, 799 { "TCON_GINT0_REG", SUNXI_TCON_GINT0_REG }, 800 { "TCON_GINT1_REG", SUNXI_TCON_GINT1_REG }, 801 { "TCON_MUX_CTL_REG", SUNXI_TCON_MUX_CTL_REG }, 802 }; 803 struct sunxi_tcon_softc *sc; 804 device_t dev; 805 806 dev = device_find_by_driver_unit("sunxitcon", u); 807 if (dev == NULL) 808 return; 809 sc = device_private(dev); 810 811 for (int i = 0; i < __arraycount(regs); i++) { 812 printf("%s: 0x%08x\n", regs[i].name, 813 TCON_READ(sc, regs[i].reg)); 814 } 815 } 816 #endif 817
Indexes created Wed Oct 01 07:09:59 GMT 2025