sunxi_tcon.c revision 1.8
1 /* $NetBSD: sunxi_tcon.c,v 1.8 2021/01/18 02:35:49 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Manuel Bouyer <bouyer (at) antioche.eu.org> 5 * All rights reserved. 6 * 7 * Copyright (c) 2014 Jared D. McNeill <jmcneill (at) invisible.ca> 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: sunxi_tcon.c,v 1.8 2021/01/18 02:35:49 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 44 #include <dev/fdt/fdtvar.h> 45 #include <dev/fdt/fdt_port.h> 46 #include <dev/fdt/panel_fdt.h> 47 48 #include <dev/videomode/videomode.h> 49 50 #include <arm/sunxi/sunxi_tconreg.h> 51 #include <arm/sunxi/sunxi_display.h> 52 53 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 54 55 enum sunxi_tcon_type { 56 TCON_A10 = 1, 57 }; 58 59 struct sunxi_tcon_softc { 60 device_t sc_dev; 61 enum sunxi_tcon_type sc_type; 62 int sc_phandle; 63 bus_space_tag_t sc_bst; 64 bus_space_handle_t sc_bsh; 65 struct clk *sc_clk_ahb; 66 struct clk *sc_clk_ch0; 67 struct clk *sc_clk_ch1; 68 struct fdtbus_reset *sc_rst, *sc_lvds_rst; 69 unsigned int sc_output_type; 70 #define OUTPUT_HDMI 0 71 #define OUTPUT_LVDS 1 72 #define OUTPUT_VGA 2 73 struct fdt_device_ports sc_ports; 74 int sc_unit; /* tcon0 or tcon1 */ 75 struct fdt_endpoint *sc_in_ep; 76 struct fdt_endpoint *sc_in_rep; 77 struct fdt_endpoint *sc_out_ep; 78 }; 79 80 static bus_space_handle_t tcon_mux_bsh; 81 static bool tcon_mux_inited = false; 82 83 static void sunxi_tcon_ep_connect(device_t, struct fdt_endpoint *, bool); 84 static int sunxi_tcon_ep_activate(device_t, struct fdt_endpoint *, bool); 85 static int sunxi_tcon_ep_enable(device_t, struct fdt_endpoint *, bool); 86 static int sunxi_tcon0_set_video(struct sunxi_tcon_softc *); 87 static int sunxi_tcon0_enable(struct sunxi_tcon_softc *, bool); 88 static int sunxi_tcon1_enable(struct sunxi_tcon_softc *, bool); 89 void sunxi_tcon_dump_regs(int); 90 91 #define TCON_READ(sc, reg) \ 92 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 93 #define TCON_WRITE(sc, reg, val) \ 94 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 95 96 static const struct device_compatible_entry compat_data[] = { 97 { .compat = "allwinner,sun4i-a10-tcon", .value = TCON_A10}, 98 { .compat = "allwinner,sun7i-a20-tcon", .value = TCON_A10}, 99 100 { 0 } 101 }; 102 103 static int sunxi_tcon_match(device_t, cfdata_t, void *); 104 static void sunxi_tcon_attach(device_t, device_t, void *); 105 106 CFATTACH_DECL_NEW(sunxi_tcon, sizeof(struct sunxi_tcon_softc), 107 sunxi_tcon_match, sunxi_tcon_attach, NULL, NULL); 108 109 static int 110 sunxi_tcon_match(device_t parent, cfdata_t cf, void *aux) 111 { 112 struct fdt_attach_args * const faa = aux; 113 114 return of_match_compat_data(faa->faa_phandle, compat_data); 115 } 116 117 static void 118 sunxi_tcon_attach(device_t parent, device_t self, void *aux) 119 { 120 struct sunxi_tcon_softc *sc = device_private(self); 121 struct fdt_attach_args * const faa = aux; 122 const int phandle = faa->faa_phandle; 123 bus_addr_t addr; 124 bus_size_t size; 125 126 sc->sc_dev = self; 127 sc->sc_phandle = phandle; 128 sc->sc_bst = faa->faa_bst; 129 130 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 131 aprint_error(": couldn't get registers\n"); 132 } 133 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 134 aprint_error(": couldn't map registers\n"); 135 return; 136 } 137 138 sc->sc_clk_ahb = fdtbus_clock_get(phandle, "ahb"); 139 sc->sc_clk_ch0 = fdtbus_clock_get(phandle, "tcon-ch0"); 140 sc->sc_clk_ch1 = fdtbus_clock_get(phandle, "tcon-ch1"); 141 142 if (sc->sc_clk_ahb == NULL || sc->sc_clk_ch0 == NULL 143 || sc->sc_clk_ch1 == NULL) { 144 aprint_error(": couldn't get clocks\n"); 145 aprint_debug_dev(self, "clk ahb %s tcon-ch0 %s tcon-ch1 %s\n", 146 sc->sc_clk_ahb == NULL ? "missing" : "present", 147 sc->sc_clk_ch0 == NULL ? "missing" : "present", 148 sc->sc_clk_ch1 == NULL ? "missing" : "present"); 149 return; 150 } 151 152 sc->sc_rst = fdtbus_reset_get(phandle, "lcd"); 153 if (sc->sc_rst == NULL) { 154 aprint_error(": couldn't get lcd reset\n"); 155 return; 156 } 157 158 sc->sc_lvds_rst = fdtbus_reset_get(phandle, "lvds"); 159 160 sc->sc_type = 161 of_search_compatible(faa->faa_phandle, compat_data)->value; 162 163 aprint_naive("\n"); 164 aprint_normal(": LCD/TV timing controller (%s)\n", 165 fdtbus_get_string(phandle, "name")); 166 167 sc->sc_unit = -1; 168 sc->sc_ports.dp_ep_connect = sunxi_tcon_ep_connect; 169 sc->sc_ports.dp_ep_activate = sunxi_tcon_ep_activate; 170 sc->sc_ports.dp_ep_enable = sunxi_tcon_ep_enable; 171 fdt_ports_register(&sc->sc_ports, self, phandle, EP_OTHER); 172 } 173 174 void 175 sunxi_tcon_doreset(void) 176 { 177 device_t dev; 178 struct sunxi_tcon_softc *sc; 179 for (int i = 0;;i++) { 180 dev = device_find_by_driver_unit("sunxitcon", i); 181 if (dev == NULL) 182 return; 183 sc = device_private(dev); 184 185 if (clk_disable(sc->sc_clk_ahb) != 0) { 186 aprint_error_dev(dev, ": couldn't disable ahb clock\n"); 187 return; 188 } 189 if (clk_disable(sc->sc_clk_ch0) != 0) { 190 aprint_error_dev(dev, ": couldn't disable ch0 clock\n"); 191 return; 192 } 193 194 if (clk_disable(sc->sc_clk_ch1) != 0) { 195 aprint_error_dev(dev, ": couldn't disable ch1 clock\n"); 196 return; 197 } 198 199 if (fdtbus_reset_assert(sc->sc_rst) != 0) { 200 aprint_error_dev(dev, ": couldn't assert lcd reset\n"); 201 return; 202 } 203 if (sc->sc_lvds_rst != NULL) { 204 if (fdtbus_reset_assert(sc->sc_lvds_rst) != 0) { 205 aprint_error_dev(dev, 206 ": couldn't assert lvds reset\n"); 207 return; 208 } 209 } 210 delay(1); 211 if (fdtbus_reset_deassert(sc->sc_rst) != 0) { 212 aprint_error_dev(dev, 213 ": couldn't de-assert lcd reset\n"); 214 return; 215 } 216 if (sc->sc_lvds_rst != NULL) { 217 if (fdtbus_reset_deassert(sc->sc_lvds_rst) != 0) { 218 aprint_error_dev(dev, 219 ": couldn't de-assert lvds reset\n"); 220 return; 221 } 222 } 223 224 if (clk_enable(sc->sc_clk_ahb) != 0) { 225 aprint_error_dev(dev, ": couldn't enable ahb clock\n"); 226 return; 227 } 228 229 TCON_WRITE(sc, SUNXI_TCON_GINT0_REG, 0); 230 TCON_WRITE(sc, SUNXI_TCON_GINT1_REG, 231 __SHIFTIN(0x20, SUNXI_TCON_GINT1_TCON0_LINENO)); 232 TCON_WRITE(sc, SUNXI_TCON0_DCLK_REG, 0xf0000000); 233 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, 0x0); 234 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, 0); 235 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0xffffffff); 236 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, 0); 237 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0xffffffff); 238 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, 0); 239 240 /* clock needed for the mux in unit 0 */ 241 if (sc->sc_unit != 0) { 242 if (clk_disable(sc->sc_clk_ahb) != 0) { 243 aprint_error_dev(dev, 244 ": couldn't disable ahb clock\n"); 245 return; 246 } 247 } 248 } 249 } 250 251 static void 252 sunxi_tcon_ep_connect(device_t self, struct fdt_endpoint *ep, bool connect) 253 { 254 struct sunxi_tcon_softc *sc = device_private(self); 255 struct fdt_endpoint *rep = fdt_endpoint_remote(ep); 256 int rep_idx = fdt_endpoint_index(rep); 257 258 KASSERT(device_is_a(self, "sunxitcon")); 259 if (!connect) { 260 aprint_error_dev(self, "endpoint disconnect not supported\n"); 261 return; 262 } 263 264 if (fdt_endpoint_port_index(ep) == 0) { 265 bool do_print = (sc->sc_unit == -1); 266 /* 267 * one of our input endpoints has been connected. 268 * the remote id is our unit number 269 */ 270 if (sc->sc_unit != -1 && rep_idx != -1 && 271 sc->sc_unit != rep_idx) { 272 aprint_error_dev(self, ": remote id %d doens't match" 273 " discovered unit number %d\n", 274 rep_idx, sc->sc_unit); 275 return; 276 } 277 if (!device_is_a(fdt_endpoint_device(rep), "sunxidebe")) { 278 aprint_error_dev(self, 279 ": input %d connected to unknown device\n", 280 fdt_endpoint_index(ep)); 281 return; 282 } 283 284 if (rep_idx != -1) 285 sc->sc_unit = rep_idx; 286 else { 287 /* assume only one tcon */ 288 sc->sc_unit = 0; 289 } 290 if (do_print) 291 aprint_verbose_dev(self, "tcon unit %d\n", sc->sc_unit); 292 if (!tcon_mux_inited && sc->sc_unit == 0) { 293 /* the mux register is only in LCD0 */ 294 if (clk_enable(sc->sc_clk_ahb) != 0) { 295 aprint_error_dev(self, 296 "couldn't enable ahb clock\n"); 297 return; 298 } 299 bus_space_subregion(sc->sc_bst, sc->sc_bsh, 300 SUNXI_TCON_MUX_CTL_REG, 4, &tcon_mux_bsh); 301 tcon_mux_inited = true; 302 bus_space_write_4(sc->sc_bst, tcon_mux_bsh, 0, 303 __SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_CLOSE, 304 SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC)); 305 } 306 } else if (fdt_endpoint_port_index(ep) == 1) { 307 device_t rep_dev = fdt_endpoint_device(rep); 308 switch(fdt_endpoint_index(ep)) { 309 case 0: 310 break; 311 case 1: 312 if (!device_is_a(rep_dev, "sunxihdmi")) { 313 aprint_error_dev(self, 314 ": output 1 connected to unknown device\n"); 315 return; 316 } 317 break; 318 default: 319 break; 320 } 321 } 322 } 323 324 static int 325 sunxi_tcon_ep_activate(device_t dev, struct fdt_endpoint *ep, bool activate) 326 { 327 struct sunxi_tcon_softc *sc = device_private(dev); 328 struct fdt_endpoint *in_ep, *out_ep; 329 int outi; 330 int error = ENODEV; 331 332 KASSERT(device_is_a(dev, "sunxitcon")); 333 /* our input is activated by debe, we activate our output */ 334 if (fdt_endpoint_port_index(ep) != SUNXI_PORT_INPUT) { 335 panic("sunxi_tcon_ep_activate: port %d", 336 fdt_endpoint_port_index(ep)); 337 } 338 339 if (!activate) 340 return EOPNOTSUPP; 341 342 if (clk_enable(sc->sc_clk_ahb) != 0) { 343 aprint_error_dev(dev, "couldn't enable ahb clock\n"); 344 return EIO; 345 } 346 sc->sc_in_ep = ep; 347 sc->sc_in_rep = fdt_endpoint_remote(ep); 348 /* check that our other input is not active */ 349 switch (fdt_endpoint_index(ep)) { 350 case 0: 351 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 352 SUNXI_PORT_INPUT, 1); 353 break; 354 case 1: 355 in_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 356 SUNXI_PORT_INPUT, 0); 357 break; 358 default: 359 in_ep = NULL; 360 panic("sunxi_tcon_ep_activate: input index %d", 361 fdt_endpoint_index(ep)); 362 } 363 if (in_ep != NULL) { 364 if (fdt_endpoint_is_active(in_ep)) 365 return EBUSY; 366 } 367 /* try output 0 (RGB/LVDS) first, then ouput 1 (HDMI) if it fails */ 368 for (outi = 0; outi < 2; outi++) { 369 out_ep = fdt_endpoint_get_from_index(&sc->sc_ports, 370 SUNXI_PORT_OUTPUT, outi); 371 if (out_ep == NULL) 372 continue; 373 error = fdt_endpoint_activate(out_ep, activate); 374 if (error == 0) { 375 struct fdt_endpoint *rep = fdt_endpoint_remote(out_ep); 376 aprint_verbose_dev(dev, "output to %s\n", 377 device_xname(fdt_endpoint_device(rep))); 378 sc->sc_out_ep = out_ep; 379 if (outi == 0) 380 return sunxi_tcon0_set_video(sc); 381 /* XXX should check VGA here */ 382 sc->sc_output_type = OUTPUT_HDMI; 383 return 0; 384 } 385 } 386 if (out_ep == NULL) { 387 aprint_error_dev(dev, "no output endpoint\n"); 388 return ENODEV; 389 } 390 return error; 391 } 392 393 static int 394 sunxi_tcon_ep_enable(device_t dev, struct fdt_endpoint *ep, bool enable) 395 { 396 struct sunxi_tcon_softc *sc = device_private(dev); 397 int error; 398 KASSERT(device_is_a(dev, "sunxitcon")); 399 switch (fdt_endpoint_port_index(ep)) { 400 case SUNXI_PORT_INPUT: 401 KASSERT(ep == sc->sc_in_ep); 402 if (fdt_endpoint_index(sc->sc_out_ep) == 0) { 403 /* tcon0 active */ 404 return sunxi_tcon0_enable(sc, enable); 405 } 406 /* propagate to our output, it will get back to us */ 407 return fdt_endpoint_enable(sc->sc_out_ep, enable); 408 case SUNXI_PORT_OUTPUT: 409 KASSERT(ep == sc->sc_out_ep); 410 switch (fdt_endpoint_index(ep)) { 411 case 0: 412 panic("sunxi_tcon0_ep_enable"); 413 case 1: 414 error = sunxi_tcon1_enable(sc, enable); 415 break; 416 default: 417 panic("sunxi_tcon_ep_enable ep %d", 418 fdt_endpoint_index(ep)); 419 420 } 421 break; 422 default: 423 panic("sunxi_tcon_ep_enable port %d", fdt_endpoint_port_index(ep)); 424 } 425 #if defined(SUNXI_TCON_DEBUG) 426 sunxi_tcon_dump_regs(device_unit(dev)); 427 #endif 428 return error; 429 } 430 431 static int 432 sunxi_tcon0_set_video(struct sunxi_tcon_softc *sc) 433 { 434 const struct fdt_panel * panel; 435 int32_t lcd_x, lcd_y; 436 int32_t lcd_hbp, lcd_ht, lcd_vbp, lcd_vt; 437 int32_t lcd_hspw, lcd_vspw, lcd_io_cfg0; 438 uint32_t vblk, start_delay; 439 uint32_t val; 440 uint32_t best_div; 441 int best_diff, best_clk_freq, clk_freq, lcd_dclk_freq; 442 bool dualchan = false; 443 static struct videomode mode; 444 int error; 445 446 panel = fdt_endpoint_get_data(fdt_endpoint_remote(sc->sc_out_ep)); 447 KASSERT(panel != NULL); 448 KASSERT(panel->panel_type == PANEL_DUAL_LVDS || 449 panel->panel_type == PANEL_LVDS); 450 sc->sc_output_type = OUTPUT_LVDS; 451 452 lcd_x = panel->panel_timing.hactive; 453 lcd_y = panel->panel_timing.vactive; 454 455 lcd_dclk_freq = panel->panel_timing.clock_freq; 456 457 lcd_hbp = panel->panel_timing.hback_porch; 458 lcd_hspw = panel->panel_timing.hsync_len; 459 lcd_ht = panel->panel_timing.hfront_porch + lcd_hspw + lcd_x + lcd_hbp; 460 461 lcd_vbp = panel->panel_timing.vback_porch; 462 lcd_vspw = panel->panel_timing.vsync_len; 463 lcd_vt = panel->panel_timing.vfront_porch + lcd_vspw + lcd_y + lcd_vbp; 464 465 lcd_io_cfg0 = 0x10000000; /* XXX */ 466 467 if (panel->panel_type == PANEL_DUAL_LVDS) 468 dualchan = true; 469 470 vblk = lcd_vt - lcd_y; 471 start_delay = (vblk >= 32) ? 30 : (vblk - 2); 472 473 if (lcd_dclk_freq > 150000000) /* hardware limit ? */ 474 lcd_dclk_freq = 150000000; 475 476 best_diff = INT_MAX; 477 best_div = 0; 478 best_clk_freq = 0; 479 for (u_int div = 7; div <= 15; div++) { 480 int dot_freq, diff; 481 clk_freq = clk_round_rate(sc->sc_clk_ch0, lcd_dclk_freq * div); 482 if (clk_freq == 0) 483 continue; 484 dot_freq = clk_freq / div; 485 diff = abs(lcd_dclk_freq - dot_freq); 486 if (best_diff > diff) { 487 best_diff = diff; 488 best_div = div; 489 best_clk_freq = clk_freq; 490 if (diff == 0) 491 break; 492 } 493 } 494 if (best_clk_freq == 0) { 495 device_printf(sc->sc_dev, 496 ": failed to find params for dot clock %d\n", 497 lcd_dclk_freq); 498 return EINVAL; 499 } 500 501 error = clk_set_rate(sc->sc_clk_ch0, best_clk_freq); 502 if (error) { 503 device_printf(sc->sc_dev, 504 ": failed to set ch0 clock to %d for %d: %d\n", 505 best_clk_freq, lcd_dclk_freq, error); 506 panic("tcon0 set clk"); 507 } 508 error = clk_enable(sc->sc_clk_ch0); 509 if (error) { 510 device_printf(sc->sc_dev, 511 ": failed to enable ch0 clock: %d\n", error); 512 return EIO; 513 } 514 515 val = __SHIFTIN(start_delay, SUNXI_TCONx_CTL_START_DELAY); 516 /* 517 * the DE selector selects the primary DEBE for this tcon: 518 * 0 selects debe0 for tcon0 and debe1 for tcon1 519 */ 520 val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_DE0, 521 SUNXI_TCONx_CTL_SRC_SEL); 522 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val); 523 524 val = (lcd_x - 1) << 16 | (lcd_y - 1); 525 TCON_WRITE(sc, SUNXI_TCON0_BASIC0_REG, val); 526 val = (lcd_ht - 1) << 16 | (lcd_hbp - 1); 527 TCON_WRITE(sc, SUNXI_TCON0_BASIC1_REG, val); 528 val = (lcd_vt * 2) << 16 | (lcd_vbp - 1); 529 TCON_WRITE(sc, SUNXI_TCON0_BASIC2_REG, val); 530 val = ((lcd_hspw > 0) ? (lcd_hspw - 1) : 0) << 16; 531 val |= ((lcd_vspw > 0) ? (lcd_vspw - 1) : 0); 532 TCON_WRITE(sc, SUNXI_TCON0_BASIC3_REG, val); 533 534 val = 0; 535 if (dualchan) 536 val |= SUNXI_TCON0_LVDS_IF_DUALCHAN; 537 if (panel->panel_lvds_format == LVDS_JEIDA_24) 538 val |= SUNXI_TCON0_LVDS_IF_MODE_JEIDA; 539 if (panel->panel_lvds_format == LVDS_JEIDA_18) 540 val |= SUNXI_TCON0_LVDS_IF_18BITS; 541 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val); 542 543 TCON_WRITE(sc, SUNXI_TCON0_IO_POL_REG, lcd_io_cfg0); 544 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0); 545 TCON_WRITE(sc, SUNXI_TCON_GINT1_REG, 546 __SHIFTIN(start_delay + 2, SUNXI_TCON_GINT1_TCON0_LINENO)); 547 548 val = 0xf0000000; 549 val &= ~SUNXI_TCON0_DCLK_DIV; 550 val |= __SHIFTIN(best_div, SUNXI_TCON0_DCLK_DIV); 551 TCON_WRITE(sc, SUNXI_TCON0_DCLK_REG, val); 552 553 mode.dot_clock = lcd_dclk_freq; 554 mode.hdisplay = lcd_x; 555 mode.hsync_start = lcd_ht - lcd_hbp; 556 mode.hsync_end = lcd_hspw + mode.hsync_start; 557 mode.htotal = lcd_ht; 558 mode.vdisplay = lcd_y; 559 mode.vsync_start = lcd_vt - lcd_vbp; 560 mode.vsync_end = lcd_vspw + mode.vsync_start; 561 mode.vtotal = lcd_vt; 562 mode.flags = 0; 563 mode.name = NULL; 564 565 sunxi_debe_set_videomode(fdt_endpoint_device(sc->sc_in_rep), &mode); 566 567 /* XXX 568 * magic values here from linux. these are not documented 569 * in the A20 user manual, and other Allwiner LVDS-capable SoC 570 * documentation don't make sense with these values 571 */ 572 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA0); 573 val |= 0x3F310000; 574 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val); 575 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA0); 576 val |= 1 << 22; 577 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val); 578 delay(2); 579 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA1); 580 val |= (0x1f << 26 | 0x1f << 10); 581 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA1, val); 582 delay(2); 583 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA1); 584 val |= (0x1f << 16 | 0x1f << 0); 585 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA1, val); 586 val = TCON_READ(sc, SUNXI_TCON_LVDS_ANA0); 587 val |= 1 << 22; 588 TCON_WRITE(sc, SUNXI_TCON_LVDS_ANA0, val); 589 return 0; 590 } 591 592 static int 593 sunxi_tcon0_enable(struct sunxi_tcon_softc *sc, bool enable) 594 { 595 uint32_t val; 596 int error; 597 598 /* turn on/off backlight and lcd */ 599 error = fdt_endpoint_enable(sc->sc_out_ep, enable); 600 if (error) 601 return error; 602 603 /* and finally disable or enable the tcon */ 604 error = fdt_endpoint_enable(sc->sc_in_ep, enable); 605 if (error) 606 return error; 607 delay(20000); 608 if (enable) { 609 if ((error = clk_enable(sc->sc_clk_ch0)) != 0) { 610 device_printf(sc->sc_dev, 611 ": couldn't enable ch0 clock\n"); 612 return error; 613 } 614 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 615 val |= SUNXI_TCON_GCTL_EN; 616 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 617 val = TCON_READ(sc, SUNXI_TCON0_CTL_REG); 618 val |= SUNXI_TCONx_CTL_EN; 619 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val); 620 val = TCON_READ(sc, SUNXI_TCON0_LVDS_IF_REG); 621 val |= SUNXI_TCON0_LVDS_IF_EN; 622 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val); 623 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0); 624 } else { 625 TCON_WRITE(sc, SUNXI_TCON0_IO_TRI_REG, 0xffffffff); 626 val = TCON_READ(sc, SUNXI_TCON0_LVDS_IF_REG); 627 val &= ~SUNXI_TCON0_LVDS_IF_EN; 628 TCON_WRITE(sc, SUNXI_TCON0_LVDS_IF_REG, val); 629 val = TCON_READ(sc, SUNXI_TCON0_CTL_REG); 630 val &= ~SUNXI_TCONx_CTL_EN; 631 TCON_WRITE(sc, SUNXI_TCON0_CTL_REG, val); 632 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 633 val &= ~SUNXI_TCON_GCTL_EN; 634 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 635 if ((error = clk_disable(sc->sc_clk_ch0)) != 0) { 636 device_printf(sc->sc_dev, 637 ": couldn't disable ch0 clock\n"); 638 return error; 639 } 640 } 641 #ifdef SUNXI_TCON_DEBUG 642 sunxi_tcon_dump_regs(device_unit(sc->sc_dev)); 643 #endif 644 return 0; 645 } 646 647 static int 648 sunxi_tcon1_enable(struct sunxi_tcon_softc *sc, bool enable) 649 { 650 uint32_t val; 651 int error; 652 653 KASSERT((sc->sc_output_type == OUTPUT_HDMI) || 654 (sc->sc_output_type == OUTPUT_VGA)); 655 656 fdt_endpoint_enable(sc->sc_in_ep, enable); 657 delay(20000); 658 if (enable) { 659 if ((error = clk_enable(sc->sc_clk_ch1)) != 0) { 660 device_printf(sc->sc_dev, 661 ": couldn't enable ch1 clock\n"); 662 return error; 663 } 664 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 665 val |= SUNXI_TCON_GCTL_EN; 666 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 667 val = TCON_READ(sc, SUNXI_TCON1_CTL_REG); 668 val |= SUNXI_TCONx_CTL_EN; 669 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 670 if (sc->sc_output_type == OUTPUT_VGA) { 671 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0x0cffffff); 672 } else 673 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0); 674 } else { 675 TCON_WRITE(sc, SUNXI_TCON1_IO_TRI_REG, 0xffffffff); 676 val = TCON_READ(sc, SUNXI_TCON1_CTL_REG); 677 val &= ~SUNXI_TCONx_CTL_EN; 678 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 679 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 680 val &= ~SUNXI_TCON_GCTL_EN; 681 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 682 if ((error = clk_disable(sc->sc_clk_ch1)) != 0) { 683 device_printf(sc->sc_dev, 684 ": couldn't disable ch1 clock\n"); 685 return error; 686 } 687 } 688 689 KASSERT(tcon_mux_inited); 690 val = bus_space_read_4(sc->sc_bst, tcon_mux_bsh, 0); 691 #ifdef SUNXI_TCON_DEBUG 692 printf("sunxi_tcon1_enable(%d) %d val 0x%x", sc->sc_unit, enable, val); 693 #endif 694 val &= ~ SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC; 695 switch(sc->sc_unit) { 696 case 0: 697 val |= __SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_LCDC0_TCON1, 698 SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC); 699 break; 700 case 1: 701 val |= __SHIFTIN(SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC_LCDC1_TCON1, 702 SUNXI_TCON_MUX_CTL_HDMI_OUTPUT_SRC); 703 break; 704 default: 705 panic("tcon: invalid unid %d\n", sc->sc_unit); 706 } 707 #ifdef SUNXI_TCON_DEBUG 708 printf(" -> 0x%x", val); 709 #endif 710 bus_space_write_4(sc->sc_bst, tcon_mux_bsh, 0, val); 711 #ifdef SUNXI_TCON_DEBUG 712 printf(": 0x%" PRIxBSH " 0x%" PRIxBSH " 0x%x 0x%x\n", sc->sc_bsh, 713 tcon_mux_bsh, bus_space_read_4(sc->sc_bst, tcon_mux_bsh, 0), 714 TCON_READ(sc, SUNXI_TCON_MUX_CTL_REG)); 715 #endif 716 return 0; 717 } 718 719 void 720 sunxi_tcon1_set_videomode(device_t dev, const struct videomode *mode) 721 { 722 struct sunxi_tcon_softc *sc = device_private(dev); 723 uint32_t val; 724 int error; 725 726 KASSERT(device_is_a(dev, "sunxitcon")); 727 KASSERT((sc->sc_output_type == OUTPUT_HDMI) || 728 (sc->sc_output_type == OUTPUT_VGA)); 729 730 sunxi_debe_set_videomode(fdt_endpoint_device(sc->sc_in_rep), mode); 731 if (mode) { 732 const u_int interlace_p = !!(mode->flags & VID_INTERLACE); 733 const u_int phsync_p = !!(mode->flags & VID_PHSYNC); 734 const u_int pvsync_p = !!(mode->flags & VID_PVSYNC); 735 const u_int hspw = mode->hsync_end - mode->hsync_start; 736 const u_int hbp = mode->htotal - mode->hsync_start; 737 const u_int vspw = mode->vsync_end - mode->vsync_start; 738 const u_int vbp = mode->vtotal - mode->vsync_start; 739 const u_int vblank_len = 740 ((mode->vtotal << interlace_p) >> 1) - mode->vdisplay - 2; 741 const u_int start_delay = 742 vblank_len >= 32 ? 30 : vblank_len - 2; 743 744 val = TCON_READ(sc, SUNXI_TCON_GCTL_REG); 745 val |= SUNXI_TCON_GCTL_IO_MAP_SEL; 746 TCON_WRITE(sc, SUNXI_TCON_GCTL_REG, val); 747 748 /* enable */ 749 val = SUNXI_TCONx_CTL_EN; 750 if (interlace_p) 751 val |= SUNXI_TCONx_CTL_INTERLACE_EN; 752 val |= __SHIFTIN(start_delay, SUNXI_TCONx_CTL_START_DELAY); 753 #ifdef SUNXI_TCON1_BLUEDATA 754 val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_BLUEDATA, 755 SUNXI_TCONx_CTL_SRC_SEL); 756 #else 757 /* 758 * the DE selector selects the primary DEBE for this tcon: 759 * 0 selects debe0 for tcon0 and debe1 for tcon1 760 */ 761 val |= __SHIFTIN(SUNXI_TCONx_CTL_SRC_SEL_DE0, 762 SUNXI_TCONx_CTL_SRC_SEL); 763 #endif 764 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 765 766 /* Source width/height */ 767 TCON_WRITE(sc, SUNXI_TCON1_BASIC0_REG, 768 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 769 /* Scaler width/height */ 770 TCON_WRITE(sc, SUNXI_TCON1_BASIC1_REG, 771 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 772 /* Output width/height */ 773 TCON_WRITE(sc, SUNXI_TCON1_BASIC2_REG, 774 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 775 /* Horizontal total + back porch */ 776 TCON_WRITE(sc, SUNXI_TCON1_BASIC3_REG, 777 ((mode->htotal - 1) << 16) | (hbp - 1)); 778 /* Vertical total + back porch */ 779 u_int vtotal = mode->vtotal * 2; 780 if (interlace_p) { 781 u_int framerate = 782 DIVIDE(DIVIDE(mode->dot_clock * 1000, mode->htotal), 783 mode->vtotal); 784 u_int clk = mode->htotal * (mode->vtotal * 2 + 1) * 785 framerate; 786 if ((clk / 2) == mode->dot_clock * 1000) 787 vtotal += 1; 788 } 789 TCON_WRITE(sc, SUNXI_TCON1_BASIC4_REG, 790 (vtotal << 16) | (vbp - 1)); 791 792 /* Sync */ 793 TCON_WRITE(sc, SUNXI_TCON1_BASIC5_REG, 794 ((hspw - 1) << 16) | (vspw - 1)); 795 /* Polarity */ 796 val = SUNXI_TCON_IO_POL_IO2_INV; 797 if (phsync_p) 798 val |= SUNXI_TCON_IO_POL_PHSYNC; 799 if (pvsync_p) 800 val |= SUNXI_TCON_IO_POL_PVSYNC; 801 TCON_WRITE(sc, SUNXI_TCON1_IO_POL_REG, val); 802 803 TCON_WRITE(sc, SUNXI_TCON_GINT1_REG, 804 __SHIFTIN(start_delay + 2, SUNXI_TCON_GINT1_TCON1_LINENO)); 805 806 /* Setup LCDx CH1 PLL */ 807 error = clk_set_rate(sc->sc_clk_ch1, mode->dot_clock * 1000); 808 if (error) { 809 device_printf(sc->sc_dev, 810 ": failed to set ch1 clock to %d: %d\n", 811 mode->dot_clock, error); 812 } 813 error = clk_enable(sc->sc_clk_ch1); 814 if (error) { 815 device_printf(sc->sc_dev, 816 ": failed to enable ch1 clock: %d\n", 817 error); 818 } 819 } else { 820 /* disable */ 821 val = TCON_READ(sc, SUNXI_TCON1_CTL_REG); 822 val &= ~SUNXI_TCONx_CTL_EN; 823 TCON_WRITE(sc, SUNXI_TCON1_CTL_REG, val); 824 error = clk_disable(sc->sc_clk_ch1); 825 if (error) { 826 device_printf(sc->sc_dev, 827 ": failed to disable ch1 clock: %d\n", 828 error); 829 } 830 } 831 } 832 833 /* check if this tcon is the console chosen by firmare */ 834 bool 835 sunxi_tcon_is_console(device_t dev, const char *pipeline) 836 { 837 struct sunxi_tcon_softc *sc = device_private(dev); 838 char p[64]; 839 char *e, *n = p; 840 bool is_console = false; 841 842 KASSERT(device_is_a(dev, "sunxitcon")); 843 strncpy(p, pipeline, sizeof(p) - 1); 844 p[sizeof(p) - 1] = '\0'; 845 846 /* 847 * pipeline is like "de_be0-lcd0-hdmi" 848 * of "de_be0-lcd1". 849 * In the first case check output type 850 * In the second check tcon unit number 851 */ 852 n = p; 853 e = strsep(&n, "-"); 854 if (e == NULL || memcmp(e, "de_be", 5) != 0) 855 goto bad; 856 e = strsep(&n, "-"); 857 if (e == NULL) 858 goto bad; 859 if (n == NULL) { 860 /* second case */ 861 if (strcmp(e, "lcd0") == 0) { 862 if (sc->sc_unit == 0) 863 is_console = true; 864 } else if (strcmp(e, "lcd1") == 0) { 865 if (sc->sc_unit == 1) 866 is_console = true; 867 } else 868 goto bad; 869 return is_console; 870 } 871 /* first case */ 872 if (strcmp(n, "hdmi") == 0) { 873 if (sc->sc_output_type == OUTPUT_HDMI) 874 is_console = true; 875 return is_console; 876 } 877 bad: 878 aprint_error("warning: can't parse pipeline %s\n", pipeline); 879 return is_console; 880 } 881 882 #if defined(DDB) || defined(SUNXI_TCON_DEBUG) 883 void 884 sunxi_tcon_dump_regs(int u) 885 { 886 static const struct { 887 const char *name; 888 uint16_t reg; 889 } regs[] = { 890 { "TCON0_BASIC0_REG", SUNXI_TCON0_BASIC0_REG }, 891 { "TCON0_BASIC1_REG", SUNXI_TCON0_BASIC1_REG }, 892 { "TCON0_BASIC2_REG", SUNXI_TCON0_BASIC2_REG }, 893 { "TCON0_BASIC3_REG", SUNXI_TCON0_BASIC3_REG }, 894 { "TCON0_CTL_REG", SUNXI_TCON0_CTL_REG }, 895 { "TCON0_DCLK_REG", SUNXI_TCON0_DCLK_REG }, 896 { "TCON0_IO_POL_REG", SUNXI_TCON0_IO_POL_REG }, 897 { "TCON0_IO_TRI_REG", SUNXI_TCON0_IO_TRI_REG }, 898 { "TCON0_LVDS_IF_REG", SUNXI_TCON0_LVDS_IF_REG }, 899 { "TCON1_BASIC0_REG", SUNXI_TCON1_BASIC0_REG }, 900 { "TCON1_BASIC1_REG", SUNXI_TCON1_BASIC1_REG }, 901 { "TCON1_BASIC2_REG", SUNXI_TCON1_BASIC2_REG }, 902 { "TCON1_BASIC3_REG", SUNXI_TCON1_BASIC3_REG }, 903 { "TCON1_BASIC4_REG", SUNXI_TCON1_BASIC4_REG }, 904 { "TCON1_BASIC5_REG", SUNXI_TCON1_BASIC5_REG }, 905 { "TCON1_CTL_REG", SUNXI_TCON1_CTL_REG }, 906 { "TCON1_IO_POL_REG", SUNXI_TCON1_IO_POL_REG }, 907 { "TCON1_IO_TRI_REG", SUNXI_TCON1_IO_TRI_REG }, 908 { "TCON_GCTL_REG", SUNXI_TCON_GCTL_REG }, 909 { "TCON_GINT0_REG", SUNXI_TCON_GINT0_REG }, 910 { "TCON_GINT1_REG", SUNXI_TCON_GINT1_REG }, 911 { "TCON_MUX_CTL_REG", SUNXI_TCON_MUX_CTL_REG }, 912 }; 913 struct sunxi_tcon_softc *sc; 914 device_t dev; 915 916 dev = device_find_by_driver_unit("sunxitcon", u); 917 if (dev == NULL) 918 return; 919 sc = device_private(dev); 920 921 for (int i = 0; i < __arraycount(regs); i++) { 922 printf("%s: 0x%08x\n", regs[i].name, 923 TCON_READ(sc, regs[i].reg)); 924 } 925 } 926 #endif 927
Indexes created Tue Sep 30 20:09:53 GMT 2025