sunxi_timer.c revision 1.5
1 /* $NetBSD: sunxi_timer.c,v 1.5 2019/03/27 06:56:19 tnn Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: sunxi_timer.c,v 1.5 2019/03/27 06:56:19 tnn Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/timetc.h> 39 40 #include <arm/locore.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #include <arm/fdt/arm_fdtvar.h> 45 46 /* Timer 0 registers */ 47 #define TMR_IRQ_EN_REG 0x00 48 #define TMR_IRQ_EN(n) __BIT(n) 49 #define TMR_IRQ_STAS_REG 0x04 50 #define TMR_IRQ_STAS_PEND(n) __BIT(n) 51 #define TMR0_CTRL_REG 0x10 52 #define TMR0_CTRL_MODE __BIT(7) 53 #define TMR0_CTRL_CLK_PRESCALE __BITS(6,4) 54 #define TMR0_CTRL_CLK_SRC __BITS(3,2) 55 #define TMR0_CTRL_CLK_SRC_OSC24M 1 56 #define TMR0_CTRL_CLK_SRC_PLL6_6 2 57 #define TMR0_CTRL_RELOAD __BIT(1) 58 #define TMR0_CTRL_EN __BIT(0) 59 #define TMR0_INTV_VALUE_REG 0x14 60 #define TMR0_CURNT_VALUE_REG 0x18 61 62 /* Timer 1 is used for delay() */ 63 64 /* Timer 2 registers */ 65 #define TMR2_CTRL_REG 0x30 66 #define TMR2_CTRL_MODE __BIT(7) 67 #define TMR2_CTRL_CLK_SRC __BITS(3,2) 68 #define TMR2_CTRL_CLK_SRC_OSC24M 1 69 #define TMR2_CTRL_RELOAD __BIT(1) 70 #define TMR2_CTRL_EN __BIT(0) 71 #define TMR2_INTV_VALUE_REG 0x34 72 #define TMR2_CURNT_VALUE_REG 0x38 73 74 /* Timer 4 registers */ 75 #define TMR4_CTRL_REG 0x50 76 #define TMR4_CTRL_RELOAD __BIT(1) 77 #define TMR4_CTRL_EN __BIT(0) 78 #define TMR4_INTV_VALUE_REG 0x54 79 #define TMR4_CURNT_VALUE_REG 0x58 80 81 static const char * const compatible[] = { 82 "allwinner,sun4i-a10-timer", 83 NULL 84 }; 85 86 struct sunxi_timer_softc { 87 device_t sc_dev; 88 bus_space_tag_t sc_bst; 89 bus_space_handle_t sc_bsh; 90 int sc_phandle; 91 struct clk *sc_clk; 92 93 struct timecounter sc_tc; 94 struct timecounter sc_tc_losc; 95 }; 96 97 #define TIMER_READ(sc, reg) \ 98 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 99 #define TIMER_WRITE(sc, reg, val) \ 100 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 101 102 static struct sunxi_timer_softc *timer_softc; 103 104 static int 105 sunxi_timer_intr(void *arg) 106 { 107 struct sunxi_timer_softc * const sc = timer_softc; 108 struct clockframe *frame = arg; 109 uint32_t stas; 110 111 stas = TIMER_READ(sc, TMR_IRQ_STAS_REG); 112 if (stas == 0) 113 return 0; 114 TIMER_WRITE(sc, TMR_IRQ_STAS_REG, stas); 115 116 if ((stas & TMR_IRQ_STAS_PEND(0)) != 0) 117 hardclock(frame); 118 119 return 1; 120 } 121 122 static void 123 sunxi_timer_cpu_initclocks(void) 124 { 125 struct sunxi_timer_softc * const sc = timer_softc; 126 char intrstr[128]; 127 void *ih; 128 129 KASSERT(sc != NULL); 130 131 if (!fdtbus_intr_str(sc->sc_phandle, 0, intrstr, sizeof(intrstr))) 132 panic("%s: failed to decode interrupt", __func__); 133 134 ih = fdtbus_intr_establish(sc->sc_phandle, 0, IPL_CLOCK, 135 FDT_INTR_MPSAFE, sunxi_timer_intr, NULL); 136 if (ih == NULL) 137 panic("%s: failed to establish timer interrupt", __func__); 138 139 aprint_normal_dev(sc->sc_dev, "interrupting on %s\n", intrstr); 140 141 /* Enable Timer 0 IRQ */ 142 const uint32_t irq_en = TIMER_READ(sc, TMR_IRQ_EN_REG); 143 TIMER_WRITE(sc, TMR_IRQ_EN_REG, irq_en | TMR_IRQ_EN(0)); 144 } 145 146 static u_int 147 sunxi_timer_get_timecount(struct timecounter *tc) 148 { 149 struct sunxi_timer_softc * const sc = tc->tc_priv; 150 151 /* Timer current value is a 32-bit down counter. */ 152 return ~TIMER_READ(sc, TMR2_CURNT_VALUE_REG); 153 } 154 155 static u_int 156 sunxi_timer_get_timecount_losc(struct timecounter *tc) 157 { 158 struct sunxi_timer_softc * const sc = tc->tc_priv; 159 160 return ~TIMER_READ(sc, TMR4_CURNT_VALUE_REG); 161 } 162 163 static int 164 sunxi_timer_match(device_t parent, cfdata_t cf, void *aux) 165 { 166 struct fdt_attach_args * const faa = aux; 167 168 return of_match_compatible(faa->faa_phandle, compatible); 169 } 170 171 static void 172 sunxi_timer_attach(device_t parent, device_t self, void *aux) 173 { 174 struct sunxi_timer_softc * const sc = device_private(self); 175 struct fdt_attach_args * const faa = aux; 176 struct timecounter *tc = &sc->sc_tc; 177 struct timecounter *tc_losc = &sc->sc_tc_losc; 178 const int phandle = faa->faa_phandle; 179 bus_addr_t addr; 180 bus_size_t size; 181 u_int ticks; 182 183 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 184 aprint_error(": couldn't get registers\n"); 185 return; 186 } 187 188 if ((sc->sc_clk = fdtbus_clock_get_index(phandle, 0)) == NULL) { 189 aprint_error(": couldn't get clock\n"); 190 return; 191 } 192 193 sc->sc_dev = self; 194 sc->sc_phandle = phandle; 195 sc->sc_bst = faa->faa_bst; 196 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 197 aprint_error(": couldn't map registers\n"); 198 return; 199 } 200 201 aprint_naive("\n"); 202 aprint_normal(": Timer\n"); 203 204 const u_int rate = clk_get_rate(sc->sc_clk); 205 206 /* Disable IRQs and all timers */ 207 TIMER_WRITE(sc, TMR_IRQ_EN_REG, 0); 208 TIMER_WRITE(sc, TMR_IRQ_STAS_REG, TIMER_READ(sc, TMR_IRQ_STAS_REG)); 209 /* Enable Timer 0 (hardclock) */ 210 TIMER_WRITE(sc, TMR0_INTV_VALUE_REG, rate / hz); 211 TIMER_WRITE(sc, TMR0_CTRL_REG, 212 __SHIFTIN(TMR0_CTRL_CLK_SRC_OSC24M, TMR0_CTRL_CLK_SRC) | 213 TMR0_CTRL_RELOAD | TMR0_CTRL_EN); 214 /* Enable Timer 2 (timecounter) */ 215 TIMER_WRITE(sc, TMR2_INTV_VALUE_REG, ~0u); 216 TIMER_WRITE(sc, TMR2_CTRL_REG, 217 __SHIFTIN(TMR2_CTRL_CLK_SRC_OSC24M, TMR2_CTRL_CLK_SRC) | 218 TMR2_CTRL_RELOAD | TMR2_CTRL_EN); 219 /* Enable Timer 4 (timecounter for LOSC) */ 220 TIMER_WRITE(sc, TMR4_INTV_VALUE_REG, ~0u); 221 TIMER_WRITE(sc, TMR4_CTRL_REG, TMR4_CTRL_RELOAD | TMR4_CTRL_EN); 222 223 /* Timecounter setup */ 224 tc->tc_get_timecount = sunxi_timer_get_timecount; 225 tc->tc_counter_mask = ~0u, 226 tc->tc_frequency = rate; 227 tc->tc_name = "Timer 2"; 228 tc->tc_quality = 200; 229 tc->tc_priv = sc; 230 tc_init(tc); 231 tc_losc->tc_get_timecount = sunxi_timer_get_timecount_losc; 232 tc_losc->tc_counter_mask = ~0u; 233 tc_losc->tc_frequency = 32768; 234 tc_losc->tc_name = "LOSC"; 235 tc_losc->tc_quality = 150; 236 tc_losc->tc_priv = sc; 237 /* 238 * LOSC is optional to implement in hardware. 239 * Make sure it ticks before registering it. 240 */ 241 ticks = sunxi_timer_get_timecount_losc(tc_losc); 242 delay(100); 243 if (ticks != sunxi_timer_get_timecount_losc(tc_losc)) 244 tc_init(tc_losc); 245 246 /* Use this as the OS timer in UP configurations */ 247 if (!arm_has_mpext_p) { 248 timer_softc = sc; 249 arm_fdt_timer_register(sunxi_timer_cpu_initclocks); 250 } 251 } 252 253 CFATTACH_DECL_NEW(sunxi_timer, sizeof(struct sunxi_timer_softc), 254 sunxi_timer_match, sunxi_timer_attach, NULL, NULL); 255
Indexes created Tue Sep 30 11:09:46 GMT 2025