sunxi_usb3phy.c revision 1.2 
1/* $NetBSD: sunxi_usb3phy.c,v 1.2 2021/01/18 02:35:49 thorpej Exp $ */
2
3/*-
4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30
31__KERNEL_RCSID(0, "$NetBSD: sunxi_usb3phy.c,v 1.2 2021/01/18 02:35:49 thorpej Exp $");
32
33#include <sys/param.h>
34#include <sys/bus.h>
35#include <sys/device.h>
36#include <sys/intr.h>
37#include <sys/systm.h>
38#include <sys/time.h>
39
40#include <dev/fdt/fdtvar.h>
41
42#define	SUNXI_APP			0x00
43#define	 APP_FORCE_VBUS			__BITS(13,12)
44
45#define	SUNXI_PIPE_CLOCK_CONTROL	0x14
46#define	 PCC_PIPE_CLK_OPEN		__BIT(6)
47
48#define	SUNXI_PHY_TUNE_LOW		0x18
49#define	 PTL_MAGIC			0x0047fc87
50
51#define	SUNXI_PHY_TUNE_HIGH		0x1c
52#define	 PTH_TX_DEEMPH_3P5DB		__BITS(24,19)
53#define	 PTH_TX_DEEMPH_6DB		__BITS(18,13)
54#define	 PTH_TX_SWING_FULL		__BITS(12,6)
55#define	 PTH_LOS_BIAS			__BITS(5,3)
56#define	 PTH_TX_BOOST_LVL		__BITS(2,0)
57
58#define	SUNXI_PHY_EXTERNAL_CONTROL	0x20
59#define	 PEC_REF_SSP_EN			__BIT(26)
60#define	 PEC_SSC_EN			__BIT(24)
61#define	 PEC_EXTERN_VBUS		__BITS(2,1)
62
63static int sunxi_usb3phy_match(device_t, cfdata_t, void *);
64static void sunxi_usb3phy_attach(device_t, device_t, void *);
65
66enum sunxi_usb3phy_type {
67	USB3PHY_H6 = 1,
68};
69
70static const struct device_compatible_entry compat_data[] = {
71	{ .compat = "allwinner,sun50i-h6-usb3-phy",	.value = USB3PHY_H6 },
72
73	{ 0 }
74};
75
76struct sunxi_usb3phy {
77	bus_space_tag_t		phy_bst;
78	bus_space_handle_t	phy_bsh;
79	struct fdtbus_regulator *phy_reg;
80};
81
82struct sunxi_usb3phy_softc {
83	device_t		sc_dev;
84	enum sunxi_usb3phy_type	sc_type;
85
86	struct sunxi_usb3phy	sc_phy;
87
88	struct fdtbus_gpio_pin	*sc_gpio_id_det;
89	struct fdtbus_gpio_pin	*sc_gpio_vbus_det;
90};
91
92#define	PHY_READ(phy, reg)				\
93	bus_space_read_4((phy)->phy_bst, (phy)->phy_bsh, (reg))
94#define	PHY_WRITE(phy, reg, val)				\
95	bus_space_write_4((phy)->phy_bst, (phy)->phy_bsh, (reg), (val))
96
97CFATTACH_DECL_NEW(sunxi_usb3phy, sizeof(struct sunxi_usb3phy_softc),
98	sunxi_usb3phy_match, sunxi_usb3phy_attach, NULL, NULL);
99
100static void *
101sunxi_usb3phy_acquire(device_t dev, const void *data, size_t len)
102{
103	struct sunxi_usb3phy_softc * const sc = device_private(dev);
104
105	return &sc->sc_phy;
106}
107
108static void
109sunxi_usb3phy_release(device_t dev, void *priv)
110{
111}
112
113static int
114sunxi_usb3phy_enable(device_t dev, void *priv, bool enable)
115{
116	struct sunxi_usb3phy * const phy = priv;
117	uint32_t val;
118
119	if (enable) {
120		val = PHY_READ(phy, SUNXI_PHY_EXTERNAL_CONTROL);
121		val |= PEC_EXTERN_VBUS;
122		val |= PEC_SSC_EN;
123		val |= PEC_REF_SSP_EN;
124		PHY_WRITE(phy, SUNXI_PHY_EXTERNAL_CONTROL, val);
125
126		val = PHY_READ(phy, SUNXI_PIPE_CLOCK_CONTROL);
127		val |= PCC_PIPE_CLK_OPEN;
128		PHY_WRITE(phy, SUNXI_PIPE_CLOCK_CONTROL, val);
129
130		val = PHY_READ(phy, SUNXI_APP);
131		val |= APP_FORCE_VBUS;
132		PHY_WRITE(phy, SUNXI_APP, val);
133
134		PHY_WRITE(phy, SUNXI_PHY_TUNE_LOW, PTL_MAGIC);
135
136		val = PHY_READ(phy, SUNXI_PHY_TUNE_HIGH);
137		val |= PTH_TX_BOOST_LVL;
138		val |= PTH_LOS_BIAS;
139		val &= ~PTH_TX_SWING_FULL;
140		val |= __SHIFTIN(0x55, PTH_TX_SWING_FULL);
141		val &= ~PTH_TX_DEEMPH_6DB;
142		val |= __SHIFTIN(0x20, PTH_TX_DEEMPH_6DB);
143		val &= ~PTH_TX_DEEMPH_3P5DB;
144		val |= __SHIFTIN(0x15, PTH_TX_DEEMPH_3P5DB);
145		PHY_WRITE(phy, SUNXI_PHY_TUNE_HIGH, val);
146
147		return phy->phy_reg ? fdtbus_regulator_enable(phy->phy_reg) : 0;
148	} else {
149		return phy->phy_reg ? fdtbus_regulator_disable(phy->phy_reg) : 0;
150	}
151}
152
153const struct fdtbus_phy_controller_func sunxi_usb3phy_funcs = {
154	.acquire = sunxi_usb3phy_acquire,
155	.release = sunxi_usb3phy_release,
156	.enable = sunxi_usb3phy_enable,
157};
158
159static int
160sunxi_usb3phy_match(device_t parent, cfdata_t cf, void *aux)
161{
162	struct fdt_attach_args * const faa = aux;
163
164	return of_match_compat_data(faa->faa_phandle, compat_data);
165}
166
167static void
168sunxi_usb3phy_attach(device_t parent, device_t self, void *aux)
169{
170	struct sunxi_usb3phy_softc * const sc = device_private(self);
171	struct sunxi_usb3phy *phy = &sc->sc_phy;
172	struct fdt_attach_args * const faa = aux;
173	const int phandle = faa->faa_phandle;
174	struct fdtbus_reset *rst;
175	struct clk *clk;
176	bus_addr_t addr;
177	bus_size_t size;
178	u_int n;
179
180	sc->sc_dev = self;
181	sc->sc_type = of_search_compatible(phandle, compat_data)->value;
182
183	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
184		aprint_error(": couldn't get phy registers\n");
185		return;
186	}
187
188	phy->phy_bst = faa->faa_bst;
189	if (bus_space_map(phy->phy_bst, addr, size, 0, &phy->phy_bsh) != 0) {
190		aprint_error(": couldn't map phy registers\n");
191		return;
192	}
193
194	/* Get optional regulator */
195	phy->phy_reg = fdtbus_regulator_acquire(phandle, "phy-supply");
196
197	/* Enable clocks */
198	for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)
199		if (clk_enable(clk) != 0) {
200			aprint_error(": couldn't enable clock #%d\n", n);
201			return;
202		}
203	/* De-assert resets */
204	for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++)
205		if (fdtbus_reset_deassert(rst) != 0) {
206			aprint_error(": couldn't de-assert reset #%d\n", n);
207			return;
208		}
209
210	aprint_naive("\n");
211	aprint_normal(": USB3 PHY\n");
212
213	fdtbus_register_phy_controller(self, phandle, &sunxi_usb3phy_funcs);
214}
215