am3_prcm.c revision 1.1.6.1
1 /* $NetBSD: am3_prcm.c,v 1.1.6.1 2020/04/13 08:03:38 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: am3_prcm.c,v 1.1.6.1 2020/04/13 08:03:38 martin Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #define TI_PRCM_PRIVATE 41 #include <arm/ti/ti_prcm.h> 42 43 #define AM3_PRCM_CM_PER 0x0000 44 #define AM3_PRCM_CM_WKUP 0x0400 45 #define AM3_PRCM_CM_DPLL 0x0500 46 #define AM3_PRCM_CM_MPU 0x0600 47 #define AM3_PRCM_CM_DEVICE 0x0700 48 #define AM3_PRCM_CM_RTC 0x0800 49 #define AM3_PRCM_CM_GFX 0x0900 50 #define AM3_PRCM_CM_CEFUSE 0x0a00 51 52 #define AM3_PRCM_CLKCTRL_MODULEMODE __BITS(1,0) 53 #define AM3_PRCM_CLKCTRL_MODULEMODE_ENABLE 0x2 54 55 #define AM3_PRCM_CM_IDLEST_DPLL_DISP (AM3_PRCM_CM_WKUP + 0x48) 56 #define AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_MN_BYPASS __BIT(8) 57 #define AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_DPLL_CLK __BIT(0) 58 #define AM3_PRCM_CM_CLKSEL_DPLL_DISP (AM3_PRCM_CM_WKUP + 0x54) 59 #define AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_MULT __BITS(18,8) 60 #define AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_DIV __BITS(6,0) 61 #define AM3_PRCM_CM_CLKMODE_DPLL_DISP (AM3_PRCM_CM_WKUP + 0x98) 62 #define AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN __BITS(2,0) 63 #define AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_MN_BYPASS 4 64 #define AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_LOCK 7 65 66 #define DPLL_DISP_RATE 297000000 67 68 static int am3_prcm_match(device_t, cfdata_t, void *); 69 static void am3_prcm_attach(device_t, device_t, void *); 70 71 static int 72 am3_prcm_hwmod_enable(struct ti_prcm_softc *sc, struct ti_prcm_clk *tc, int enable) 73 { 74 uint32_t val; 75 76 val = PRCM_READ(sc, tc->u.hwmod.reg); 77 val &= ~AM3_PRCM_CLKCTRL_MODULEMODE; 78 if (enable) 79 val |= __SHIFTIN(AM3_PRCM_CLKCTRL_MODULEMODE_ENABLE, 80 AM3_PRCM_CLKCTRL_MODULEMODE); 81 PRCM_WRITE(sc, tc->u.hwmod.reg, val); 82 83 return 0; 84 } 85 86 static int 87 am3_prcm_hwmod_enable_display(struct ti_prcm_softc *sc, struct ti_prcm_clk *tc, int enable) 88 { 89 uint32_t val; 90 int retry; 91 92 if (enable) { 93 /* Put the DPLL in MN bypass mode */ 94 PRCM_WRITE(sc, AM3_PRCM_CM_CLKMODE_DPLL_DISP, 95 __SHIFTIN(AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_MN_BYPASS, 96 AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN)); 97 for (retry = 10000; retry > 0; retry--) { 98 val = PRCM_READ(sc, AM3_PRCM_CM_IDLEST_DPLL_DISP); 99 if ((val & AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_MN_BYPASS) != 0) 100 break; 101 delay(10); 102 } 103 104 /* Set DPLL frequency to DPLL_DISP_RATE (297 MHz) */ 105 val = __SHIFTIN(DPLL_DISP_RATE / 1000000, AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_MULT); 106 val |= __SHIFTIN(24 - 1, AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_DIV); 107 PRCM_WRITE(sc, AM3_PRCM_CM_CLKSEL_DPLL_DISP, val); 108 109 /* Disable MN bypass mode */ 110 PRCM_WRITE(sc, AM3_PRCM_CM_CLKMODE_DPLL_DISP, 111 __SHIFTIN(AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_LOCK, 112 AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN)); 113 for (retry = 10000; retry > 0; retry--) { 114 val = PRCM_READ(sc, AM3_PRCM_CM_IDLEST_DPLL_DISP); 115 if ((val & AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_DPLL_CLK) != 0) 116 break; 117 delay(10); 118 } 119 } 120 121 return am3_prcm_hwmod_enable(sc, tc, enable); 122 } 123 124 #define AM3_PRCM_HWMOD_PER(_name, _reg, _parent) \ 125 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable) 126 #define AM3_PRCM_HWMOD_PER_DISP(_name, _reg, _parent) \ 127 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable_display) 128 #define AM3_PRCM_HWMOD_WKUP(_name, _reg, _parent) \ 129 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_WKUP + (_reg), (_parent), am3_prcm_hwmod_enable) 130 131 static const char * const compatible[] = { 132 "ti,am3-prcm", 133 NULL 134 }; 135 136 CFATTACH_DECL_NEW(am3_prcm, sizeof(struct ti_prcm_softc), 137 am3_prcm_match, am3_prcm_attach, NULL, NULL); 138 139 static struct ti_prcm_clk am3_prcm_clks[] = { 140 /* XXX until we get a proper clock tree */ 141 TI_PRCM_FIXED("FIXED_32K", 32768), 142 TI_PRCM_FIXED("FIXED_24MHZ", 24000000), 143 TI_PRCM_FIXED("FIXED_48MHZ", 48000000), 144 TI_PRCM_FIXED("FIXED_96MHZ", 96000000), 145 TI_PRCM_FIXED("DISPLAY_CLK", DPLL_DISP_RATE), 146 TI_PRCM_FIXED_FACTOR("PERIPH_CLK", 1, 1, "FIXED_48MHZ"), 147 TI_PRCM_FIXED_FACTOR("MMC_CLK", 1, 1, "FIXED_96MHZ"), 148 149 AM3_PRCM_HWMOD_PER("uart1", 0x6c, "PERIPH_CLK"), 150 AM3_PRCM_HWMOD_PER("uart2", 0x70, "PERIPH_CLK"), 151 AM3_PRCM_HWMOD_PER("uart3", 0x74, "PERIPH_CLK"), 152 AM3_PRCM_HWMOD_PER("uart4", 0x78, "PERIPH_CLK"), 153 AM3_PRCM_HWMOD_PER("uart5", 0x38, "PERIPH_CLK"), 154 155 AM3_PRCM_HWMOD_WKUP("i2c1", 0xb8, "PERIPH_CLK"), 156 AM3_PRCM_HWMOD_PER("i2c2", 0x48, "PERIPH_CLK"), 157 AM3_PRCM_HWMOD_PER("i2c3", 0x44, "PERIPH_CLK"), 158 159 AM3_PRCM_HWMOD_WKUP("gpio1", 0x8, "PERIPH_CLK"), 160 AM3_PRCM_HWMOD_PER("gpio2", 0xac, "PERIPH_CLK"), 161 AM3_PRCM_HWMOD_PER("gpio3", 0xb0, "PERIPH_CLK"), 162 AM3_PRCM_HWMOD_PER("gpio4", 0xb4, "PERIPH_CLK"), 163 164 AM3_PRCM_HWMOD_WKUP("timer1", 0x10, "FIXED_32K"), 165 AM3_PRCM_HWMOD_PER("timer2", 0x80, "FIXED_24MHZ"), 166 AM3_PRCM_HWMOD_PER("timer3", 0x84, "FIXED_24MHZ"), 167 AM3_PRCM_HWMOD_PER("timer4", 0x88, "FIXED_24MHZ"), 168 AM3_PRCM_HWMOD_PER("timer5", 0xec, "FIXED_24MHZ"), 169 AM3_PRCM_HWMOD_PER("timer6", 0xf0, "FIXED_24MHZ"), 170 AM3_PRCM_HWMOD_PER("timer7", 0x7c, "FIXED_24MHZ"), 171 172 AM3_PRCM_HWMOD_WKUP("wd_timer2", 0xd4, "FIXED_32K"), 173 174 AM3_PRCM_HWMOD_PER("mmc1", 0x3c, "MMC_CLK"), 175 AM3_PRCM_HWMOD_PER("mmc2", 0xf4, "MMC_CLK"), 176 AM3_PRCM_HWMOD_PER("mmc3", 0xf8, "MMC_CLK"), 177 178 AM3_PRCM_HWMOD_PER("tpcc", 0xbc, "PERIPH_CLK"), 179 AM3_PRCM_HWMOD_PER("tptc0", 0x24, "PERIPH_CLK"), 180 AM3_PRCM_HWMOD_PER("tptc1", 0xfc, "PERIPH_CLK"), 181 AM3_PRCM_HWMOD_PER("tptc2", 0x100, "PERIPH_CLK"), 182 183 AM3_PRCM_HWMOD_PER("usb_otg_hs", 0x1c, "PERIPH_CLK"), 184 185 AM3_PRCM_HWMOD_PER("rng", 0x90, "PERIPH_CLK"), 186 187 AM3_PRCM_HWMOD_PER_DISP("lcdc", 0x18, "DISPLAY_CLK"), 188 }; 189 190 static int 191 am3_prcm_match(device_t parent, cfdata_t cf, void *aux) 192 { 193 struct fdt_attach_args * const faa = aux; 194 195 return of_match_compatible(faa->faa_phandle, compatible); 196 } 197 198 static void 199 am3_prcm_attach(device_t parent, device_t self, void *aux) 200 { 201 struct ti_prcm_softc * const sc = device_private(self); 202 struct fdt_attach_args * const faa = aux; 203 int clocks; 204 205 sc->sc_dev = self; 206 sc->sc_phandle = faa->faa_phandle; 207 sc->sc_bst = faa->faa_bst; 208 209 sc->sc_clks = am3_prcm_clks; 210 sc->sc_nclks = __arraycount(am3_prcm_clks); 211 212 if (ti_prcm_attach(sc) != 0) 213 return; 214 215 aprint_naive("\n"); 216 aprint_normal(": AM3xxx PRCM\n"); 217 218 clocks = of_find_firstchild_byname(sc->sc_phandle, "clocks"); 219 if (clocks > 0) 220 fdt_add_bus(self, clocks, faa); 221 } 222
Indexes created Wed Oct 29 20:09:47 GMT 2025