am3_prcm.c revision 1.9
1 /* $NetBSD: am3_prcm.c,v 1.9 2019/11/03 22:59:06 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: am3_prcm.c,v 1.9 2019/11/03 22:59:06 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #define TI_PRCM_PRIVATE 41 #include <arm/ti/ti_prcm.h> 42 43 #define AM3_PRCM_CM_PER 0x0000 44 #define AM3_PRCM_CM_WKUP 0x0400 45 #define AM3_PRCM_CM_DPLL 0x0500 46 #define AM3_PRCM_CM_MPU 0x0600 47 #define AM3_PRCM_CM_DEVICE 0x0700 48 #define AM3_PRCM_CM_RTC 0x0800 49 #define AM3_PRCM_CM_GFX 0x0900 50 #define AM3_PRCM_CM_CEFUSE 0x0a00 51 52 #define AM3_PRCM_CLKCTRL_MODULEMODE __BITS(1,0) 53 #define AM3_PRCM_CLKCTRL_MODULEMODE_ENABLE 0x2 54 55 /* WKUP */ 56 #define AM3_PRCM_CM_IDLEST_DPLL_DISP (AM3_PRCM_CM_WKUP + 0x48) 57 #define AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_MN_BYPASS __BIT(8) 58 #define AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_DPLL_CLK __BIT(0) 59 #define AM3_PRCM_CM_CLKSEL_DPLL_DISP (AM3_PRCM_CM_WKUP + 0x54) 60 #define AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_MULT __BITS(18,8) 61 #define AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_DIV __BITS(6,0) 62 #define AM3_PRCM_CM_CLKMODE_DPLL_DISP (AM3_PRCM_CM_WKUP + 0x98) 63 #define AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN __BITS(2,0) 64 #define AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_MN_BYPASS 4 65 #define AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_LOCK 7 66 67 static int am3_prcm_match(device_t, cfdata_t, void *); 68 static void am3_prcm_attach(device_t, device_t, void *); 69 70 static int 71 am3_prcm_hwmod_enable(struct ti_prcm_softc *sc, struct ti_prcm_clk *tc, int enable) 72 { 73 uint32_t val; 74 75 val = PRCM_READ(sc, tc->u.hwmod.reg); 76 val &= ~AM3_PRCM_CLKCTRL_MODULEMODE; 77 if (enable) 78 val |= __SHIFTIN(AM3_PRCM_CLKCTRL_MODULEMODE_ENABLE, 79 AM3_PRCM_CLKCTRL_MODULEMODE); 80 PRCM_WRITE(sc, tc->u.hwmod.reg, val); 81 82 return 0; 83 } 84 85 static int 86 am3_prcm_hwmod_enable_display(struct ti_prcm_softc *sc, struct ti_prcm_clk *tc, int enable) 87 { 88 uint32_t val; 89 int retry; 90 91 if (enable) { 92 /* Put the DPLL in MN bypass mode */ 93 PRCM_WRITE(sc, AM3_PRCM_CM_CLKMODE_DPLL_DISP, 94 __SHIFTIN(AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_MN_BYPASS, 95 AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN)); 96 for (retry = 10000; retry > 0; retry--) { 97 val = PRCM_READ(sc, AM3_PRCM_CM_IDLEST_DPLL_DISP); 98 if ((val & AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_MN_BYPASS) != 0) 99 break; 100 delay(10); 101 } 102 103 /* Set DPLL frequency to 270 MHz */ 104 val = __SHIFTIN(270, AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_MULT); 105 val |= __SHIFTIN(24 - 1, AM3_PRCM_CM_CLKSEL_DPLL_DISP_DPLL_DIV); 106 PRCM_WRITE(sc, AM3_PRCM_CM_CLKSEL_DPLL_DISP, val); 107 108 /* Disable MN bypass mode */ 109 PRCM_WRITE(sc, AM3_PRCM_CM_CLKMODE_DPLL_DISP, 110 __SHIFTIN(AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN_LOCK, 111 AM3_PRCM_CM_CLKMODE_DPLL_DISP_DPLL_EN)); 112 for (retry = 10000; retry > 0; retry--) { 113 val = PRCM_READ(sc, AM3_PRCM_CM_IDLEST_DPLL_DISP); 114 if ((val & AM3_PRCM_CM_IDLEST_DPLL_DISP_ST_DPLL_CLK) != 0) 115 break; 116 delay(10); 117 } 118 } 119 120 return am3_prcm_hwmod_enable(sc, tc, enable); 121 } 122 123 #define AM3_PRCM_HWMOD_PER(_name, _reg, _parent) \ 124 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable) 125 #define AM3_PRCM_HWMOD_PER_DISP(_name, _reg, _parent) \ 126 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_PER + (_reg), (_parent), am3_prcm_hwmod_enable_display) 127 #define AM3_PRCM_HWMOD_WKUP(_name, _reg, _parent) \ 128 TI_PRCM_HWMOD((_name), AM3_PRCM_CM_WKUP + (_reg), (_parent), am3_prcm_hwmod_enable) 129 130 static const char * const compatible[] = { 131 "ti,am3-prcm", 132 NULL 133 }; 134 135 CFATTACH_DECL_NEW(am3_prcm, sizeof(struct ti_prcm_softc), 136 am3_prcm_match, am3_prcm_attach, NULL, NULL); 137 138 static struct ti_prcm_clk am3_prcm_clks[] = { 139 /* XXX until we get a proper clock tree */ 140 TI_PRCM_FIXED("FIXED_32K", 32768), 141 TI_PRCM_FIXED("FIXED_24MHZ", 24000000), 142 TI_PRCM_FIXED("FIXED_48MHZ", 48000000), 143 TI_PRCM_FIXED("FIXED_96MHZ", 96000000), 144 TI_PRCM_FIXED("DISPLAY_CLK", 270000000), 145 TI_PRCM_FIXED_FACTOR("PERIPH_CLK", 1, 1, "FIXED_48MHZ"), 146 TI_PRCM_FIXED_FACTOR("MMC_CLK", 1, 1, "FIXED_96MHZ"), 147 148 AM3_PRCM_HWMOD_PER("uart1", 0x6c, "PERIPH_CLK"), 149 AM3_PRCM_HWMOD_PER("uart2", 0x70, "PERIPH_CLK"), 150 AM3_PRCM_HWMOD_PER("uart3", 0x74, "PERIPH_CLK"), 151 AM3_PRCM_HWMOD_PER("uart4", 0x78, "PERIPH_CLK"), 152 AM3_PRCM_HWMOD_PER("uart5", 0x38, "PERIPH_CLK"), 153 154 AM3_PRCM_HWMOD_WKUP("i2c1", 0xb8, "PERIPH_CLK"), 155 AM3_PRCM_HWMOD_PER("i2c2", 0x48, "PERIPH_CLK"), 156 AM3_PRCM_HWMOD_PER("i2c3", 0x44, "PERIPH_CLK"), 157 158 AM3_PRCM_HWMOD_WKUP("gpio1", 0x8, "PERIPH_CLK"), 159 AM3_PRCM_HWMOD_PER("gpio2", 0xac, "PERIPH_CLK"), 160 AM3_PRCM_HWMOD_PER("gpio3", 0xb0, "PERIPH_CLK"), 161 AM3_PRCM_HWMOD_PER("gpio4", 0xb4, "PERIPH_CLK"), 162 163 AM3_PRCM_HWMOD_WKUP("timer0", 0x10, "FIXED_32K"), 164 AM3_PRCM_HWMOD_PER("timer2", 0x80, "FIXED_24MHZ"), 165 AM3_PRCM_HWMOD_PER("timer3", 0x84, "FIXED_24MHZ"), 166 AM3_PRCM_HWMOD_PER("timer4", 0x88, "FIXED_24MHZ"), 167 AM3_PRCM_HWMOD_PER("timer5", 0xec, "FIXED_24MHZ"), 168 AM3_PRCM_HWMOD_PER("timer6", 0xf0, "FIXED_24MHZ"), 169 AM3_PRCM_HWMOD_PER("timer7", 0x7c, "FIXED_24MHZ"), 170 171 AM3_PRCM_HWMOD_PER("mmc0", 0x3c, "MMC_CLK"), 172 AM3_PRCM_HWMOD_PER("mmc1", 0xf4, "MMC_CLK"), 173 AM3_PRCM_HWMOD_PER("mmc2", 0xf8, "MMC_CLK"), 174 175 AM3_PRCM_HWMOD_PER("tpcc", 0xbc, "PERIPH_CLK"), 176 AM3_PRCM_HWMOD_PER("tptc0", 0x24, "PERIPH_CLK"), 177 AM3_PRCM_HWMOD_PER("tptc1", 0xfc, "PERIPH_CLK"), 178 AM3_PRCM_HWMOD_PER("tptc2", 0x100, "PERIPH_CLK"), 179 180 AM3_PRCM_HWMOD_PER("usb_otg_hs", 0x1c, "PERIPH_CLK"), 181 182 AM3_PRCM_HWMOD_PER("rng", 0x90, "PERIPH_CLK"), 183 184 AM3_PRCM_HWMOD_PER_DISP("lcdc", 0x18, "DISPLAY_CLK"), 185 }; 186 187 static int 188 am3_prcm_match(device_t parent, cfdata_t cf, void *aux) 189 { 190 struct fdt_attach_args * const faa = aux; 191 192 return of_match_compatible(faa->faa_phandle, compatible); 193 } 194 195 static void 196 am3_prcm_attach(device_t parent, device_t self, void *aux) 197 { 198 struct ti_prcm_softc * const sc = device_private(self); 199 struct fdt_attach_args * const faa = aux; 200 int clocks; 201 202 sc->sc_dev = self; 203 sc->sc_phandle = faa->faa_phandle; 204 sc->sc_bst = faa->faa_bst; 205 206 sc->sc_clks = am3_prcm_clks; 207 sc->sc_nclks = __arraycount(am3_prcm_clks); 208 209 if (ti_prcm_attach(sc) != 0) 210 return; 211 212 aprint_naive("\n"); 213 aprint_normal(": AM3xxx PRCM\n"); 214 215 clocks = of_find_firstchild_byname(sc->sc_phandle, "clocks"); 216 if (clocks > 0) 217 fdt_add_bus(self, clocks, faa); 218 } 219
Indexes created Tue Sep 30 11:09:46 GMT 2025