if_cpsw.c revision 1.2.2.1
1 /* $NetBSD: if_cpsw.c,v 1.2.2.1 2019/06/10 22:05:57 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 2012 Damjan Marion <dmarion (at) Freebsd.org> 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 43 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 46 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 48 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 52 * SUCH DAMAGE. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.2.2.1 2019/06/10 22:05:57 christos Exp $"); 57 58 #include <sys/param.h> 59 #include <sys/bus.h> 60 #include <sys/device.h> 61 #include <sys/ioctl.h> 62 #include <sys/intr.h> 63 #include <sys/kmem.h> 64 #include <sys/mutex.h> 65 #include <sys/systm.h> 66 #include <sys/kernel.h> 67 68 #include <net/if.h> 69 #include <net/if_ether.h> 70 #include <net/if_media.h> 71 #include <net/bpf.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #if 0 77 #include <arch/arm/omap/omap2_obiovar.h> 78 #else 79 #include <dev/fdt/fdtvar.h> 80 #endif 81 #include <arch/arm/omap/if_cpswreg.h> 82 #include <arch/arm/omap/sitara_cmreg.h> 83 #include <arch/arm/omap/sitara_cm.h> 84 85 #define CPSW_TXFRAGS 16 86 87 #define CPSW_CPPI_RAM_SIZE (0x2000) 88 #define CPSW_CPPI_RAM_TXDESCS_SIZE (CPSW_CPPI_RAM_SIZE/2) 89 #define CPSW_CPPI_RAM_RXDESCS_SIZE \ 90 (CPSW_CPPI_RAM_SIZE - CPSW_CPPI_RAM_TXDESCS_SIZE) 91 #define CPSW_CPPI_RAM_TXDESCS_BASE (CPSW_CPPI_RAM_OFFSET + 0x0000) 92 #define CPSW_CPPI_RAM_RXDESCS_BASE \ 93 (CPSW_CPPI_RAM_OFFSET + CPSW_CPPI_RAM_TXDESCS_SIZE) 94 95 #define CPSW_NTXDESCS (CPSW_CPPI_RAM_TXDESCS_SIZE/sizeof(struct cpsw_cpdma_bd)) 96 #define CPSW_NRXDESCS (CPSW_CPPI_RAM_RXDESCS_SIZE/sizeof(struct cpsw_cpdma_bd)) 97 98 CTASSERT(powerof2(CPSW_NTXDESCS)); 99 CTASSERT(powerof2(CPSW_NRXDESCS)); 100 101 #define CPSW_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 102 103 #define TXDESC_NEXT(x) cpsw_txdesc_adjust((x), 1) 104 #define TXDESC_PREV(x) cpsw_txdesc_adjust((x), -1) 105 106 #define RXDESC_NEXT(x) cpsw_rxdesc_adjust((x), 1) 107 #define RXDESC_PREV(x) cpsw_rxdesc_adjust((x), -1) 108 109 struct cpsw_ring_data { 110 bus_dmamap_t tx_dm[CPSW_NTXDESCS]; 111 struct mbuf *tx_mb[CPSW_NTXDESCS]; 112 bus_dmamap_t rx_dm[CPSW_NRXDESCS]; 113 struct mbuf *rx_mb[CPSW_NRXDESCS]; 114 }; 115 116 struct cpsw_softc { 117 device_t sc_dev; 118 bus_space_tag_t sc_bst; 119 bus_space_handle_t sc_bsh; 120 bus_size_t sc_bss; 121 bus_dma_tag_t sc_bdt; 122 bus_space_handle_t sc_bsh_txdescs; 123 bus_space_handle_t sc_bsh_rxdescs; 124 bus_addr_t sc_txdescs_pa; 125 bus_addr_t sc_rxdescs_pa; 126 struct ethercom sc_ec; 127 struct mii_data sc_mii; 128 bool sc_phy_has_1000t; 129 bool sc_attached; 130 callout_t sc_tick_ch; 131 void *sc_ih; 132 struct cpsw_ring_data *sc_rdp; 133 volatile u_int sc_txnext; 134 volatile u_int sc_txhead; 135 volatile u_int sc_rxhead; 136 void *sc_rxthih; 137 void *sc_rxih; 138 void *sc_txih; 139 void *sc_miscih; 140 void *sc_txpad; 141 bus_dmamap_t sc_txpad_dm; 142 #define sc_txpad_pa sc_txpad_dm->dm_segs[0].ds_addr 143 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 144 volatile bool sc_txrun; 145 volatile bool sc_rxrun; 146 volatile bool sc_txeoq; 147 volatile bool sc_rxeoq; 148 }; 149 150 static int cpsw_match(device_t, cfdata_t, void *); 151 static void cpsw_attach(device_t, device_t, void *); 152 static int cpsw_detach(device_t, int); 153 154 static void cpsw_start(struct ifnet *); 155 static int cpsw_ioctl(struct ifnet *, u_long, void *); 156 static void cpsw_watchdog(struct ifnet *); 157 static int cpsw_init(struct ifnet *); 158 static void cpsw_stop(struct ifnet *, int); 159 160 static int cpsw_mii_readreg(device_t, int, int, uint16_t *); 161 static int cpsw_mii_writereg(device_t, int, int, uint16_t); 162 static void cpsw_mii_statchg(struct ifnet *); 163 164 static int cpsw_new_rxbuf(struct cpsw_softc * const, const u_int); 165 static void cpsw_tick(void *); 166 167 static int cpsw_rxthintr(void *); 168 static int cpsw_rxintr(void *); 169 static int cpsw_txintr(void *); 170 static int cpsw_miscintr(void *); 171 172 /* ALE support */ 173 #define CPSW_MAX_ALE_ENTRIES 1024 174 175 static int cpsw_ale_update_addresses(struct cpsw_softc *, int purge); 176 177 CFATTACH_DECL_NEW(cpsw, sizeof(struct cpsw_softc), 178 cpsw_match, cpsw_attach, cpsw_detach, NULL); 179 180 #undef KERNHIST 181 #include <sys/kernhist.h> 182 KERNHIST_DEFINE(cpswhist); 183 184 #ifdef KERNHIST 185 #define KERNHIST_CALLED_5(NAME, i, j, k, l) \ 186 do { \ 187 _kernhist_call = atomic_inc_uint_nv(&_kernhist_cnt); \ 188 KERNHIST_LOG(NAME, "called! %x %x %x %x", i, j, k, l); \ 189 } while (/*CONSTCOND*/ 0) 190 #else 191 #define KERNHIST_CALLED_5(NAME, i, j, k, l) 192 #endif 193 194 static inline u_int 195 cpsw_txdesc_adjust(u_int x, int y) 196 { 197 return (((x) + y) & (CPSW_NTXDESCS - 1)); 198 } 199 200 static inline u_int 201 cpsw_rxdesc_adjust(u_int x, int y) 202 { 203 return (((x) + y) & (CPSW_NRXDESCS - 1)); 204 } 205 206 static inline uint32_t 207 cpsw_read_4(struct cpsw_softc * const sc, bus_size_t const offset) 208 { 209 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, offset); 210 } 211 212 static inline void 213 cpsw_write_4(struct cpsw_softc * const sc, bus_size_t const offset, 214 uint32_t const value) 215 { 216 bus_space_write_4(sc->sc_bst, sc->sc_bsh, offset, value); 217 } 218 219 static inline void 220 cpsw_set_txdesc_next(struct cpsw_softc * const sc, const u_int i, uint32_t n) 221 { 222 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i + 0; 223 224 KERNHIST_FUNC(__func__); 225 KERNHIST_CALLED_5(cpswhist, sc, i, n, 0); 226 227 bus_space_write_4(sc->sc_bst, sc->sc_bsh_txdescs, o, n); 228 } 229 230 static inline void 231 cpsw_set_rxdesc_next(struct cpsw_softc * const sc, const u_int i, uint32_t n) 232 { 233 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i + 0; 234 235 KERNHIST_FUNC(__func__); 236 KERNHIST_CALLED_5(cpswhist, sc, i, n, 0); 237 238 bus_space_write_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, n); 239 } 240 241 static inline void 242 cpsw_get_txdesc(struct cpsw_softc * const sc, const u_int i, 243 struct cpsw_cpdma_bd * const bdp) 244 { 245 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 246 uint32_t * const dp = bdp->word; 247 const bus_size_t c = __arraycount(bdp->word); 248 249 KERNHIST_FUNC(__func__); 250 KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0); 251 252 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh_txdescs, o, dp, c); 253 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 254 dp[0], dp[1], dp[2], dp[3]); 255 } 256 257 static inline void 258 cpsw_set_txdesc(struct cpsw_softc * const sc, const u_int i, 259 struct cpsw_cpdma_bd * const bdp) 260 { 261 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 262 uint32_t * const dp = bdp->word; 263 const bus_size_t c = __arraycount(bdp->word); 264 265 KERNHIST_FUNC(__func__); 266 KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0); 267 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 268 dp[0], dp[1], dp[2], dp[3]); 269 270 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh_txdescs, o, dp, c); 271 } 272 273 static inline void 274 cpsw_get_rxdesc(struct cpsw_softc * const sc, const u_int i, 275 struct cpsw_cpdma_bd * const bdp) 276 { 277 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 278 uint32_t * const dp = bdp->word; 279 const bus_size_t c = __arraycount(bdp->word); 280 281 KERNHIST_FUNC(__func__); 282 KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0); 283 284 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, dp, c); 285 286 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 287 dp[0], dp[1], dp[2], dp[3]); 288 } 289 290 static inline void 291 cpsw_set_rxdesc(struct cpsw_softc * const sc, const u_int i, 292 struct cpsw_cpdma_bd * const bdp) 293 { 294 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 295 uint32_t * const dp = bdp->word; 296 const bus_size_t c = __arraycount(bdp->word); 297 298 KERNHIST_FUNC(__func__); 299 KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0); 300 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 301 dp[0], dp[1], dp[2], dp[3]); 302 303 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, dp, c); 304 } 305 306 static inline bus_addr_t 307 cpsw_txdesc_paddr(struct cpsw_softc * const sc, u_int x) 308 { 309 KASSERT(x < CPSW_NTXDESCS); 310 return sc->sc_txdescs_pa + sizeof(struct cpsw_cpdma_bd) * x; 311 } 312 313 static inline bus_addr_t 314 cpsw_rxdesc_paddr(struct cpsw_softc * const sc, u_int x) 315 { 316 KASSERT(x < CPSW_NRXDESCS); 317 return sc->sc_rxdescs_pa + sizeof(struct cpsw_cpdma_bd) * x; 318 } 319 320 321 static int 322 cpsw_match(device_t parent, cfdata_t cf, void *aux) 323 { 324 struct fdt_attach_args * const faa = aux; 325 326 static const char * const compatible[] = { 327 "ti,am335x-cpsw", 328 "ti,cpsw", 329 NULL 330 }; 331 332 return of_match_compatible(faa->faa_phandle, compatible); 333 } 334 335 static bool 336 cpsw_phy_has_1000t(struct cpsw_softc * const sc) 337 { 338 struct ifmedia_entry *ifm; 339 340 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 341 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T) 342 return true; 343 } 344 return false; 345 } 346 347 static int 348 cpsw_detach(device_t self, int flags) 349 { 350 struct cpsw_softc * const sc = device_private(self); 351 struct ifnet *ifp = &sc->sc_ec.ec_if; 352 u_int i; 353 354 /* Succeed now if there's no work to do. */ 355 if (!sc->sc_attached) 356 return 0; 357 358 sc->sc_attached = false; 359 360 /* Stop the interface. Callouts are stopped in it. */ 361 cpsw_stop(ifp, 1); 362 363 /* Destroy our callout. */ 364 callout_destroy(&sc->sc_tick_ch); 365 366 /* Let go of the interrupts */ 367 intr_disestablish(sc->sc_rxthih); 368 intr_disestablish(sc->sc_rxih); 369 intr_disestablish(sc->sc_txih); 370 intr_disestablish(sc->sc_miscih); 371 372 /* Delete all media. */ 373 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 374 375 ether_ifdetach(ifp); 376 if_detach(ifp); 377 378 /* Free the packet padding buffer */ 379 kmem_free(sc->sc_txpad, ETHER_MIN_LEN); 380 bus_dmamap_destroy(sc->sc_bdt, sc->sc_txpad_dm); 381 382 /* Destroy all the descriptors */ 383 for (i = 0; i < CPSW_NTXDESCS; i++) 384 bus_dmamap_destroy(sc->sc_bdt, sc->sc_rdp->tx_dm[i]); 385 for (i = 0; i < CPSW_NRXDESCS; i++) 386 bus_dmamap_destroy(sc->sc_bdt, sc->sc_rdp->rx_dm[i]); 387 kmem_free(sc->sc_rdp, sizeof(*sc->sc_rdp)); 388 389 /* Unmap */ 390 bus_space_unmap(sc->sc_bst, sc->sc_bsh, sc->sc_bss); 391 392 393 return 0; 394 } 395 396 static void 397 cpsw_attach(device_t parent, device_t self, void *aux) 398 { 399 struct fdt_attach_args * const faa = aux; 400 struct cpsw_softc * const sc = device_private(self); 401 prop_dictionary_t dict = device_properties(self); 402 struct ethercom * const ec = &sc->sc_ec; 403 struct ifnet * const ifp = &ec->ec_if; 404 struct mii_data * const mii = &sc->sc_mii; 405 const int phandle = faa->faa_phandle; 406 bus_addr_t addr; 407 bus_size_t size; 408 int error; 409 u_int i; 410 411 KERNHIST_INIT(cpswhist, 4096); 412 413 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 414 aprint_error(": couldn't get registers\n"); 415 return; 416 } 417 418 sc->sc_dev = self; 419 420 aprint_normal(": TI Layer 2 3-Port Switch\n"); 421 aprint_naive("\n"); 422 423 callout_init(&sc->sc_tick_ch, 0); 424 callout_setfunc(&sc->sc_tick_ch, cpsw_tick, sc); 425 426 prop_data_t eaprop = prop_dictionary_get(dict, "mac-address"); 427 if (eaprop == NULL) { 428 #if 0 429 /* grab mac_id0 from AM335x control module */ 430 uint32_t reg_lo, reg_hi; 431 432 if (sitara_cm_reg_read_4(OMAP2SCM_MAC_ID0_LO, ®_lo) == 0 && 433 sitara_cm_reg_read_4(OMAP2SCM_MAC_ID0_HI, ®_hi) == 0) { 434 sc->sc_enaddr[0] = (reg_hi >> 0) & 0xff; 435 sc->sc_enaddr[1] = (reg_hi >> 8) & 0xff; 436 sc->sc_enaddr[2] = (reg_hi >> 16) & 0xff; 437 sc->sc_enaddr[3] = (reg_hi >> 24) & 0xff; 438 sc->sc_enaddr[4] = (reg_lo >> 0) & 0xff; 439 sc->sc_enaddr[5] = (reg_lo >> 8) & 0xff; 440 } else 441 #endif 442 { 443 aprint_error_dev(sc->sc_dev, 444 "using fake station address\n"); 445 /* 'N' happens to have the Local bit set */ 446 #if 0 447 sc->sc_enaddr[0] = 'N'; 448 sc->sc_enaddr[1] = 'e'; 449 sc->sc_enaddr[2] = 't'; 450 sc->sc_enaddr[3] = 'B'; 451 sc->sc_enaddr[4] = 'S'; 452 sc->sc_enaddr[5] = 'D'; 453 #else 454 /* XXX Glor */ 455 sc->sc_enaddr[0] = 0xd4; 456 sc->sc_enaddr[1] = 0x94; 457 sc->sc_enaddr[2] = 0xa1; 458 sc->sc_enaddr[3] = 0x97; 459 sc->sc_enaddr[4] = 0x03; 460 sc->sc_enaddr[5] = 0x94; 461 #endif 462 } 463 } else { 464 KASSERT(prop_object_type(eaprop) == PROP_TYPE_DATA); 465 KASSERT(prop_data_size(eaprop) == ETHER_ADDR_LEN); 466 memcpy(sc->sc_enaddr, prop_data_data_nocopy(eaprop), 467 ETHER_ADDR_LEN); 468 } 469 470 #if 0 471 sc->sc_rxthih = intr_establish(oa->obio_intrbase + CPSW_INTROFF_RXTH, 472 IPL_VM, IST_LEVEL, cpsw_rxthintr, sc); 473 sc->sc_rxih = intr_establish(oa->obio_intrbase + CPSW_INTROFF_RX, 474 IPL_VM, IST_LEVEL, cpsw_rxintr, sc); 475 sc->sc_txih = intr_establish(oa->obio_intrbase + CPSW_INTROFF_TX, 476 IPL_VM, IST_LEVEL, cpsw_txintr, sc); 477 sc->sc_miscih = intr_establish(oa->obio_intrbase + CPSW_INTROFF_MISC, 478 IPL_VM, IST_LEVEL, cpsw_miscintr, sc); 479 #else 480 #define FDT_INTR_FLAGS 0 481 sc->sc_rxthih = fdtbus_intr_establish(phandle, CPSW_INTROFF_RXTH, IPL_VM, FDT_INTR_FLAGS, cpsw_rxthintr, sc); 482 sc->sc_rxih = fdtbus_intr_establish(phandle, CPSW_INTROFF_RX, IPL_VM, FDT_INTR_FLAGS, cpsw_rxintr, sc); 483 sc->sc_txih = fdtbus_intr_establish(phandle, CPSW_INTROFF_TX, IPL_VM, FDT_INTR_FLAGS, cpsw_txintr, sc); 484 sc->sc_miscih = fdtbus_intr_establish(phandle, CPSW_INTROFF_MISC, IPL_VM, FDT_INTR_FLAGS, cpsw_miscintr, sc); 485 #endif 486 487 sc->sc_bst = faa->faa_bst; 488 sc->sc_bss = size; 489 sc->sc_bdt = faa->faa_dmat; 490 491 error = bus_space_map(sc->sc_bst, addr, size, 0, 492 &sc->sc_bsh); 493 if (error) { 494 aprint_error_dev(sc->sc_dev, 495 "can't map registers: %d\n", error); 496 return; 497 } 498 499 sc->sc_txdescs_pa = addr + CPSW_CPPI_RAM_TXDESCS_BASE; 500 error = bus_space_subregion(sc->sc_bst, sc->sc_bsh, 501 CPSW_CPPI_RAM_TXDESCS_BASE, CPSW_CPPI_RAM_TXDESCS_SIZE, 502 &sc->sc_bsh_txdescs); 503 if (error) { 504 aprint_error_dev(sc->sc_dev, 505 "can't subregion tx ring SRAM: %d\n", error); 506 return; 507 } 508 aprint_debug_dev(sc->sc_dev, "txdescs at %p\n", 509 (void *)sc->sc_bsh_txdescs); 510 511 sc->sc_rxdescs_pa = addr + CPSW_CPPI_RAM_RXDESCS_BASE; 512 error = bus_space_subregion(sc->sc_bst, sc->sc_bsh, 513 CPSW_CPPI_RAM_RXDESCS_BASE, CPSW_CPPI_RAM_RXDESCS_SIZE, 514 &sc->sc_bsh_rxdescs); 515 if (error) { 516 aprint_error_dev(sc->sc_dev, 517 "can't subregion rx ring SRAM: %d\n", error); 518 return; 519 } 520 aprint_debug_dev(sc->sc_dev, "rxdescs at %p\n", 521 (void *)sc->sc_bsh_rxdescs); 522 523 sc->sc_rdp = kmem_alloc(sizeof(*sc->sc_rdp), KM_SLEEP); 524 525 for (i = 0; i < CPSW_NTXDESCS; i++) { 526 if ((error = bus_dmamap_create(sc->sc_bdt, MCLBYTES, 527 CPSW_TXFRAGS, MCLBYTES, 0, 0, 528 &sc->sc_rdp->tx_dm[i])) != 0) { 529 aprint_error_dev(sc->sc_dev, 530 "unable to create tx DMA map: %d\n", error); 531 } 532 sc->sc_rdp->tx_mb[i] = NULL; 533 } 534 535 for (i = 0; i < CPSW_NRXDESCS; i++) { 536 if ((error = bus_dmamap_create(sc->sc_bdt, MCLBYTES, 1, 537 MCLBYTES, 0, 0, &sc->sc_rdp->rx_dm[i])) != 0) { 538 aprint_error_dev(sc->sc_dev, 539 "unable to create rx DMA map: %d\n", error); 540 } 541 sc->sc_rdp->rx_mb[i] = NULL; 542 } 543 544 sc->sc_txpad = kmem_zalloc(ETHER_MIN_LEN, KM_SLEEP); 545 bus_dmamap_create(sc->sc_bdt, ETHER_MIN_LEN, 1, ETHER_MIN_LEN, 0, 546 BUS_DMA_WAITOK, &sc->sc_txpad_dm); 547 bus_dmamap_load(sc->sc_bdt, sc->sc_txpad_dm, sc->sc_txpad, 548 ETHER_MIN_LEN, NULL, BUS_DMA_WAITOK | BUS_DMA_WRITE); 549 bus_dmamap_sync(sc->sc_bdt, sc->sc_txpad_dm, 0, ETHER_MIN_LEN, 550 BUS_DMASYNC_PREWRITE); 551 552 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 553 ether_sprintf(sc->sc_enaddr)); 554 555 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 556 ifp->if_softc = sc; 557 ifp->if_capabilities = 0; 558 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 559 ifp->if_start = cpsw_start; 560 ifp->if_ioctl = cpsw_ioctl; 561 ifp->if_init = cpsw_init; 562 ifp->if_stop = cpsw_stop; 563 ifp->if_watchdog = cpsw_watchdog; 564 IFQ_SET_READY(&ifp->if_snd); 565 566 cpsw_stop(ifp, 0); 567 568 mii->mii_ifp = ifp; 569 mii->mii_readreg = cpsw_mii_readreg; 570 mii->mii_writereg = cpsw_mii_writereg; 571 mii->mii_statchg = cpsw_mii_statchg; 572 573 sc->sc_ec.ec_mii = mii; 574 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 575 576 /* Initialize MDIO */ 577 cpsw_write_4(sc, MDIOCONTROL, 578 MDIOCTL_ENABLE | MDIOCTL_FAULTENB | MDIOCTL_CLKDIV(0xff)); 579 /* Clear ALE */ 580 cpsw_write_4(sc, CPSW_ALE_CONTROL, ALECTL_CLEAR_TABLE); 581 582 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 0, 0); 583 if (LIST_FIRST(&mii->mii_phys) == NULL) { 584 aprint_error_dev(self, "no PHY found!\n"); 585 sc->sc_phy_has_1000t = false; 586 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 587 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 588 } else { 589 sc->sc_phy_has_1000t = cpsw_phy_has_1000t(sc); 590 if (sc->sc_phy_has_1000t) { 591 #if 0 592 aprint_normal_dev(sc->sc_dev, "1000baseT PHY found. " 593 "Setting RGMII Mode\n"); 594 /* 595 * Select the Interface RGMII Mode in the Control 596 * Module 597 */ 598 sitara_cm_reg_write_4(CPSW_GMII_SEL, 599 GMIISEL_GMII2_SEL(RGMII_MODE) | 600 GMIISEL_GMII1_SEL(RGMII_MODE)); 601 #endif 602 } 603 604 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 605 } 606 607 if_attach(ifp); 608 if_deferred_start_init(ifp, NULL); 609 ether_ifattach(ifp, sc->sc_enaddr); 610 611 /* The attach is successful. */ 612 sc->sc_attached = true; 613 614 return; 615 } 616 617 static void 618 cpsw_start(struct ifnet *ifp) 619 { 620 struct cpsw_softc * const sc = ifp->if_softc; 621 struct cpsw_ring_data * const rdp = sc->sc_rdp; 622 struct cpsw_cpdma_bd bd; 623 uint32_t * const dw = bd.word; 624 struct mbuf *m; 625 bus_dmamap_t dm; 626 u_int eopi __diagused = ~0; 627 u_int seg; 628 u_int txfree; 629 int txstart = -1; 630 int error; 631 bool pad; 632 u_int mlen; 633 634 KERNHIST_FUNC(__func__); 635 KERNHIST_CALLED_5(cpswhist, sc, 0, 0, 0); 636 637 if (__predict_false((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != 638 IFF_RUNNING)) { 639 return; 640 } 641 642 if (sc->sc_txnext >= sc->sc_txhead) 643 txfree = CPSW_NTXDESCS - 1 + sc->sc_txhead - sc->sc_txnext; 644 else 645 txfree = sc->sc_txhead - sc->sc_txnext - 1; 646 647 KERNHIST_LOG(cpswhist, "start txf %x txh %x txn %x txr %x\n", 648 txfree, sc->sc_txhead, sc->sc_txnext, sc->sc_txrun); 649 650 while (txfree > 0) { 651 IFQ_POLL(&ifp->if_snd, m); 652 if (m == NULL) 653 break; 654 655 dm = rdp->tx_dm[sc->sc_txnext]; 656 657 error = bus_dmamap_load_mbuf(sc->sc_bdt, dm, m, BUS_DMA_NOWAIT); 658 if (error == EFBIG) { 659 device_printf(sc->sc_dev, "won't fit\n"); 660 IFQ_DEQUEUE(&ifp->if_snd, m); 661 m_freem(m); 662 ifp->if_oerrors++; 663 continue; 664 } else if (error != 0) { 665 device_printf(sc->sc_dev, "error\n"); 666 break; 667 } 668 669 if (dm->dm_nsegs + 1 >= txfree) { 670 ifp->if_flags |= IFF_OACTIVE; 671 bus_dmamap_unload(sc->sc_bdt, dm); 672 break; 673 } 674 675 mlen = m_length(m); 676 pad = mlen < CPSW_PAD_LEN; 677 678 KASSERT(rdp->tx_mb[sc->sc_txnext] == NULL); 679 rdp->tx_mb[sc->sc_txnext] = m; 680 IFQ_DEQUEUE(&ifp->if_snd, m); 681 682 bus_dmamap_sync(sc->sc_bdt, dm, 0, dm->dm_mapsize, 683 BUS_DMASYNC_PREWRITE); 684 685 if (txstart == -1) 686 txstart = sc->sc_txnext; 687 eopi = sc->sc_txnext; 688 for (seg = 0; seg < dm->dm_nsegs; seg++) { 689 dw[0] = cpsw_txdesc_paddr(sc, 690 TXDESC_NEXT(sc->sc_txnext)); 691 dw[1] = dm->dm_segs[seg].ds_addr; 692 dw[2] = dm->dm_segs[seg].ds_len; 693 dw[3] = 0; 694 695 if (seg == 0) 696 dw[3] |= CPDMA_BD_SOP | CPDMA_BD_OWNER | 697 MAX(mlen, CPSW_PAD_LEN); 698 699 if ((seg == dm->dm_nsegs - 1) && !pad) 700 dw[3] |= CPDMA_BD_EOP; 701 702 cpsw_set_txdesc(sc, sc->sc_txnext, &bd); 703 txfree--; 704 eopi = sc->sc_txnext; 705 sc->sc_txnext = TXDESC_NEXT(sc->sc_txnext); 706 } 707 if (pad) { 708 dw[0] = cpsw_txdesc_paddr(sc, 709 TXDESC_NEXT(sc->sc_txnext)); 710 dw[1] = sc->sc_txpad_pa; 711 dw[2] = CPSW_PAD_LEN - mlen; 712 dw[3] = CPDMA_BD_EOP; 713 714 cpsw_set_txdesc(sc, sc->sc_txnext, &bd); 715 txfree--; 716 eopi = sc->sc_txnext; 717 sc->sc_txnext = TXDESC_NEXT(sc->sc_txnext); 718 } 719 720 bpf_mtap(ifp, m, BPF_D_OUT); 721 } 722 723 if (txstart >= 0) { 724 ifp->if_timer = 5; 725 /* terminate the new chain */ 726 KASSERT(eopi == TXDESC_PREV(sc->sc_txnext)); 727 cpsw_set_txdesc_next(sc, TXDESC_PREV(sc->sc_txnext), 0); 728 KERNHIST_LOG(cpswhist, "CP %x HDP %x s %x e %x\n", 729 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)), 730 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)), txstart, eopi); 731 /* link the new chain on */ 732 cpsw_set_txdesc_next(sc, TXDESC_PREV(txstart), 733 cpsw_txdesc_paddr(sc, txstart)); 734 if (sc->sc_txeoq) { 735 /* kick the dma engine */ 736 sc->sc_txeoq = false; 737 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 738 cpsw_txdesc_paddr(sc, txstart)); 739 } 740 } 741 KERNHIST_LOG(cpswhist, "end txf %x txh %x txn %x txr %x\n", 742 txfree, sc->sc_txhead, sc->sc_txnext, sc->sc_txrun); 743 } 744 745 static int 746 cpsw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 747 { 748 const int s = splnet(); 749 int error = 0; 750 751 switch (cmd) { 752 default: 753 error = ether_ioctl(ifp, cmd, data); 754 if (error == ENETRESET) { 755 error = 0; 756 } 757 break; 758 } 759 760 splx(s); 761 762 return error; 763 } 764 765 static void 766 cpsw_watchdog(struct ifnet *ifp) 767 { 768 struct cpsw_softc *sc = ifp->if_softc; 769 770 device_printf(sc->sc_dev, "device timeout\n"); 771 772 ifp->if_oerrors++; 773 cpsw_init(ifp); 774 cpsw_start(ifp); 775 } 776 777 static int 778 cpsw_mii_wait(struct cpsw_softc * const sc, int reg) 779 { 780 u_int tries; 781 782 for (tries = 0; tries < 1000; tries++) { 783 if ((cpsw_read_4(sc, reg) & __BIT(31)) == 0) 784 return 0; 785 delay(1); 786 } 787 return ETIMEDOUT; 788 } 789 790 static int 791 cpsw_mii_readreg(device_t dev, int phy, int reg, uint16_t *val) 792 { 793 struct cpsw_softc * const sc = device_private(dev); 794 uint32_t v; 795 796 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 797 return -1; 798 799 cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | 800 ((reg & 0x1F) << 21) | ((phy & 0x1F) << 16)); 801 802 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 803 return -1; 804 805 v = cpsw_read_4(sc, MDIOUSERACCESS0); 806 if (v & __BIT(29)) { 807 *val = v & 0xffff; 808 return 0; 809 } 810 811 return -1; 812 } 813 814 static int 815 cpsw_mii_writereg(device_t dev, int phy, int reg, uint16_t val) 816 { 817 struct cpsw_softc * const sc = device_private(dev); 818 uint32_t v; 819 820 KASSERT((val & 0xffff0000UL) == 0); 821 822 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 823 goto out; 824 825 cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | (1 << 30) | 826 ((reg & 0x1F) << 21) | ((phy & 0x1F) << 16) | val); 827 828 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 829 goto out; 830 831 v = cpsw_read_4(sc, MDIOUSERACCESS0); 832 if ((v & __BIT(29)) == 0) { 833 out: 834 device_printf(sc->sc_dev, "%s error\n", __func__); 835 return -1; 836 } 837 838 return 0; 839 } 840 841 static void 842 cpsw_mii_statchg(struct ifnet *ifp) 843 { 844 return; 845 } 846 847 static int 848 cpsw_new_rxbuf(struct cpsw_softc * const sc, const u_int i) 849 { 850 struct cpsw_ring_data * const rdp = sc->sc_rdp; 851 const u_int h = RXDESC_PREV(i); 852 struct cpsw_cpdma_bd bd; 853 uint32_t * const dw = bd.word; 854 struct mbuf *m; 855 int error = ENOBUFS; 856 857 MGETHDR(m, M_DONTWAIT, MT_DATA); 858 if (m == NULL) { 859 goto reuse; 860 } 861 862 MCLGET(m, M_DONTWAIT); 863 if ((m->m_flags & M_EXT) == 0) { 864 m_freem(m); 865 goto reuse; 866 } 867 868 /* We have a new buffer, prepare it for the ring. */ 869 870 if (rdp->rx_mb[i] != NULL) 871 bus_dmamap_unload(sc->sc_bdt, rdp->rx_dm[i]); 872 873 m->m_len = m->m_pkthdr.len = MCLBYTES; 874 875 rdp->rx_mb[i] = m; 876 877 error = bus_dmamap_load_mbuf(sc->sc_bdt, rdp->rx_dm[i], rdp->rx_mb[i], 878 BUS_DMA_READ | BUS_DMA_NOWAIT); 879 if (error) { 880 device_printf(sc->sc_dev, "can't load rx DMA map %d: %d\n", 881 i, error); 882 } 883 884 bus_dmamap_sync(sc->sc_bdt, rdp->rx_dm[i], 885 0, rdp->rx_dm[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 886 887 error = 0; 888 889 reuse: 890 /* (re-)setup the descriptor */ 891 dw[0] = 0; 892 dw[1] = rdp->rx_dm[i]->dm_segs[0].ds_addr; 893 dw[2] = MIN(0x7ff, rdp->rx_dm[i]->dm_segs[0].ds_len); 894 dw[3] = CPDMA_BD_OWNER; 895 896 cpsw_set_rxdesc(sc, i, &bd); 897 /* and link onto ring */ 898 cpsw_set_rxdesc_next(sc, h, cpsw_rxdesc_paddr(sc, i)); 899 900 return error; 901 } 902 903 static int 904 cpsw_init(struct ifnet *ifp) 905 { 906 struct cpsw_softc * const sc = ifp->if_softc; 907 struct mii_data * const mii = &sc->sc_mii; 908 int i; 909 910 cpsw_stop(ifp, 0); 911 912 sc->sc_txnext = 0; 913 sc->sc_txhead = 0; 914 915 /* Reset wrapper */ 916 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 917 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 918 ; 919 920 /* Reset SS */ 921 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 922 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 923 ; 924 925 /* Clear table and enable ALE */ 926 cpsw_write_4(sc, CPSW_ALE_CONTROL, 927 ALECTL_ENABLE_ALE | ALECTL_CLEAR_TABLE); 928 929 /* Reset and init Sliver port 1 and 2 */ 930 for (i = 0; i < CPSW_ETH_PORTS; i++) { 931 uint32_t macctl; 932 933 /* Reset */ 934 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 935 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 936 ; 937 /* Set Slave Mapping */ 938 cpsw_write_4(sc, CPSW_SL_RX_PRI_MAP(i), 0x76543210); 939 cpsw_write_4(sc, CPSW_PORT_P_TX_PRI_MAP(i+1), 0x33221100); 940 cpsw_write_4(sc, CPSW_SL_RX_MAXLEN(i), 0x5f2); 941 /* Set MAC Address */ 942 cpsw_write_4(sc, CPSW_PORT_P_SA_HI(i+1), 943 sc->sc_enaddr[0] | (sc->sc_enaddr[1] << 8) | 944 (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[3] << 24)); 945 cpsw_write_4(sc, CPSW_PORT_P_SA_LO(i+1), 946 sc->sc_enaddr[4] | (sc->sc_enaddr[5] << 8)); 947 948 /* Set MACCONTROL for ports 0,1 */ 949 macctl = SLMACCTL_FULLDUPLEX | SLMACCTL_GMII_EN | 950 SLMACCTL_IFCTL_A; 951 if (sc->sc_phy_has_1000t) 952 macctl |= SLMACCTL_GIG; 953 cpsw_write_4(sc, CPSW_SL_MACCONTROL(i), macctl); 954 955 /* Set ALE port to forwarding(3) */ 956 cpsw_write_4(sc, CPSW_ALE_PORTCTL(i+1), 3); 957 } 958 959 /* Set Host Port Mapping */ 960 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210); 961 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0); 962 963 /* Set ALE port to forwarding(3) */ 964 cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 3); 965 966 /* Initialize addrs */ 967 cpsw_ale_update_addresses(sc, 1); 968 969 cpsw_write_4(sc, CPSW_SS_PTYPE, 0); 970 cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7); 971 972 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 973 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 974 ; 975 976 for (i = 0; i < 8; i++) { 977 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0); 978 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0); 979 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0); 980 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0); 981 } 982 983 bus_space_set_region_4(sc->sc_bst, sc->sc_bsh_txdescs, 0, 0, 984 CPSW_CPPI_RAM_TXDESCS_SIZE/4); 985 986 sc->sc_txhead = 0; 987 sc->sc_txnext = 0; 988 989 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0); 990 991 bus_space_set_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, 0, 0, 992 CPSW_CPPI_RAM_RXDESCS_SIZE/4); 993 /* Initialize RX Buffer Descriptors */ 994 cpsw_set_rxdesc_next(sc, RXDESC_PREV(0), 0); 995 for (i = 0; i < CPSW_NRXDESCS; i++) { 996 cpsw_new_rxbuf(sc, i); 997 } 998 sc->sc_rxhead = 0; 999 1000 /* turn off flow control */ 1001 cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0); 1002 1003 /* align layer 3 header to 32-bit */ 1004 cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, ETHER_ALIGN); 1005 1006 /* Clear all interrupt Masks */ 1007 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF); 1008 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF); 1009 1010 /* Enable TX & RX DMA */ 1011 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1); 1012 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1); 1013 1014 /* Enable TX and RX interrupt receive for core 0 */ 1015 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 1); 1016 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 1); 1017 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F); 1018 1019 /* Enable host Error Interrupt */ 1020 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 2); 1021 1022 /* Enable interrupts for TX and RX Channel 0 */ 1023 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1); 1024 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 1); 1025 1026 /* Ack stalled irqs */ 1027 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH); 1028 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX); 1029 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX); 1030 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC); 1031 1032 /* Initialize MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */ 1033 /* TODO Calculate MDCLK=CLK/(CLKDIV+1) */ 1034 cpsw_write_4(sc, MDIOCONTROL, 1035 MDIOCTL_ENABLE | MDIOCTL_FAULTENB | MDIOCTL_CLKDIV(0xff)); 1036 1037 mii_mediachg(mii); 1038 1039 /* Write channel 0 RX HDP */ 1040 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(0), cpsw_rxdesc_paddr(sc, 0)); 1041 sc->sc_rxrun = true; 1042 sc->sc_rxeoq = false; 1043 1044 sc->sc_txrun = true; 1045 sc->sc_txeoq = true; 1046 callout_schedule(&sc->sc_tick_ch, hz); 1047 ifp->if_flags |= IFF_RUNNING; 1048 ifp->if_flags &= ~IFF_OACTIVE; 1049 1050 return 0; 1051 } 1052 1053 static void 1054 cpsw_stop(struct ifnet *ifp, int disable) 1055 { 1056 struct cpsw_softc * const sc = ifp->if_softc; 1057 struct cpsw_ring_data * const rdp = sc->sc_rdp; 1058 u_int i; 1059 1060 aprint_debug_dev(sc->sc_dev, "%s: ifp %p disable %d\n", __func__, 1061 ifp, disable); 1062 1063 if ((ifp->if_flags & IFF_RUNNING) == 0) 1064 return; 1065 1066 callout_stop(&sc->sc_tick_ch); 1067 mii_down(&sc->sc_mii); 1068 1069 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 1); 1070 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 1); 1071 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0x0); 1072 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0x0); 1073 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x0); 1074 1075 cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0); 1076 cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0); 1077 i = 0; 1078 while ((sc->sc_txrun || sc->sc_rxrun) && i < 10000) { 1079 delay(10); 1080 if ((sc->sc_txrun == true) && cpsw_txintr(sc) == 0) 1081 sc->sc_txrun = false; 1082 if ((sc->sc_rxrun == true) && cpsw_rxintr(sc) == 0) 1083 sc->sc_rxrun = false; 1084 i++; 1085 } 1086 //printf("%s toredown complete in %u\n", __func__, i); 1087 1088 /* Reset wrapper */ 1089 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 1090 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 1091 ; 1092 1093 /* Reset SS */ 1094 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 1095 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 1096 ; 1097 1098 for (i = 0; i < CPSW_ETH_PORTS; i++) { 1099 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 1100 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 1101 ; 1102 } 1103 1104 /* Reset CPDMA */ 1105 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 1106 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 1107 ; 1108 1109 /* Release any queued transmit buffers. */ 1110 for (i = 0; i < CPSW_NTXDESCS; i++) { 1111 bus_dmamap_unload(sc->sc_bdt, rdp->tx_dm[i]); 1112 m_freem(rdp->tx_mb[i]); 1113 rdp->tx_mb[i] = NULL; 1114 } 1115 1116 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1117 ifp->if_timer = 0; 1118 1119 if (!disable) 1120 return; 1121 1122 for (i = 0; i < CPSW_NRXDESCS; i++) { 1123 bus_dmamap_unload(sc->sc_bdt, rdp->rx_dm[i]); 1124 m_freem(rdp->rx_mb[i]); 1125 rdp->rx_mb[i] = NULL; 1126 } 1127 } 1128 1129 static void 1130 cpsw_tick(void *arg) 1131 { 1132 struct cpsw_softc * const sc = arg; 1133 struct mii_data * const mii = &sc->sc_mii; 1134 const int s = splnet(); 1135 1136 mii_tick(mii); 1137 1138 splx(s); 1139 1140 callout_schedule(&sc->sc_tick_ch, hz); 1141 } 1142 1143 static int 1144 cpsw_rxthintr(void *arg) 1145 { 1146 struct cpsw_softc * const sc = arg; 1147 1148 /* this won't deassert the interrupt though */ 1149 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH); 1150 1151 return 1; 1152 } 1153 1154 static int 1155 cpsw_rxintr(void *arg) 1156 { 1157 struct cpsw_softc * const sc = arg; 1158 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1159 struct cpsw_ring_data * const rdp = sc->sc_rdp; 1160 struct cpsw_cpdma_bd bd; 1161 const uint32_t * const dw = bd.word; 1162 bus_dmamap_t dm; 1163 struct mbuf *m; 1164 u_int i; 1165 u_int len, off; 1166 1167 KERNHIST_FUNC(__func__); 1168 KERNHIST_CALLED_5(cpswhist, sc, 0, 0, 0); 1169 1170 for (;;) { 1171 KASSERT(sc->sc_rxhead < CPSW_NRXDESCS); 1172 1173 i = sc->sc_rxhead; 1174 KERNHIST_LOG(cpswhist, "rxhead %x CP %x\n", i, 1175 cpsw_read_4(sc, CPSW_CPDMA_RX_CP(0)), 0, 0); 1176 dm = rdp->rx_dm[i]; 1177 m = rdp->rx_mb[i]; 1178 1179 KASSERT(dm != NULL); 1180 KASSERT(m != NULL); 1181 1182 cpsw_get_rxdesc(sc, i, &bd); 1183 1184 if (ISSET(dw[3], CPDMA_BD_OWNER)) 1185 break; 1186 1187 if (ISSET(dw[3], CPDMA_BD_TDOWNCMPLT)) { 1188 sc->sc_rxrun = false; 1189 return 1; 1190 } 1191 1192 if ((dw[3] & (CPDMA_BD_SOP | CPDMA_BD_EOP)) != 1193 (CPDMA_BD_SOP | CPDMA_BD_EOP)) { 1194 //Debugger(); 1195 } 1196 1197 bus_dmamap_sync(sc->sc_bdt, dm, 0, dm->dm_mapsize, 1198 BUS_DMASYNC_POSTREAD); 1199 1200 if (cpsw_new_rxbuf(sc, i) != 0) { 1201 /* drop current packet, reuse buffer for new */ 1202 ifp->if_ierrors++; 1203 goto next; 1204 } 1205 1206 off = __SHIFTOUT(dw[2], (uint32_t)__BITS(26, 16)); 1207 len = __SHIFTOUT(dw[3], (uint32_t)__BITS(10, 0)); 1208 1209 if (ISSET(dw[3], CPDMA_BD_PASSCRC)) 1210 len -= ETHER_CRC_LEN; 1211 1212 m_set_rcvif(m, ifp); 1213 m->m_pkthdr.len = m->m_len = len; 1214 m->m_data += off; 1215 1216 if_percpuq_enqueue(ifp->if_percpuq, m); 1217 1218 next: 1219 sc->sc_rxhead = RXDESC_NEXT(sc->sc_rxhead); 1220 if (ISSET(dw[3], CPDMA_BD_EOQ)) { 1221 sc->sc_rxeoq = true; 1222 break; 1223 } else { 1224 sc->sc_rxeoq = false; 1225 } 1226 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(0), 1227 cpsw_rxdesc_paddr(sc, i)); 1228 } 1229 1230 if (sc->sc_rxeoq) { 1231 device_printf(sc->sc_dev, "rxeoq\n"); 1232 //Debugger(); 1233 } 1234 1235 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX); 1236 1237 return 1; 1238 } 1239 1240 static int 1241 cpsw_txintr(void *arg) 1242 { 1243 struct cpsw_softc * const sc = arg; 1244 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1245 struct cpsw_ring_data * const rdp = sc->sc_rdp; 1246 struct cpsw_cpdma_bd bd; 1247 const uint32_t * const dw = bd.word; 1248 bool handled = false; 1249 uint32_t tx0_cp; 1250 u_int cpi; 1251 1252 KERNHIST_FUNC(__func__); 1253 KERNHIST_CALLED_5(cpswhist, sc, 0, 0, 0); 1254 1255 KASSERT(sc->sc_txrun); 1256 1257 KERNHIST_LOG(cpswhist, "before txnext %x txhead %x txrun %x\n", 1258 sc->sc_txnext, sc->sc_txhead, sc->sc_txrun, 0); 1259 1260 tx0_cp = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)); 1261 1262 if (tx0_cp == 0xfffffffc) { 1263 /* Teardown, ack it */ 1264 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(0), 0xfffffffc); 1265 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 0); 1266 sc->sc_txrun = false; 1267 return 0; 1268 } 1269 1270 for (;;) { 1271 tx0_cp = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)); 1272 cpi = (tx0_cp - sc->sc_txdescs_pa) / sizeof(struct cpsw_cpdma_bd); 1273 KASSERT(sc->sc_txhead < CPSW_NTXDESCS); 1274 1275 KERNHIST_LOG(cpswhist, "txnext %x txhead %x txrun %x cpi %x\n", 1276 sc->sc_txnext, sc->sc_txhead, sc->sc_txrun, cpi); 1277 1278 cpsw_get_txdesc(sc, sc->sc_txhead, &bd); 1279 1280 if (dw[2] == 0) { 1281 //Debugger(); 1282 } 1283 1284 if (ISSET(dw[3], CPDMA_BD_SOP) == 0) 1285 goto next; 1286 1287 if (ISSET(dw[3], CPDMA_BD_OWNER)) { 1288 printf("pwned %x %x %x\n", cpi, sc->sc_txhead, 1289 sc->sc_txnext); 1290 break; 1291 } 1292 1293 if (ISSET(dw[3], CPDMA_BD_TDOWNCMPLT)) { 1294 sc->sc_txrun = false; 1295 return 1; 1296 } 1297 1298 bus_dmamap_sync(sc->sc_bdt, rdp->tx_dm[sc->sc_txhead], 1299 0, rdp->tx_dm[sc->sc_txhead]->dm_mapsize, 1300 BUS_DMASYNC_POSTWRITE); 1301 bus_dmamap_unload(sc->sc_bdt, rdp->tx_dm[sc->sc_txhead]); 1302 1303 m_freem(rdp->tx_mb[sc->sc_txhead]); 1304 rdp->tx_mb[sc->sc_txhead] = NULL; 1305 1306 ifp->if_opackets++; 1307 1308 handled = true; 1309 1310 ifp->if_flags &= ~IFF_OACTIVE; 1311 1312 next: 1313 if (ISSET(dw[3], CPDMA_BD_EOP) && ISSET(dw[3], CPDMA_BD_EOQ)) { 1314 sc->sc_txeoq = true; 1315 } 1316 if (sc->sc_txhead == cpi) { 1317 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(0), 1318 cpsw_txdesc_paddr(sc, cpi)); 1319 sc->sc_txhead = TXDESC_NEXT(sc->sc_txhead); 1320 break; 1321 } 1322 sc->sc_txhead = TXDESC_NEXT(sc->sc_txhead); 1323 if (ISSET(dw[3], CPDMA_BD_EOP) && ISSET(dw[3], CPDMA_BD_EOQ)) { 1324 sc->sc_txeoq = true; 1325 break; 1326 } 1327 } 1328 1329 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX); 1330 1331 if ((sc->sc_txnext != sc->sc_txhead) && sc->sc_txeoq) { 1332 if (cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)) == 0) { 1333 sc->sc_txeoq = false; 1334 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 1335 cpsw_txdesc_paddr(sc, sc->sc_txhead)); 1336 } 1337 } 1338 1339 KERNHIST_LOG(cpswhist, "after txnext %x txhead %x txrun %x\n", 1340 sc->sc_txnext, sc->sc_txhead, sc->sc_txrun, 0); 1341 KERNHIST_LOG(cpswhist, "CP %x HDP %x\n", 1342 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)), 1343 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)), 0, 0); 1344 1345 if (handled && sc->sc_txnext == sc->sc_txhead) 1346 ifp->if_timer = 0; 1347 1348 if (handled) 1349 if_schedule_deferred_start(ifp); 1350 1351 return handled; 1352 } 1353 1354 static int 1355 cpsw_miscintr(void *arg) 1356 { 1357 struct cpsw_softc * const sc = arg; 1358 uint32_t miscstat; 1359 uint32_t dmastat; 1360 uint32_t stat; 1361 1362 miscstat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0)); 1363 device_printf(sc->sc_dev, "%s %x FIRE\n", __func__, miscstat); 1364 1365 #define CPSW_MISC_HOST_PEND __BIT32(2) 1366 #define CPSW_MISC_STAT_PEND __BIT32(3) 1367 1368 if (ISSET(miscstat, CPSW_MISC_HOST_PEND)) { 1369 /* Host Error */ 1370 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 1371 printf("CPSW_CPDMA_DMA_INTSTAT_MASKED %x\n", dmastat); 1372 1373 printf("rxhead %02x\n", sc->sc_rxhead); 1374 1375 stat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS); 1376 printf("CPSW_CPDMA_DMASTATUS %x\n", stat); 1377 stat = cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)); 1378 printf("CPSW_CPDMA_TX0_HDP %x\n", stat); 1379 stat = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)); 1380 printf("CPSW_CPDMA_TX0_CP %x\n", stat); 1381 stat = cpsw_read_4(sc, CPSW_CPDMA_RX_HDP(0)); 1382 printf("CPSW_CPDMA_RX0_HDP %x\n", stat); 1383 stat = cpsw_read_4(sc, CPSW_CPDMA_RX_CP(0)); 1384 printf("CPSW_CPDMA_RX0_CP %x\n", stat); 1385 1386 //Debugger(); 1387 1388 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, dmastat); 1389 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 1390 printf("CPSW_CPDMA_DMA_INTSTAT_MASKED %x\n", dmastat); 1391 } 1392 1393 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC); 1394 1395 return 1; 1396 } 1397 1398 /* 1399 * 1400 * ALE support routines. 1401 * 1402 */ 1403 1404 static void 1405 cpsw_ale_entry_init(uint32_t *ale_entry) 1406 { 1407 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 1408 } 1409 1410 static void 1411 cpsw_ale_entry_set_mac(uint32_t *ale_entry, const uint8_t *mac) 1412 { 1413 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 1414 ale_entry[1] = mac[0] << 8 | mac[1]; 1415 } 1416 1417 static void 1418 cpsw_ale_entry_set_bcast_mac(uint32_t *ale_entry) 1419 { 1420 ale_entry[0] = 0xffffffff; 1421 ale_entry[1] = 0x0000ffff; 1422 } 1423 1424 static void 1425 cpsw_ale_entry_set(uint32_t *ale_entry, ale_entry_field_t field, uint32_t val) 1426 { 1427 /* Entry type[61:60] is addr entry(1), Mcast fwd state[63:62] is fw(3)*/ 1428 switch (field) { 1429 case ALE_ENTRY_TYPE: 1430 /* [61:60] */ 1431 ale_entry[1] |= (val & 0x3) << 28; 1432 break; 1433 case ALE_MCAST_FWD_STATE: 1434 /* [63:62] */ 1435 ale_entry[1] |= (val & 0x3) << 30; 1436 break; 1437 case ALE_PORT_MASK: 1438 /* [68:66] */ 1439 ale_entry[2] |= (val & 0x7) << 2; 1440 break; 1441 case ALE_PORT_NUMBER: 1442 /* [67:66] */ 1443 ale_entry[2] |= (val & 0x3) << 2; 1444 break; 1445 default: 1446 panic("Invalid ALE entry field: %d\n", field); 1447 } 1448 1449 return; 1450 } 1451 1452 static bool 1453 cpsw_ale_entry_mac_match(const uint32_t *ale_entry, const uint8_t *mac) 1454 { 1455 return (((ale_entry[1] >> 8) & 0xff) == mac[0]) && 1456 (((ale_entry[1] >> 0) & 0xff) == mac[1]) && 1457 (((ale_entry[0] >>24) & 0xff) == mac[2]) && 1458 (((ale_entry[0] >>16) & 0xff) == mac[3]) && 1459 (((ale_entry[0] >> 8) & 0xff) == mac[4]) && 1460 (((ale_entry[0] >> 0) & 0xff) == mac[5]); 1461 } 1462 1463 static void 1464 cpsw_ale_set_outgoing_mac(struct cpsw_softc *sc, int port, const uint8_t *mac) 1465 { 1466 cpsw_write_4(sc, CPSW_PORT_P_SA_HI(port), 1467 mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]); 1468 cpsw_write_4(sc, CPSW_PORT_P_SA_LO(port), 1469 mac[5] << 8 | mac[4]); 1470 } 1471 1472 static void 1473 cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 1474 { 1475 cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023); 1476 ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0); 1477 ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1); 1478 ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2); 1479 } 1480 1481 static void 1482 cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, 1483 const uint32_t *ale_entry) 1484 { 1485 cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]); 1486 cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]); 1487 cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]); 1488 cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023)); 1489 } 1490 1491 static int 1492 cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc) 1493 { 1494 int i; 1495 uint32_t ale_entry[3]; 1496 1497 /* First two entries are link address and broadcast. */ 1498 for (i = 2; i < CPSW_MAX_ALE_ENTRIES; i++) { 1499 cpsw_ale_read_entry(sc, i, ale_entry); 1500 if (((ale_entry[1] >> 28) & 3) == 1 && /* Address entry */ 1501 ((ale_entry[1] >> 8) & 1) == 1) { /* MCast link addr */ 1502 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 1503 cpsw_ale_write_entry(sc, i, ale_entry); 1504 } 1505 } 1506 return CPSW_MAX_ALE_ENTRIES; 1507 } 1508 1509 static int 1510 cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmask, uint8_t *mac) 1511 { 1512 int free_index = -1, matching_index = -1, i; 1513 uint32_t ale_entry[3]; 1514 1515 /* Find a matching entry or a free entry. */ 1516 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 1517 cpsw_ale_read_entry(sc, i, ale_entry); 1518 1519 /* Entry Type[61:60] is 0 for free entry */ 1520 if (free_index < 0 && ((ale_entry[1] >> 28) & 3) == 0) { 1521 free_index = i; 1522 } 1523 1524 if (cpsw_ale_entry_mac_match(ale_entry, mac)) { 1525 matching_index = i; 1526 break; 1527 } 1528 } 1529 1530 if (matching_index < 0) { 1531 if (free_index < 0) 1532 return ENOMEM; 1533 i = free_index; 1534 } 1535 1536 cpsw_ale_entry_init(ale_entry); 1537 1538 cpsw_ale_entry_set_mac(ale_entry, mac); 1539 cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS); 1540 cpsw_ale_entry_set(ale_entry, ALE_MCAST_FWD_STATE, ALE_FWSTATE_FWONLY); 1541 cpsw_ale_entry_set(ale_entry, ALE_PORT_MASK, portmask); 1542 1543 cpsw_ale_write_entry(sc, i, ale_entry); 1544 1545 return 0; 1546 } 1547 1548 static int 1549 cpsw_ale_update_addresses(struct cpsw_softc *sc, int purge) 1550 { 1551 uint8_t *mac = sc->sc_enaddr; 1552 uint32_t ale_entry[3]; 1553 int i; 1554 struct ethercom * const ec = &sc->sc_ec; 1555 struct ether_multi *ifma; 1556 1557 cpsw_ale_entry_init(ale_entry); 1558 /* Route incoming packets for our MAC address to Port 0 (host). */ 1559 /* For simplicity, keep this entry at table index 0 in the ALE. */ 1560 cpsw_ale_entry_set_mac(ale_entry, mac); 1561 cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS); 1562 cpsw_ale_entry_set(ale_entry, ALE_PORT_NUMBER, 0); 1563 cpsw_ale_write_entry(sc, 0, ale_entry); 1564 1565 /* Set outgoing MAC Address for Ports 1 and 2. */ 1566 for (i = CPSW_CPPI_PORTS; i < (CPSW_ETH_PORTS + CPSW_CPPI_PORTS); ++i) 1567 cpsw_ale_set_outgoing_mac(sc, i, mac); 1568 1569 /* Keep the broadcast address at table entry 1. */ 1570 cpsw_ale_entry_init(ale_entry); 1571 cpsw_ale_entry_set_bcast_mac(ale_entry); 1572 cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS); 1573 cpsw_ale_entry_set(ale_entry, ALE_MCAST_FWD_STATE, ALE_FWSTATE_FWONLY); 1574 cpsw_ale_entry_set(ale_entry, ALE_PORT_MASK, ALE_PORT_MASK_ALL); 1575 cpsw_ale_write_entry(sc, 1, ale_entry); 1576 1577 /* SIOCDELMULTI doesn't specify the particular address 1578 being removed, so we have to remove all and rebuild. */ 1579 if (purge) 1580 cpsw_ale_remove_all_mc_entries(sc); 1581 1582 /* Set other multicast addrs desired. */ 1583 LIST_FOREACH(ifma, &ec->ec_multiaddrs, enm_list) { 1584 cpsw_ale_mc_entry_set(sc, ALE_PORT_MASK_ALL, ifma->enm_addrlo); 1585 } 1586 1587 return 0; 1588 } 1589
Indexes created Sat Oct 25 06:10:15 GMT 2025