if_cpsw.c revision 1.6.2.4
1 /* $NetBSD: if_cpsw.c,v 1.6.2.4 2023/03/03 17:04:17 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 2012 Damjan Marion <dmarion (at) Freebsd.org> 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 43 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 46 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 48 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 52 * SUCH DAMAGE. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.6.2.4 2023/03/03 17:04:17 martin Exp $"); 57 58 #include <sys/param.h> 59 #include <sys/bus.h> 60 #include <sys/device.h> 61 #include <sys/ioctl.h> 62 #include <sys/intr.h> 63 #include <sys/kmem.h> 64 #include <sys/mutex.h> 65 #include <sys/systm.h> 66 #include <sys/kernel.h> 67 68 #include <net/if.h> 69 #include <net/if_ether.h> 70 #include <net/if_media.h> 71 #include <net/bpf.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/fdt/fdtvar.h> 77 78 #include <arm/ti/if_cpswreg.h> 79 80 #define FDT_INTR_FLAGS 0 81 82 #define CPSW_TXFRAGS 16 83 84 #define CPSW_CPPI_RAM_SIZE (0x2000) 85 #define CPSW_CPPI_RAM_TXDESCS_SIZE (CPSW_CPPI_RAM_SIZE/2) 86 #define CPSW_CPPI_RAM_RXDESCS_SIZE \ 87 (CPSW_CPPI_RAM_SIZE - CPSW_CPPI_RAM_TXDESCS_SIZE) 88 #define CPSW_CPPI_RAM_TXDESCS_BASE (CPSW_CPPI_RAM_OFFSET + 0x0000) 89 #define CPSW_CPPI_RAM_RXDESCS_BASE \ 90 (CPSW_CPPI_RAM_OFFSET + CPSW_CPPI_RAM_TXDESCS_SIZE) 91 92 #define CPSW_NTXDESCS (CPSW_CPPI_RAM_TXDESCS_SIZE/sizeof(struct cpsw_cpdma_bd)) 93 #define CPSW_NRXDESCS (CPSW_CPPI_RAM_RXDESCS_SIZE/sizeof(struct cpsw_cpdma_bd)) 94 95 CTASSERT(powerof2(CPSW_NTXDESCS)); 96 CTASSERT(powerof2(CPSW_NRXDESCS)); 97 98 #undef CPSW_DEBUG_DMA /* define this for DMA debugging */ 99 100 #define CPSW_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 101 102 #define TXDESC_NEXT(x) cpsw_txdesc_adjust((x), 1) 103 #define TXDESC_PREV(x) cpsw_txdesc_adjust((x), -1) 104 105 #define RXDESC_NEXT(x) cpsw_rxdesc_adjust((x), 1) 106 #define RXDESC_PREV(x) cpsw_rxdesc_adjust((x), -1) 107 108 struct cpsw_ring_data { 109 bus_dmamap_t tx_dm[CPSW_NTXDESCS]; 110 struct mbuf *tx_mb[CPSW_NTXDESCS]; 111 bus_dmamap_t rx_dm[CPSW_NRXDESCS]; 112 struct mbuf *rx_mb[CPSW_NRXDESCS]; 113 }; 114 115 struct cpsw_softc { 116 device_t sc_dev; 117 bus_space_tag_t sc_bst; 118 bus_space_handle_t sc_bsh; 119 bus_size_t sc_bss; 120 bus_dma_tag_t sc_bdt; 121 bus_space_handle_t sc_bsh_txdescs; 122 bus_space_handle_t sc_bsh_rxdescs; 123 bus_addr_t sc_txdescs_pa; 124 bus_addr_t sc_rxdescs_pa; 125 struct ethercom sc_ec; 126 struct mii_data sc_mii; 127 bool sc_phy_has_1000t; 128 bool sc_attached; 129 callout_t sc_tick_ch; 130 void *sc_ih; 131 struct cpsw_ring_data *sc_rdp; 132 volatile u_int sc_txnext; 133 volatile u_int sc_txhead; 134 volatile u_int sc_rxhead; 135 void *sc_rxthih; 136 void *sc_rxih; 137 void *sc_txih; 138 void *sc_miscih; 139 void *sc_txpad; 140 bus_dmamap_t sc_txpad_dm; 141 #define sc_txpad_pa sc_txpad_dm->dm_segs[0].ds_addr 142 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 143 volatile bool sc_txrun; 144 volatile bool sc_rxrun; 145 volatile bool sc_txeoq; 146 volatile bool sc_rxeoq; 147 }; 148 149 static int cpsw_match(device_t, cfdata_t, void *); 150 static void cpsw_attach(device_t, device_t, void *); 151 static int cpsw_detach(device_t, int); 152 153 static void cpsw_start(struct ifnet *); 154 static int cpsw_ioctl(struct ifnet *, u_long, void *); 155 static void cpsw_watchdog(struct ifnet *); 156 static int cpsw_init(struct ifnet *); 157 static void cpsw_stop(struct ifnet *, int); 158 159 static int cpsw_mii_readreg(device_t, int, int, uint16_t *); 160 static int cpsw_mii_writereg(device_t, int, int, uint16_t); 161 static void cpsw_mii_statchg(struct ifnet *); 162 163 static int cpsw_new_rxbuf(struct cpsw_softc * const, const u_int); 164 static void cpsw_tick(void *); 165 166 static int cpsw_rxthintr(void *); 167 static int cpsw_rxintr(void *); 168 static int cpsw_txintr(void *); 169 static int cpsw_miscintr(void *); 170 171 /* ALE support */ 172 #define CPSW_MAX_ALE_ENTRIES 1024 173 174 static int cpsw_ale_update_addresses(struct cpsw_softc *, int purge); 175 176 CFATTACH_DECL_NEW(cpsw, sizeof(struct cpsw_softc), 177 cpsw_match, cpsw_attach, cpsw_detach, NULL); 178 179 #include <sys/kernhist.h> 180 KERNHIST_DEFINE(cpswhist); 181 182 #define CPSWHIST_CALLARGS(A,B,C,D) do { \ 183 KERNHIST_CALLARGS(cpswhist, "%jx %jx %jx %jx", \ 184 (uintptr_t)(A), (uintptr_t)(B), (uintptr_t)(C), (uintptr_t)(D));\ 185 } while (0) 186 187 188 static inline u_int 189 cpsw_txdesc_adjust(u_int x, int y) 190 { 191 return (((x) + y) & (CPSW_NTXDESCS - 1)); 192 } 193 194 static inline u_int 195 cpsw_rxdesc_adjust(u_int x, int y) 196 { 197 return (((x) + y) & (CPSW_NRXDESCS - 1)); 198 } 199 200 static inline uint32_t 201 cpsw_read_4(struct cpsw_softc * const sc, bus_size_t const offset) 202 { 203 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, offset); 204 } 205 206 static inline void 207 cpsw_write_4(struct cpsw_softc * const sc, bus_size_t const offset, 208 uint32_t const value) 209 { 210 bus_space_write_4(sc->sc_bst, sc->sc_bsh, offset, value); 211 } 212 213 static inline void 214 cpsw_set_txdesc_next(struct cpsw_softc * const sc, const u_int i, uint32_t n) 215 { 216 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i + 0; 217 218 KERNHIST_FUNC(__func__); 219 CPSWHIST_CALLARGS(sc, i, n, 0); 220 221 bus_space_write_4(sc->sc_bst, sc->sc_bsh_txdescs, o, n); 222 } 223 224 static inline void 225 cpsw_set_rxdesc_next(struct cpsw_softc * const sc, const u_int i, uint32_t n) 226 { 227 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i + 0; 228 229 KERNHIST_FUNC(__func__); 230 CPSWHIST_CALLARGS(sc, i, n, 0); 231 232 bus_space_write_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, n); 233 } 234 235 static inline void 236 cpsw_get_txdesc(struct cpsw_softc * const sc, const u_int i, 237 struct cpsw_cpdma_bd * const bdp) 238 { 239 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 240 uint32_t * const dp = bdp->word; 241 const bus_size_t c = __arraycount(bdp->word); 242 243 KERNHIST_FUNC(__func__); 244 CPSWHIST_CALLARGS(sc, i, bdp, 0); 245 246 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh_txdescs, o, dp, c); 247 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 248 dp[0], dp[1], dp[2], dp[3]); 249 } 250 251 static inline void 252 cpsw_set_txdesc(struct cpsw_softc * const sc, const u_int i, 253 struct cpsw_cpdma_bd * const bdp) 254 { 255 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 256 uint32_t * const dp = bdp->word; 257 const bus_size_t c = __arraycount(bdp->word); 258 259 KERNHIST_FUNC(__func__); 260 CPSWHIST_CALLARGS(sc, i, bdp, 0); 261 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 262 dp[0], dp[1], dp[2], dp[3]); 263 264 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh_txdescs, o, dp, c); 265 } 266 267 static inline void 268 cpsw_get_rxdesc(struct cpsw_softc * const sc, const u_int i, 269 struct cpsw_cpdma_bd * const bdp) 270 { 271 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 272 uint32_t * const dp = bdp->word; 273 const bus_size_t c = __arraycount(bdp->word); 274 275 KERNHIST_FUNC(__func__); 276 CPSWHIST_CALLARGS(sc, i, bdp, 0); 277 278 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, dp, c); 279 280 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 281 dp[0], dp[1], dp[2], dp[3]); 282 } 283 284 static inline void 285 cpsw_set_rxdesc(struct cpsw_softc * const sc, const u_int i, 286 struct cpsw_cpdma_bd * const bdp) 287 { 288 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 289 uint32_t * const dp = bdp->word; 290 const bus_size_t c = __arraycount(bdp->word); 291 292 KERNHIST_FUNC(__func__); 293 CPSWHIST_CALLARGS(sc, i, bdp, 0); 294 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 295 dp[0], dp[1], dp[2], dp[3]); 296 297 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, dp, c); 298 } 299 300 static inline bus_addr_t 301 cpsw_txdesc_paddr(struct cpsw_softc * const sc, u_int x) 302 { 303 KASSERT(x < CPSW_NTXDESCS); 304 return sc->sc_txdescs_pa + sizeof(struct cpsw_cpdma_bd) * x; 305 } 306 307 static inline bus_addr_t 308 cpsw_rxdesc_paddr(struct cpsw_softc * const sc, u_int x) 309 { 310 KASSERT(x < CPSW_NRXDESCS); 311 return sc->sc_rxdescs_pa + sizeof(struct cpsw_cpdma_bd) * x; 312 } 313 314 315 static int 316 cpsw_match(device_t parent, cfdata_t cf, void *aux) 317 { 318 struct fdt_attach_args * const faa = aux; 319 320 static const char * const compatible[] = { 321 "ti,am335x-cpsw", 322 "ti,cpsw", 323 NULL 324 }; 325 326 return of_match_compatible(faa->faa_phandle, compatible); 327 } 328 329 static bool 330 cpsw_phy_has_1000t(struct cpsw_softc * const sc) 331 { 332 struct ifmedia_entry *ifm; 333 334 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 335 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T) 336 return true; 337 } 338 return false; 339 } 340 341 static int 342 cpsw_detach(device_t self, int flags) 343 { 344 struct cpsw_softc * const sc = device_private(self); 345 struct ifnet *ifp = &sc->sc_ec.ec_if; 346 u_int i; 347 348 /* Succeed now if there's no work to do. */ 349 if (!sc->sc_attached) 350 return 0; 351 352 sc->sc_attached = false; 353 354 /* Stop the interface. Callouts are stopped in it. */ 355 cpsw_stop(ifp, 1); 356 357 /* Destroy our callout. */ 358 callout_destroy(&sc->sc_tick_ch); 359 360 /* Let go of the interrupts */ 361 intr_disestablish(sc->sc_rxthih); 362 intr_disestablish(sc->sc_rxih); 363 intr_disestablish(sc->sc_txih); 364 intr_disestablish(sc->sc_miscih); 365 366 /* Delete all media. */ 367 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 368 369 ether_ifdetach(ifp); 370 if_detach(ifp); 371 372 /* Free the packet padding buffer */ 373 kmem_free(sc->sc_txpad, ETHER_MIN_LEN); 374 bus_dmamap_destroy(sc->sc_bdt, sc->sc_txpad_dm); 375 376 /* Destroy all the descriptors */ 377 for (i = 0; i < CPSW_NTXDESCS; i++) 378 bus_dmamap_destroy(sc->sc_bdt, sc->sc_rdp->tx_dm[i]); 379 for (i = 0; i < CPSW_NRXDESCS; i++) 380 bus_dmamap_destroy(sc->sc_bdt, sc->sc_rdp->rx_dm[i]); 381 kmem_free(sc->sc_rdp, sizeof(*sc->sc_rdp)); 382 383 /* Unmap */ 384 bus_space_unmap(sc->sc_bst, sc->sc_bsh, sc->sc_bss); 385 386 387 return 0; 388 } 389 390 static void 391 cpsw_attach(device_t parent, device_t self, void *aux) 392 { 393 struct fdt_attach_args * const faa = aux; 394 struct cpsw_softc * const sc = device_private(self); 395 struct ethercom * const ec = &sc->sc_ec; 396 struct ifnet * const ifp = &ec->ec_if; 397 struct mii_data * const mii = &sc->sc_mii; 398 const int phandle = faa->faa_phandle; 399 const uint8_t *macaddr; 400 bus_addr_t addr; 401 bus_size_t size; 402 int error, slave, len; 403 u_int i; 404 405 KERNHIST_INIT(cpswhist, 4096); 406 407 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 408 aprint_error(": couldn't get registers\n"); 409 return; 410 } 411 412 sc->sc_dev = self; 413 414 aprint_normal(": TI Layer 2 3-Port Switch\n"); 415 aprint_naive("\n"); 416 417 callout_init(&sc->sc_tick_ch, 0); 418 callout_setfunc(&sc->sc_tick_ch, cpsw_tick, sc); 419 420 macaddr = NULL; 421 slave = of_find_firstchild_byname(phandle, "slave"); 422 if (slave > 0) { 423 macaddr = fdtbus_get_prop(slave, "mac-address", &len); 424 if (len != ETHER_ADDR_LEN) 425 macaddr = NULL; 426 } 427 if (macaddr == NULL) { 428 #if 0 429 /* grab mac_id0 from AM335x control module */ 430 uint32_t reg_lo, reg_hi; 431 432 if (sitara_cm_reg_read_4(OMAP2SCM_MAC_ID0_LO, ®_lo) == 0 && 433 sitara_cm_reg_read_4(OMAP2SCM_MAC_ID0_HI, ®_hi) == 0) { 434 sc->sc_enaddr[0] = (reg_hi >> 0) & 0xff; 435 sc->sc_enaddr[1] = (reg_hi >> 8) & 0xff; 436 sc->sc_enaddr[2] = (reg_hi >> 16) & 0xff; 437 sc->sc_enaddr[3] = (reg_hi >> 24) & 0xff; 438 sc->sc_enaddr[4] = (reg_lo >> 0) & 0xff; 439 sc->sc_enaddr[5] = (reg_lo >> 8) & 0xff; 440 } else 441 #endif 442 { 443 aprint_error_dev(sc->sc_dev, 444 "using fake station address\n"); 445 /* 'N' happens to have the Local bit set */ 446 #if 0 447 sc->sc_enaddr[0] = 'N'; 448 sc->sc_enaddr[1] = 'e'; 449 sc->sc_enaddr[2] = 't'; 450 sc->sc_enaddr[3] = 'B'; 451 sc->sc_enaddr[4] = 'S'; 452 sc->sc_enaddr[5] = 'D'; 453 #else 454 /* XXX Glor */ 455 sc->sc_enaddr[0] = 0xd4; 456 sc->sc_enaddr[1] = 0x94; 457 sc->sc_enaddr[2] = 0xa1; 458 sc->sc_enaddr[3] = 0x97; 459 sc->sc_enaddr[4] = 0x03; 460 sc->sc_enaddr[5] = 0x94; 461 #endif 462 } 463 } else { 464 memcpy(sc->sc_enaddr, macaddr, ETHER_ADDR_LEN); 465 } 466 467 sc->sc_rxthih = fdtbus_intr_establish(phandle, CPSW_INTROFF_RXTH, IPL_VM, FDT_INTR_FLAGS, cpsw_rxthintr, sc); 468 sc->sc_rxih = fdtbus_intr_establish(phandle, CPSW_INTROFF_RX, IPL_VM, FDT_INTR_FLAGS, cpsw_rxintr, sc); 469 sc->sc_txih = fdtbus_intr_establish(phandle, CPSW_INTROFF_TX, IPL_VM, FDT_INTR_FLAGS, cpsw_txintr, sc); 470 sc->sc_miscih = fdtbus_intr_establish(phandle, CPSW_INTROFF_MISC, IPL_VM, FDT_INTR_FLAGS, cpsw_miscintr, sc); 471 472 sc->sc_bst = faa->faa_bst; 473 sc->sc_bss = size; 474 sc->sc_bdt = faa->faa_dmat; 475 476 error = bus_space_map(sc->sc_bst, addr, size, 0, 477 &sc->sc_bsh); 478 if (error) { 479 aprint_error_dev(sc->sc_dev, 480 "can't map registers: %d\n", error); 481 return; 482 } 483 484 sc->sc_txdescs_pa = addr + CPSW_CPPI_RAM_TXDESCS_BASE; 485 error = bus_space_subregion(sc->sc_bst, sc->sc_bsh, 486 CPSW_CPPI_RAM_TXDESCS_BASE, CPSW_CPPI_RAM_TXDESCS_SIZE, 487 &sc->sc_bsh_txdescs); 488 if (error) { 489 aprint_error_dev(sc->sc_dev, 490 "can't subregion tx ring SRAM: %d\n", error); 491 return; 492 } 493 aprint_debug_dev(sc->sc_dev, "txdescs at %p\n", 494 (void *)sc->sc_bsh_txdescs); 495 496 sc->sc_rxdescs_pa = addr + CPSW_CPPI_RAM_RXDESCS_BASE; 497 error = bus_space_subregion(sc->sc_bst, sc->sc_bsh, 498 CPSW_CPPI_RAM_RXDESCS_BASE, CPSW_CPPI_RAM_RXDESCS_SIZE, 499 &sc->sc_bsh_rxdescs); 500 if (error) { 501 aprint_error_dev(sc->sc_dev, 502 "can't subregion rx ring SRAM: %d\n", error); 503 return; 504 } 505 aprint_debug_dev(sc->sc_dev, "rxdescs at %p\n", 506 (void *)sc->sc_bsh_rxdescs); 507 508 sc->sc_rdp = kmem_alloc(sizeof(*sc->sc_rdp), KM_SLEEP); 509 510 for (i = 0; i < CPSW_NTXDESCS; i++) { 511 if ((error = bus_dmamap_create(sc->sc_bdt, MCLBYTES, 512 CPSW_TXFRAGS, MCLBYTES, 0, 0, 513 &sc->sc_rdp->tx_dm[i])) != 0) { 514 aprint_error_dev(sc->sc_dev, 515 "unable to create tx DMA map: %d\n", error); 516 } 517 sc->sc_rdp->tx_mb[i] = NULL; 518 } 519 520 for (i = 0; i < CPSW_NRXDESCS; i++) { 521 if ((error = bus_dmamap_create(sc->sc_bdt, MCLBYTES, 1, 522 MCLBYTES, 0, 0, &sc->sc_rdp->rx_dm[i])) != 0) { 523 aprint_error_dev(sc->sc_dev, 524 "unable to create rx DMA map: %d\n", error); 525 } 526 sc->sc_rdp->rx_mb[i] = NULL; 527 } 528 529 sc->sc_txpad = kmem_zalloc(ETHER_MIN_LEN, KM_SLEEP); 530 bus_dmamap_create(sc->sc_bdt, ETHER_MIN_LEN, 1, ETHER_MIN_LEN, 0, 531 BUS_DMA_WAITOK, &sc->sc_txpad_dm); 532 bus_dmamap_load(sc->sc_bdt, sc->sc_txpad_dm, sc->sc_txpad, 533 ETHER_MIN_LEN, NULL, BUS_DMA_WAITOK | BUS_DMA_WRITE); 534 bus_dmamap_sync(sc->sc_bdt, sc->sc_txpad_dm, 0, ETHER_MIN_LEN, 535 BUS_DMASYNC_PREWRITE); 536 537 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 538 ether_sprintf(sc->sc_enaddr)); 539 540 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 541 ifp->if_softc = sc; 542 ifp->if_capabilities = 0; 543 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 544 ifp->if_start = cpsw_start; 545 ifp->if_ioctl = cpsw_ioctl; 546 ifp->if_init = cpsw_init; 547 ifp->if_stop = cpsw_stop; 548 ifp->if_watchdog = cpsw_watchdog; 549 IFQ_SET_READY(&ifp->if_snd); 550 551 cpsw_stop(ifp, 0); 552 553 mii->mii_ifp = ifp; 554 mii->mii_readreg = cpsw_mii_readreg; 555 mii->mii_writereg = cpsw_mii_writereg; 556 mii->mii_statchg = cpsw_mii_statchg; 557 558 sc->sc_ec.ec_mii = mii; 559 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 560 561 /* Initialize MDIO */ 562 cpsw_write_4(sc, MDIOCONTROL, 563 MDIOCTL_ENABLE | MDIOCTL_FAULTENB | MDIOCTL_CLKDIV(0xff)); 564 /* Clear ALE */ 565 cpsw_write_4(sc, CPSW_ALE_CONTROL, ALECTL_CLEAR_TABLE); 566 567 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 0, 0); 568 if (LIST_FIRST(&mii->mii_phys) == NULL) { 569 aprint_error_dev(self, "no PHY found!\n"); 570 sc->sc_phy_has_1000t = false; 571 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 572 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 573 } else { 574 sc->sc_phy_has_1000t = cpsw_phy_has_1000t(sc); 575 576 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 577 } 578 579 if_attach(ifp); 580 if_deferred_start_init(ifp, NULL); 581 ether_ifattach(ifp, sc->sc_enaddr); 582 583 /* The attach is successful. */ 584 sc->sc_attached = true; 585 586 return; 587 } 588 589 static void 590 cpsw_start(struct ifnet *ifp) 591 { 592 struct cpsw_softc * const sc = ifp->if_softc; 593 struct cpsw_ring_data * const rdp = sc->sc_rdp; 594 struct cpsw_cpdma_bd bd; 595 uint32_t * const dw = bd.word; 596 struct mbuf *m; 597 bus_dmamap_t dm; 598 u_int eopi __diagused = ~0; 599 u_int seg; 600 u_int txfree; 601 int txstart = -1; 602 int error; 603 bool pad; 604 u_int mlen; 605 606 KERNHIST_FUNC(__func__); 607 CPSWHIST_CALLARGS(sc, 0, 0, 0); 608 609 if (__predict_false((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != 610 IFF_RUNNING)) { 611 return; 612 } 613 614 if (sc->sc_txnext >= sc->sc_txhead) 615 txfree = CPSW_NTXDESCS - 1 + sc->sc_txhead - sc->sc_txnext; 616 else 617 txfree = sc->sc_txhead - sc->sc_txnext - 1; 618 619 KERNHIST_LOG(cpswhist, "start txf %x txh %x txn %x txr %x\n", 620 txfree, sc->sc_txhead, sc->sc_txnext, sc->sc_txrun); 621 622 while (txfree > 0) { 623 IFQ_POLL(&ifp->if_snd, m); 624 if (m == NULL) 625 break; 626 627 dm = rdp->tx_dm[sc->sc_txnext]; 628 629 error = bus_dmamap_load_mbuf(sc->sc_bdt, dm, m, BUS_DMA_NOWAIT); 630 if (error == EFBIG) { 631 device_printf(sc->sc_dev, "won't fit\n"); 632 IFQ_DEQUEUE(&ifp->if_snd, m); 633 m_freem(m); 634 ifp->if_oerrors++; 635 continue; 636 } else if (error != 0) { 637 device_printf(sc->sc_dev, "error\n"); 638 break; 639 } 640 641 if (dm->dm_nsegs + 1 >= txfree) { 642 ifp->if_flags |= IFF_OACTIVE; 643 bus_dmamap_unload(sc->sc_bdt, dm); 644 break; 645 } 646 647 mlen = m_length(m); 648 pad = mlen < CPSW_PAD_LEN; 649 650 KASSERT(rdp->tx_mb[sc->sc_txnext] == NULL); 651 rdp->tx_mb[sc->sc_txnext] = m; 652 IFQ_DEQUEUE(&ifp->if_snd, m); 653 654 bus_dmamap_sync(sc->sc_bdt, dm, 0, dm->dm_mapsize, 655 BUS_DMASYNC_PREWRITE); 656 657 if (txstart == -1) 658 txstart = sc->sc_txnext; 659 eopi = sc->sc_txnext; 660 for (seg = 0; seg < dm->dm_nsegs; seg++) { 661 dw[0] = cpsw_txdesc_paddr(sc, 662 TXDESC_NEXT(sc->sc_txnext)); 663 dw[1] = dm->dm_segs[seg].ds_addr; 664 dw[2] = dm->dm_segs[seg].ds_len; 665 dw[3] = 0; 666 667 if (seg == 0) 668 dw[3] |= CPDMA_BD_SOP | CPDMA_BD_OWNER | 669 MAX(mlen, CPSW_PAD_LEN); 670 671 if ((seg == dm->dm_nsegs - 1) && !pad) 672 dw[3] |= CPDMA_BD_EOP; 673 674 cpsw_set_txdesc(sc, sc->sc_txnext, &bd); 675 txfree--; 676 eopi = sc->sc_txnext; 677 sc->sc_txnext = TXDESC_NEXT(sc->sc_txnext); 678 } 679 if (pad) { 680 dw[0] = cpsw_txdesc_paddr(sc, 681 TXDESC_NEXT(sc->sc_txnext)); 682 dw[1] = sc->sc_txpad_pa; 683 dw[2] = CPSW_PAD_LEN - mlen; 684 dw[3] = CPDMA_BD_EOP; 685 686 cpsw_set_txdesc(sc, sc->sc_txnext, &bd); 687 txfree--; 688 eopi = sc->sc_txnext; 689 sc->sc_txnext = TXDESC_NEXT(sc->sc_txnext); 690 } 691 692 bpf_mtap(ifp, m, BPF_D_OUT); 693 } 694 695 if (txstart >= 0) { 696 ifp->if_timer = 5; 697 /* terminate the new chain */ 698 KASSERT(eopi == TXDESC_PREV(sc->sc_txnext)); 699 cpsw_set_txdesc_next(sc, TXDESC_PREV(sc->sc_txnext), 0); 700 KERNHIST_LOG(cpswhist, "CP %x HDP %x s %x e %x\n", 701 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)), 702 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)), txstart, eopi); 703 /* link the new chain on */ 704 cpsw_set_txdesc_next(sc, TXDESC_PREV(txstart), 705 cpsw_txdesc_paddr(sc, txstart)); 706 if (sc->sc_txeoq) { 707 /* kick the dma engine */ 708 sc->sc_txeoq = false; 709 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 710 cpsw_txdesc_paddr(sc, txstart)); 711 } 712 } 713 KERNHIST_LOG(cpswhist, "end txf %x txh %x txn %x txr %x\n", 714 txfree, sc->sc_txhead, sc->sc_txnext, sc->sc_txrun); 715 } 716 717 static int 718 cpsw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 719 { 720 const int s = splnet(); 721 int error = 0; 722 723 switch (cmd) { 724 default: 725 error = ether_ioctl(ifp, cmd, data); 726 if (error == ENETRESET) { 727 error = 0; 728 } 729 break; 730 } 731 732 splx(s); 733 734 return error; 735 } 736 737 static void 738 cpsw_watchdog(struct ifnet *ifp) 739 { 740 struct cpsw_softc *sc = ifp->if_softc; 741 742 device_printf(sc->sc_dev, "device timeout\n"); 743 744 ifp->if_oerrors++; 745 cpsw_init(ifp); 746 cpsw_start(ifp); 747 } 748 749 static int 750 cpsw_mii_wait(struct cpsw_softc * const sc, int reg) 751 { 752 u_int tries; 753 754 for (tries = 0; tries < 1000; tries++) { 755 if ((cpsw_read_4(sc, reg) & __BIT(31)) == 0) 756 return 0; 757 delay(1); 758 } 759 return ETIMEDOUT; 760 } 761 762 static int 763 cpsw_mii_readreg(device_t dev, int phy, int reg, uint16_t *val) 764 { 765 struct cpsw_softc * const sc = device_private(dev); 766 uint32_t v; 767 768 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 769 return -1; 770 771 cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | 772 ((reg & 0x1F) << 21) | ((phy & 0x1F) << 16)); 773 774 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 775 return -1; 776 777 v = cpsw_read_4(sc, MDIOUSERACCESS0); 778 if (v & __BIT(29)) { 779 *val = v & 0xffff; 780 return 0; 781 } 782 783 return -1; 784 } 785 786 static int 787 cpsw_mii_writereg(device_t dev, int phy, int reg, uint16_t val) 788 { 789 struct cpsw_softc * const sc = device_private(dev); 790 uint32_t v; 791 792 KASSERT((val & 0xffff0000UL) == 0); 793 794 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 795 goto out; 796 797 cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | (1 << 30) | 798 ((reg & 0x1F) << 21) | ((phy & 0x1F) << 16) | val); 799 800 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 801 goto out; 802 803 v = cpsw_read_4(sc, MDIOUSERACCESS0); 804 if ((v & __BIT(29)) == 0) { 805 out: 806 device_printf(sc->sc_dev, "%s error\n", __func__); 807 return -1; 808 } 809 810 return 0; 811 } 812 813 static void 814 cpsw_mii_statchg(struct ifnet *ifp) 815 { 816 return; 817 } 818 819 static int 820 cpsw_new_rxbuf(struct cpsw_softc * const sc, const u_int i) 821 { 822 struct cpsw_ring_data * const rdp = sc->sc_rdp; 823 const u_int h = RXDESC_PREV(i); 824 struct cpsw_cpdma_bd bd; 825 uint32_t * const dw = bd.word; 826 struct mbuf *m; 827 int error = ENOBUFS; 828 829 MGETHDR(m, M_DONTWAIT, MT_DATA); 830 if (m == NULL) { 831 goto reuse; 832 } 833 834 MCLGET(m, M_DONTWAIT); 835 if ((m->m_flags & M_EXT) == 0) { 836 m_freem(m); 837 goto reuse; 838 } 839 840 /* We have a new buffer, prepare it for the ring. */ 841 842 if (rdp->rx_mb[i] != NULL) 843 bus_dmamap_unload(sc->sc_bdt, rdp->rx_dm[i]); 844 845 m->m_len = m->m_pkthdr.len = MCLBYTES; 846 847 rdp->rx_mb[i] = m; 848 849 error = bus_dmamap_load_mbuf(sc->sc_bdt, rdp->rx_dm[i], rdp->rx_mb[i], 850 BUS_DMA_READ | BUS_DMA_NOWAIT); 851 if (error) { 852 device_printf(sc->sc_dev, "can't load rx DMA map %d: %d\n", 853 i, error); 854 } 855 856 bus_dmamap_sync(sc->sc_bdt, rdp->rx_dm[i], 857 0, rdp->rx_dm[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 858 859 error = 0; 860 861 reuse: 862 /* (re-)setup the descriptor */ 863 dw[0] = 0; 864 dw[1] = rdp->rx_dm[i]->dm_segs[0].ds_addr; 865 dw[2] = MIN(0x7ff, rdp->rx_dm[i]->dm_segs[0].ds_len); 866 dw[3] = CPDMA_BD_OWNER; 867 868 cpsw_set_rxdesc(sc, i, &bd); 869 /* and link onto ring */ 870 cpsw_set_rxdesc_next(sc, h, cpsw_rxdesc_paddr(sc, i)); 871 872 return error; 873 } 874 875 static int 876 cpsw_init(struct ifnet *ifp) 877 { 878 struct cpsw_softc * const sc = ifp->if_softc; 879 struct mii_data * const mii = &sc->sc_mii; 880 int i; 881 882 cpsw_stop(ifp, 0); 883 884 sc->sc_txnext = 0; 885 sc->sc_txhead = 0; 886 887 /* Reset wrapper */ 888 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 889 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 890 ; 891 892 /* Reset SS */ 893 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 894 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 895 ; 896 897 /* Clear table and enable ALE */ 898 cpsw_write_4(sc, CPSW_ALE_CONTROL, 899 ALECTL_ENABLE_ALE | ALECTL_CLEAR_TABLE); 900 901 /* Reset and init Sliver port 1 and 2 */ 902 for (i = 0; i < CPSW_ETH_PORTS; i++) { 903 uint32_t macctl; 904 905 /* Reset */ 906 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 907 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 908 ; 909 /* Set Slave Mapping */ 910 cpsw_write_4(sc, CPSW_SL_RX_PRI_MAP(i), 0x76543210); 911 cpsw_write_4(sc, CPSW_PORT_P_TX_PRI_MAP(i+1), 0x33221100); 912 cpsw_write_4(sc, CPSW_SL_RX_MAXLEN(i), 0x5f2); 913 /* Set MAC Address */ 914 cpsw_write_4(sc, CPSW_PORT_P_SA_HI(i+1), 915 sc->sc_enaddr[0] | (sc->sc_enaddr[1] << 8) | 916 (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[3] << 24)); 917 cpsw_write_4(sc, CPSW_PORT_P_SA_LO(i+1), 918 sc->sc_enaddr[4] | (sc->sc_enaddr[5] << 8)); 919 920 /* Set MACCONTROL for ports 0,1 */ 921 macctl = SLMACCTL_FULLDUPLEX | SLMACCTL_GMII_EN | 922 SLMACCTL_IFCTL_A; 923 if (sc->sc_phy_has_1000t) 924 macctl |= SLMACCTL_GIG; 925 cpsw_write_4(sc, CPSW_SL_MACCONTROL(i), macctl); 926 927 /* Set ALE port to forwarding(3) */ 928 cpsw_write_4(sc, CPSW_ALE_PORTCTL(i+1), 3); 929 } 930 931 /* Set Host Port Mapping */ 932 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210); 933 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0); 934 935 /* Set ALE port to forwarding(3) */ 936 cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 3); 937 938 /* Initialize addrs */ 939 cpsw_ale_update_addresses(sc, 1); 940 941 cpsw_write_4(sc, CPSW_SS_PTYPE, 0); 942 cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7); 943 944 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 945 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 946 ; 947 948 for (i = 0; i < 8; i++) { 949 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0); 950 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0); 951 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0); 952 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0); 953 } 954 955 bus_space_set_region_4(sc->sc_bst, sc->sc_bsh_txdescs, 0, 0, 956 CPSW_CPPI_RAM_TXDESCS_SIZE/4); 957 958 sc->sc_txhead = 0; 959 sc->sc_txnext = 0; 960 961 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0); 962 963 bus_space_set_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, 0, 0, 964 CPSW_CPPI_RAM_RXDESCS_SIZE/4); 965 /* Initialize RX Buffer Descriptors */ 966 cpsw_set_rxdesc_next(sc, RXDESC_PREV(0), 0); 967 for (i = 0; i < CPSW_NRXDESCS; i++) { 968 cpsw_new_rxbuf(sc, i); 969 } 970 sc->sc_rxhead = 0; 971 972 /* turn off flow control */ 973 cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0); 974 975 /* align layer 3 header to 32-bit */ 976 cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, ETHER_ALIGN); 977 978 /* Clear all interrupt Masks */ 979 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF); 980 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF); 981 982 /* Enable TX & RX DMA */ 983 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1); 984 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1); 985 986 /* Enable TX and RX interrupt receive for core 0 */ 987 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 1); 988 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 1); 989 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F); 990 991 /* Enable host Error Interrupt */ 992 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 2); 993 994 /* Enable interrupts for TX and RX Channel 0 */ 995 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1); 996 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 1); 997 998 /* Ack stalled irqs */ 999 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH); 1000 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX); 1001 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX); 1002 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC); 1003 1004 /* Initialize MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */ 1005 /* TODO Calculate MDCLK=CLK/(CLKDIV+1) */ 1006 cpsw_write_4(sc, MDIOCONTROL, 1007 MDIOCTL_ENABLE | MDIOCTL_FAULTENB | MDIOCTL_CLKDIV(0xff)); 1008 1009 mii_mediachg(mii); 1010 1011 /* Write channel 0 RX HDP */ 1012 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(0), cpsw_rxdesc_paddr(sc, 0)); 1013 sc->sc_rxrun = true; 1014 sc->sc_rxeoq = false; 1015 1016 sc->sc_txrun = true; 1017 sc->sc_txeoq = true; 1018 callout_schedule(&sc->sc_tick_ch, hz); 1019 ifp->if_flags |= IFF_RUNNING; 1020 ifp->if_flags &= ~IFF_OACTIVE; 1021 1022 return 0; 1023 } 1024 1025 static void 1026 cpsw_stop(struct ifnet *ifp, int disable) 1027 { 1028 struct cpsw_softc * const sc = ifp->if_softc; 1029 struct cpsw_ring_data * const rdp = sc->sc_rdp; 1030 u_int i; 1031 1032 aprint_debug_dev(sc->sc_dev, "%s: ifp %p disable %d\n", __func__, 1033 ifp, disable); 1034 1035 if ((ifp->if_flags & IFF_RUNNING) == 0) 1036 return; 1037 1038 callout_stop(&sc->sc_tick_ch); 1039 mii_down(&sc->sc_mii); 1040 1041 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 1); 1042 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 1); 1043 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0x0); 1044 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0x0); 1045 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x0); 1046 1047 cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0); 1048 cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0); 1049 i = 0; 1050 while ((sc->sc_txrun || sc->sc_rxrun) && i < 10000) { 1051 delay(10); 1052 if ((sc->sc_txrun == true) && cpsw_txintr(sc) == 0) 1053 sc->sc_txrun = false; 1054 if ((sc->sc_rxrun == true) && cpsw_rxintr(sc) == 0) 1055 sc->sc_rxrun = false; 1056 i++; 1057 } 1058 //printf("%s toredown complete in %u\n", __func__, i); 1059 1060 /* Reset wrapper */ 1061 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 1062 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 1063 ; 1064 1065 /* Reset SS */ 1066 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 1067 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 1068 ; 1069 1070 for (i = 0; i < CPSW_ETH_PORTS; i++) { 1071 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 1072 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 1073 ; 1074 } 1075 1076 /* Reset CPDMA */ 1077 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 1078 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 1079 ; 1080 1081 /* Release any queued transmit buffers. */ 1082 for (i = 0; i < CPSW_NTXDESCS; i++) { 1083 bus_dmamap_unload(sc->sc_bdt, rdp->tx_dm[i]); 1084 m_freem(rdp->tx_mb[i]); 1085 rdp->tx_mb[i] = NULL; 1086 } 1087 1088 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1089 ifp->if_timer = 0; 1090 1091 if (!disable) 1092 return; 1093 1094 for (i = 0; i < CPSW_NRXDESCS; i++) { 1095 bus_dmamap_unload(sc->sc_bdt, rdp->rx_dm[i]); 1096 m_freem(rdp->rx_mb[i]); 1097 rdp->rx_mb[i] = NULL; 1098 } 1099 } 1100 1101 static void 1102 cpsw_tick(void *arg) 1103 { 1104 struct cpsw_softc * const sc = arg; 1105 struct mii_data * const mii = &sc->sc_mii; 1106 const int s = splnet(); 1107 1108 mii_tick(mii); 1109 1110 splx(s); 1111 1112 callout_schedule(&sc->sc_tick_ch, hz); 1113 } 1114 1115 static int 1116 cpsw_rxthintr(void *arg) 1117 { 1118 struct cpsw_softc * const sc = arg; 1119 1120 /* this won't deassert the interrupt though */ 1121 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH); 1122 1123 return 1; 1124 } 1125 1126 static int 1127 cpsw_rxintr(void *arg) 1128 { 1129 struct cpsw_softc * const sc = arg; 1130 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1131 struct cpsw_ring_data * const rdp = sc->sc_rdp; 1132 struct cpsw_cpdma_bd bd; 1133 const uint32_t * const dw = bd.word; 1134 bus_dmamap_t dm; 1135 struct mbuf *m; 1136 u_int i; 1137 u_int len, off; 1138 1139 KERNHIST_FUNC(__func__); 1140 CPSWHIST_CALLARGS(sc, 0, 0, 0); 1141 1142 for (;;) { 1143 KASSERT(sc->sc_rxhead < CPSW_NRXDESCS); 1144 1145 i = sc->sc_rxhead; 1146 KERNHIST_LOG(cpswhist, "rxhead %x CP %x\n", i, 1147 cpsw_read_4(sc, CPSW_CPDMA_RX_CP(0)), 0, 0); 1148 dm = rdp->rx_dm[i]; 1149 m = rdp->rx_mb[i]; 1150 1151 KASSERT(dm != NULL); 1152 KASSERT(m != NULL); 1153 1154 cpsw_get_rxdesc(sc, i, &bd); 1155 1156 if (ISSET(dw[3], CPDMA_BD_OWNER)) 1157 break; 1158 1159 if (ISSET(dw[3], CPDMA_BD_TDOWNCMPLT)) { 1160 sc->sc_rxrun = false; 1161 return 1; 1162 } 1163 1164 #if defined(CPSW_DEBUG_DMA) 1165 if ((dw[3] & (CPDMA_BD_SOP | CPDMA_BD_EOP)) != 1166 (CPDMA_BD_SOP | CPDMA_BD_EOP)) { 1167 Debugger(); 1168 } 1169 #endif 1170 1171 bus_dmamap_sync(sc->sc_bdt, dm, 0, dm->dm_mapsize, 1172 BUS_DMASYNC_POSTREAD); 1173 1174 if (cpsw_new_rxbuf(sc, i) != 0) { 1175 /* drop current packet, reuse buffer for new */ 1176 ifp->if_ierrors++; 1177 goto next; 1178 } 1179 1180 off = __SHIFTOUT(dw[2], (uint32_t)__BITS(26, 16)); 1181 len = __SHIFTOUT(dw[3], (uint32_t)__BITS(10, 0)); 1182 1183 if (ISSET(dw[3], CPDMA_BD_PASSCRC)) 1184 len -= ETHER_CRC_LEN; 1185 1186 m_set_rcvif(m, ifp); 1187 m->m_pkthdr.len = m->m_len = len; 1188 m->m_data += off; 1189 1190 if_percpuq_enqueue(ifp->if_percpuq, m); 1191 1192 next: 1193 sc->sc_rxhead = RXDESC_NEXT(sc->sc_rxhead); 1194 if (ISSET(dw[3], CPDMA_BD_EOQ)) { 1195 sc->sc_rxeoq = true; 1196 break; 1197 } else { 1198 sc->sc_rxeoq = false; 1199 } 1200 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(0), 1201 cpsw_rxdesc_paddr(sc, i)); 1202 } 1203 1204 #if defined(CPSW_DEBUG_DMA) 1205 if (sc->sc_rxeoq) { 1206 device_printf(sc->sc_dev, "rxeoq\n"); 1207 Debugger(); 1208 } 1209 #endif 1210 1211 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX); 1212 1213 return 1; 1214 } 1215 1216 static int 1217 cpsw_txintr(void *arg) 1218 { 1219 struct cpsw_softc * const sc = arg; 1220 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1221 struct cpsw_ring_data * const rdp = sc->sc_rdp; 1222 struct cpsw_cpdma_bd bd; 1223 const uint32_t * const dw = bd.word; 1224 bool handled = false; 1225 uint32_t tx0_cp; 1226 u_int cpi; 1227 1228 KERNHIST_FUNC(__func__); 1229 CPSWHIST_CALLARGS(sc, 0, 0, 0); 1230 1231 KASSERT(sc->sc_txrun); 1232 1233 KERNHIST_LOG(cpswhist, "before txnext %x txhead %x txrun %x\n", 1234 sc->sc_txnext, sc->sc_txhead, sc->sc_txrun, 0); 1235 1236 tx0_cp = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)); 1237 1238 if (tx0_cp == 0xfffffffc) { 1239 /* Teardown, ack it */ 1240 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(0), 0xfffffffc); 1241 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 0); 1242 sc->sc_txrun = false; 1243 return 0; 1244 } 1245 1246 for (;;) { 1247 tx0_cp = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)); 1248 cpi = (tx0_cp - sc->sc_txdescs_pa) / sizeof(struct cpsw_cpdma_bd); 1249 KASSERT(sc->sc_txhead < CPSW_NTXDESCS); 1250 1251 KERNHIST_LOG(cpswhist, "txnext %x txhead %x txrun %x cpi %x\n", 1252 sc->sc_txnext, sc->sc_txhead, sc->sc_txrun, cpi); 1253 1254 cpsw_get_txdesc(sc, sc->sc_txhead, &bd); 1255 1256 #if defined(CPSW_DEBUG_DMA) 1257 if (dw[2] == 0) { 1258 //Debugger(); 1259 } 1260 #endif 1261 1262 if (ISSET(dw[3], CPDMA_BD_SOP) == 0) 1263 goto next; 1264 1265 if (ISSET(dw[3], CPDMA_BD_OWNER)) { 1266 printf("pwned %x %x %x\n", cpi, sc->sc_txhead, 1267 sc->sc_txnext); 1268 break; 1269 } 1270 1271 if (ISSET(dw[3], CPDMA_BD_TDOWNCMPLT)) { 1272 sc->sc_txrun = false; 1273 return 1; 1274 } 1275 1276 bus_dmamap_sync(sc->sc_bdt, rdp->tx_dm[sc->sc_txhead], 1277 0, rdp->tx_dm[sc->sc_txhead]->dm_mapsize, 1278 BUS_DMASYNC_POSTWRITE); 1279 bus_dmamap_unload(sc->sc_bdt, rdp->tx_dm[sc->sc_txhead]); 1280 1281 m_freem(rdp->tx_mb[sc->sc_txhead]); 1282 rdp->tx_mb[sc->sc_txhead] = NULL; 1283 1284 ifp->if_opackets++; 1285 1286 handled = true; 1287 1288 ifp->if_flags &= ~IFF_OACTIVE; 1289 1290 next: 1291 if (ISSET(dw[3], CPDMA_BD_EOP) && ISSET(dw[3], CPDMA_BD_EOQ)) { 1292 sc->sc_txeoq = true; 1293 } 1294 if (sc->sc_txhead == cpi) { 1295 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(0), 1296 cpsw_txdesc_paddr(sc, cpi)); 1297 sc->sc_txhead = TXDESC_NEXT(sc->sc_txhead); 1298 break; 1299 } 1300 sc->sc_txhead = TXDESC_NEXT(sc->sc_txhead); 1301 if (ISSET(dw[3], CPDMA_BD_EOP) && ISSET(dw[3], CPDMA_BD_EOQ)) { 1302 sc->sc_txeoq = true; 1303 break; 1304 } 1305 } 1306 1307 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX); 1308 1309 if ((sc->sc_txnext != sc->sc_txhead) && sc->sc_txeoq) { 1310 if (cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)) == 0) { 1311 sc->sc_txeoq = false; 1312 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 1313 cpsw_txdesc_paddr(sc, sc->sc_txhead)); 1314 } 1315 } 1316 1317 KERNHIST_LOG(cpswhist, "after txnext %x txhead %x txrun %x\n", 1318 sc->sc_txnext, sc->sc_txhead, sc->sc_txrun, 0); 1319 KERNHIST_LOG(cpswhist, "CP %x HDP %x\n", 1320 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)), 1321 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)), 0, 0); 1322 1323 if (handled && sc->sc_txnext == sc->sc_txhead) 1324 ifp->if_timer = 0; 1325 1326 if (handled) 1327 if_schedule_deferred_start(ifp); 1328 1329 return handled; 1330 } 1331 1332 static int 1333 cpsw_miscintr(void *arg) 1334 { 1335 struct cpsw_softc * const sc = arg; 1336 uint32_t miscstat; 1337 uint32_t dmastat; 1338 uint32_t stat; 1339 1340 miscstat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0)); 1341 device_printf(sc->sc_dev, "%s %x FIRE\n", __func__, miscstat); 1342 1343 #define CPSW_MISC_HOST_PEND __BIT32(2) 1344 #define CPSW_MISC_STAT_PEND __BIT32(3) 1345 1346 if (ISSET(miscstat, CPSW_MISC_HOST_PEND)) { 1347 /* Host Error */ 1348 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 1349 printf("CPSW_CPDMA_DMA_INTSTAT_MASKED %x\n", dmastat); 1350 1351 printf("rxhead %02x\n", sc->sc_rxhead); 1352 1353 stat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS); 1354 printf("CPSW_CPDMA_DMASTATUS %x\n", stat); 1355 stat = cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)); 1356 printf("CPSW_CPDMA_TX0_HDP %x\n", stat); 1357 stat = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)); 1358 printf("CPSW_CPDMA_TX0_CP %x\n", stat); 1359 stat = cpsw_read_4(sc, CPSW_CPDMA_RX_HDP(0)); 1360 printf("CPSW_CPDMA_RX0_HDP %x\n", stat); 1361 stat = cpsw_read_4(sc, CPSW_CPDMA_RX_CP(0)); 1362 printf("CPSW_CPDMA_RX0_CP %x\n", stat); 1363 1364 //Debugger(); 1365 1366 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, dmastat); 1367 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 1368 printf("CPSW_CPDMA_DMA_INTSTAT_MASKED %x\n", dmastat); 1369 } 1370 1371 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC); 1372 1373 return 1; 1374 } 1375 1376 /* 1377 * 1378 * ALE support routines. 1379 * 1380 */ 1381 1382 static void 1383 cpsw_ale_entry_init(uint32_t *ale_entry) 1384 { 1385 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 1386 } 1387 1388 static void 1389 cpsw_ale_entry_set_mac(uint32_t *ale_entry, const uint8_t *mac) 1390 { 1391 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 1392 ale_entry[1] = mac[0] << 8 | mac[1]; 1393 } 1394 1395 static void 1396 cpsw_ale_entry_set_bcast_mac(uint32_t *ale_entry) 1397 { 1398 ale_entry[0] = 0xffffffff; 1399 ale_entry[1] = 0x0000ffff; 1400 } 1401 1402 static void 1403 cpsw_ale_entry_set(uint32_t *ale_entry, ale_entry_field_t field, uint32_t val) 1404 { 1405 /* Entry type[61:60] is addr entry(1), Mcast fwd state[63:62] is fw(3)*/ 1406 switch (field) { 1407 case ALE_ENTRY_TYPE: 1408 /* [61:60] */ 1409 ale_entry[1] |= (val & 0x3) << 28; 1410 break; 1411 case ALE_MCAST_FWD_STATE: 1412 /* [63:62] */ 1413 ale_entry[1] |= (val & 0x3) << 30; 1414 break; 1415 case ALE_PORT_MASK: 1416 /* [68:66] */ 1417 ale_entry[2] |= (val & 0x7) << 2; 1418 break; 1419 case ALE_PORT_NUMBER: 1420 /* [67:66] */ 1421 ale_entry[2] |= (val & 0x3) << 2; 1422 break; 1423 default: 1424 panic("Invalid ALE entry field: %d\n", field); 1425 } 1426 1427 return; 1428 } 1429 1430 static bool 1431 cpsw_ale_entry_mac_match(const uint32_t *ale_entry, const uint8_t *mac) 1432 { 1433 return (((ale_entry[1] >> 8) & 0xff) == mac[0]) && 1434 (((ale_entry[1] >> 0) & 0xff) == mac[1]) && 1435 (((ale_entry[0] >>24) & 0xff) == mac[2]) && 1436 (((ale_entry[0] >>16) & 0xff) == mac[3]) && 1437 (((ale_entry[0] >> 8) & 0xff) == mac[4]) && 1438 (((ale_entry[0] >> 0) & 0xff) == mac[5]); 1439 } 1440 1441 static void 1442 cpsw_ale_set_outgoing_mac(struct cpsw_softc *sc, int port, const uint8_t *mac) 1443 { 1444 cpsw_write_4(sc, CPSW_PORT_P_SA_HI(port), 1445 mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]); 1446 cpsw_write_4(sc, CPSW_PORT_P_SA_LO(port), 1447 mac[5] << 8 | mac[4]); 1448 } 1449 1450 static void 1451 cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 1452 { 1453 cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023); 1454 ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0); 1455 ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1); 1456 ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2); 1457 } 1458 1459 static void 1460 cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, 1461 const uint32_t *ale_entry) 1462 { 1463 cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]); 1464 cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]); 1465 cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]); 1466 cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023)); 1467 } 1468 1469 static int 1470 cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc) 1471 { 1472 int i; 1473 uint32_t ale_entry[3]; 1474 1475 /* First two entries are link address and broadcast. */ 1476 for (i = 2; i < CPSW_MAX_ALE_ENTRIES; i++) { 1477 cpsw_ale_read_entry(sc, i, ale_entry); 1478 if (((ale_entry[1] >> 28) & 3) == 1 && /* Address entry */ 1479 ((ale_entry[1] >> 8) & 1) == 1) { /* MCast link addr */ 1480 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 1481 cpsw_ale_write_entry(sc, i, ale_entry); 1482 } 1483 } 1484 return CPSW_MAX_ALE_ENTRIES; 1485 } 1486 1487 static int 1488 cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmask, uint8_t *mac) 1489 { 1490 int free_index = -1, matching_index = -1, i; 1491 uint32_t ale_entry[3]; 1492 1493 /* Find a matching entry or a free entry. */ 1494 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 1495 cpsw_ale_read_entry(sc, i, ale_entry); 1496 1497 /* Entry Type[61:60] is 0 for free entry */ 1498 if (free_index < 0 && ((ale_entry[1] >> 28) & 3) == 0) { 1499 free_index = i; 1500 } 1501 1502 if (cpsw_ale_entry_mac_match(ale_entry, mac)) { 1503 matching_index = i; 1504 break; 1505 } 1506 } 1507 1508 if (matching_index < 0) { 1509 if (free_index < 0) 1510 return ENOMEM; 1511 i = free_index; 1512 } 1513 1514 cpsw_ale_entry_init(ale_entry); 1515 1516 cpsw_ale_entry_set_mac(ale_entry, mac); 1517 cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS); 1518 cpsw_ale_entry_set(ale_entry, ALE_MCAST_FWD_STATE, ALE_FWSTATE_FWONLY); 1519 cpsw_ale_entry_set(ale_entry, ALE_PORT_MASK, portmask); 1520 1521 cpsw_ale_write_entry(sc, i, ale_entry); 1522 1523 return 0; 1524 } 1525 1526 static int 1527 cpsw_ale_update_addresses(struct cpsw_softc *sc, int purge) 1528 { 1529 uint8_t *mac = sc->sc_enaddr; 1530 uint32_t ale_entry[3]; 1531 int i; 1532 struct ethercom * const ec = &sc->sc_ec; 1533 struct ether_multi *ifma; 1534 1535 cpsw_ale_entry_init(ale_entry); 1536 /* Route incoming packets for our MAC address to Port 0 (host). */ 1537 /* For simplicity, keep this entry at table index 0 in the ALE. */ 1538 cpsw_ale_entry_set_mac(ale_entry, mac); 1539 cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS); 1540 cpsw_ale_entry_set(ale_entry, ALE_PORT_NUMBER, 0); 1541 cpsw_ale_write_entry(sc, 0, ale_entry); 1542 1543 /* Set outgoing MAC Address for Ports 1 and 2. */ 1544 for (i = CPSW_CPPI_PORTS; i < (CPSW_ETH_PORTS + CPSW_CPPI_PORTS); ++i) 1545 cpsw_ale_set_outgoing_mac(sc, i, mac); 1546 1547 /* Keep the broadcast address at table entry 1. */ 1548 cpsw_ale_entry_init(ale_entry); 1549 cpsw_ale_entry_set_bcast_mac(ale_entry); 1550 cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS); 1551 cpsw_ale_entry_set(ale_entry, ALE_MCAST_FWD_STATE, ALE_FWSTATE_FWONLY); 1552 cpsw_ale_entry_set(ale_entry, ALE_PORT_MASK, ALE_PORT_MASK_ALL); 1553 cpsw_ale_write_entry(sc, 1, ale_entry); 1554 1555 /* SIOCDELMULTI doesn't specify the particular address 1556 being removed, so we have to remove all and rebuild. */ 1557 if (purge) 1558 cpsw_ale_remove_all_mc_entries(sc); 1559 1560 /* Set other multicast addrs desired. */ 1561 ETHER_LOCK(ec); 1562 LIST_FOREACH(ifma, &ec->ec_multiaddrs, enm_list) { 1563 cpsw_ale_mc_entry_set(sc, ALE_PORT_MASK_ALL, ifma->enm_addrlo); 1564 } 1565 ETHER_UNLOCK(ec); 1566 1567 return 0; 1568 } 1569
Indexes created Wed Oct 22 00:09:40 GMT 2025