if_cpsw.c revision 1.7
1 /* $NetBSD: if_cpsw.c,v 1.7 2019/10/27 23:25:38 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 2012 Damjan Marion <dmarion (at) Freebsd.org> 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 43 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 46 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 48 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 52 * SUCH DAMAGE. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.7 2019/10/27 23:25:38 jmcneill Exp $"); 57 58 #include <sys/param.h> 59 #include <sys/bus.h> 60 #include <sys/device.h> 61 #include <sys/ioctl.h> 62 #include <sys/intr.h> 63 #include <sys/kmem.h> 64 #include <sys/mutex.h> 65 #include <sys/systm.h> 66 #include <sys/kernel.h> 67 68 #include <net/if.h> 69 #include <net/if_ether.h> 70 #include <net/if_media.h> 71 #include <net/bpf.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #if 0 77 #include <arch/arm/omap/omap2_obiovar.h> 78 #else 79 #include <dev/fdt/fdtvar.h> 80 #endif 81 #include <arch/arm/omap/if_cpswreg.h> 82 #include <arch/arm/omap/sitara_cmreg.h> 83 #include <arch/arm/omap/sitara_cm.h> 84 85 #define CPSW_TXFRAGS 16 86 87 #define CPSW_CPPI_RAM_SIZE (0x2000) 88 #define CPSW_CPPI_RAM_TXDESCS_SIZE (CPSW_CPPI_RAM_SIZE/2) 89 #define CPSW_CPPI_RAM_RXDESCS_SIZE \ 90 (CPSW_CPPI_RAM_SIZE - CPSW_CPPI_RAM_TXDESCS_SIZE) 91 #define CPSW_CPPI_RAM_TXDESCS_BASE (CPSW_CPPI_RAM_OFFSET + 0x0000) 92 #define CPSW_CPPI_RAM_RXDESCS_BASE \ 93 (CPSW_CPPI_RAM_OFFSET + CPSW_CPPI_RAM_TXDESCS_SIZE) 94 95 #define CPSW_NTXDESCS (CPSW_CPPI_RAM_TXDESCS_SIZE/sizeof(struct cpsw_cpdma_bd)) 96 #define CPSW_NRXDESCS (CPSW_CPPI_RAM_RXDESCS_SIZE/sizeof(struct cpsw_cpdma_bd)) 97 98 CTASSERT(powerof2(CPSW_NTXDESCS)); 99 CTASSERT(powerof2(CPSW_NRXDESCS)); 100 101 #define CPSW_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 102 103 #define TXDESC_NEXT(x) cpsw_txdesc_adjust((x), 1) 104 #define TXDESC_PREV(x) cpsw_txdesc_adjust((x), -1) 105 106 #define RXDESC_NEXT(x) cpsw_rxdesc_adjust((x), 1) 107 #define RXDESC_PREV(x) cpsw_rxdesc_adjust((x), -1) 108 109 struct cpsw_ring_data { 110 bus_dmamap_t tx_dm[CPSW_NTXDESCS]; 111 struct mbuf *tx_mb[CPSW_NTXDESCS]; 112 bus_dmamap_t rx_dm[CPSW_NRXDESCS]; 113 struct mbuf *rx_mb[CPSW_NRXDESCS]; 114 }; 115 116 struct cpsw_softc { 117 device_t sc_dev; 118 bus_space_tag_t sc_bst; 119 bus_space_handle_t sc_bsh; 120 bus_size_t sc_bss; 121 bus_dma_tag_t sc_bdt; 122 bus_space_handle_t sc_bsh_txdescs; 123 bus_space_handle_t sc_bsh_rxdescs; 124 bus_addr_t sc_txdescs_pa; 125 bus_addr_t sc_rxdescs_pa; 126 struct ethercom sc_ec; 127 struct mii_data sc_mii; 128 bool sc_phy_has_1000t; 129 bool sc_attached; 130 callout_t sc_tick_ch; 131 void *sc_ih; 132 struct cpsw_ring_data *sc_rdp; 133 volatile u_int sc_txnext; 134 volatile u_int sc_txhead; 135 volatile u_int sc_rxhead; 136 void *sc_rxthih; 137 void *sc_rxih; 138 void *sc_txih; 139 void *sc_miscih; 140 void *sc_txpad; 141 bus_dmamap_t sc_txpad_dm; 142 #define sc_txpad_pa sc_txpad_dm->dm_segs[0].ds_addr 143 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 144 volatile bool sc_txrun; 145 volatile bool sc_rxrun; 146 volatile bool sc_txeoq; 147 volatile bool sc_rxeoq; 148 }; 149 150 static int cpsw_match(device_t, cfdata_t, void *); 151 static void cpsw_attach(device_t, device_t, void *); 152 static int cpsw_detach(device_t, int); 153 154 static void cpsw_start(struct ifnet *); 155 static int cpsw_ioctl(struct ifnet *, u_long, void *); 156 static void cpsw_watchdog(struct ifnet *); 157 static int cpsw_init(struct ifnet *); 158 static void cpsw_stop(struct ifnet *, int); 159 160 static int cpsw_mii_readreg(device_t, int, int, uint16_t *); 161 static int cpsw_mii_writereg(device_t, int, int, uint16_t); 162 static void cpsw_mii_statchg(struct ifnet *); 163 164 static int cpsw_new_rxbuf(struct cpsw_softc * const, const u_int); 165 static void cpsw_tick(void *); 166 167 static int cpsw_rxthintr(void *); 168 static int cpsw_rxintr(void *); 169 static int cpsw_txintr(void *); 170 static int cpsw_miscintr(void *); 171 172 /* ALE support */ 173 #define CPSW_MAX_ALE_ENTRIES 1024 174 175 static int cpsw_ale_update_addresses(struct cpsw_softc *, int purge); 176 177 CFATTACH_DECL_NEW(cpsw, sizeof(struct cpsw_softc), 178 cpsw_match, cpsw_attach, cpsw_detach, NULL); 179 180 #undef KERNHIST 181 #include <sys/kernhist.h> 182 KERNHIST_DEFINE(cpswhist); 183 184 #ifdef KERNHIST 185 #define KERNHIST_CALLED_5(NAME, i, j, k, l) \ 186 do { \ 187 _kernhist_call = atomic_inc_uint_nv(&_kernhist_cnt); \ 188 KERNHIST_LOG(NAME, "called! %x %x %x %x", i, j, k, l); \ 189 } while (/*CONSTCOND*/ 0) 190 #else 191 #define KERNHIST_CALLED_5(NAME, i, j, k, l) 192 #endif 193 194 static inline u_int 195 cpsw_txdesc_adjust(u_int x, int y) 196 { 197 return (((x) + y) & (CPSW_NTXDESCS - 1)); 198 } 199 200 static inline u_int 201 cpsw_rxdesc_adjust(u_int x, int y) 202 { 203 return (((x) + y) & (CPSW_NRXDESCS - 1)); 204 } 205 206 static inline uint32_t 207 cpsw_read_4(struct cpsw_softc * const sc, bus_size_t const offset) 208 { 209 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, offset); 210 } 211 212 static inline void 213 cpsw_write_4(struct cpsw_softc * const sc, bus_size_t const offset, 214 uint32_t const value) 215 { 216 bus_space_write_4(sc->sc_bst, sc->sc_bsh, offset, value); 217 } 218 219 static inline void 220 cpsw_set_txdesc_next(struct cpsw_softc * const sc, const u_int i, uint32_t n) 221 { 222 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i + 0; 223 224 KERNHIST_FUNC(__func__); 225 KERNHIST_CALLED_5(cpswhist, sc, i, n, 0); 226 227 bus_space_write_4(sc->sc_bst, sc->sc_bsh_txdescs, o, n); 228 } 229 230 static inline void 231 cpsw_set_rxdesc_next(struct cpsw_softc * const sc, const u_int i, uint32_t n) 232 { 233 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i + 0; 234 235 KERNHIST_FUNC(__func__); 236 KERNHIST_CALLED_5(cpswhist, sc, i, n, 0); 237 238 bus_space_write_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, n); 239 } 240 241 static inline void 242 cpsw_get_txdesc(struct cpsw_softc * const sc, const u_int i, 243 struct cpsw_cpdma_bd * const bdp) 244 { 245 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 246 uint32_t * const dp = bdp->word; 247 const bus_size_t c = __arraycount(bdp->word); 248 249 KERNHIST_FUNC(__func__); 250 KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0); 251 252 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh_txdescs, o, dp, c); 253 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 254 dp[0], dp[1], dp[2], dp[3]); 255 } 256 257 static inline void 258 cpsw_set_txdesc(struct cpsw_softc * const sc, const u_int i, 259 struct cpsw_cpdma_bd * const bdp) 260 { 261 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 262 uint32_t * const dp = bdp->word; 263 const bus_size_t c = __arraycount(bdp->word); 264 265 KERNHIST_FUNC(__func__); 266 KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0); 267 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 268 dp[0], dp[1], dp[2], dp[3]); 269 270 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh_txdescs, o, dp, c); 271 } 272 273 static inline void 274 cpsw_get_rxdesc(struct cpsw_softc * const sc, const u_int i, 275 struct cpsw_cpdma_bd * const bdp) 276 { 277 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 278 uint32_t * const dp = bdp->word; 279 const bus_size_t c = __arraycount(bdp->word); 280 281 KERNHIST_FUNC(__func__); 282 KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0); 283 284 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, dp, c); 285 286 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 287 dp[0], dp[1], dp[2], dp[3]); 288 } 289 290 static inline void 291 cpsw_set_rxdesc(struct cpsw_softc * const sc, const u_int i, 292 struct cpsw_cpdma_bd * const bdp) 293 { 294 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 295 uint32_t * const dp = bdp->word; 296 const bus_size_t c = __arraycount(bdp->word); 297 298 KERNHIST_FUNC(__func__); 299 KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0); 300 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 301 dp[0], dp[1], dp[2], dp[3]); 302 303 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, dp, c); 304 } 305 306 static inline bus_addr_t 307 cpsw_txdesc_paddr(struct cpsw_softc * const sc, u_int x) 308 { 309 KASSERT(x < CPSW_NTXDESCS); 310 return sc->sc_txdescs_pa + sizeof(struct cpsw_cpdma_bd) * x; 311 } 312 313 static inline bus_addr_t 314 cpsw_rxdesc_paddr(struct cpsw_softc * const sc, u_int x) 315 { 316 KASSERT(x < CPSW_NRXDESCS); 317 return sc->sc_rxdescs_pa + sizeof(struct cpsw_cpdma_bd) * x; 318 } 319 320 321 static int 322 cpsw_match(device_t parent, cfdata_t cf, void *aux) 323 { 324 struct fdt_attach_args * const faa = aux; 325 326 static const char * const compatible[] = { 327 "ti,am335x-cpsw", 328 "ti,cpsw", 329 NULL 330 }; 331 332 return of_match_compatible(faa->faa_phandle, compatible); 333 } 334 335 static bool 336 cpsw_phy_has_1000t(struct cpsw_softc * const sc) 337 { 338 struct ifmedia_entry *ifm; 339 340 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 341 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T) 342 return true; 343 } 344 return false; 345 } 346 347 static int 348 cpsw_detach(device_t self, int flags) 349 { 350 struct cpsw_softc * const sc = device_private(self); 351 struct ifnet *ifp = &sc->sc_ec.ec_if; 352 u_int i; 353 354 /* Succeed now if there's no work to do. */ 355 if (!sc->sc_attached) 356 return 0; 357 358 sc->sc_attached = false; 359 360 /* Stop the interface. Callouts are stopped in it. */ 361 cpsw_stop(ifp, 1); 362 363 /* Destroy our callout. */ 364 callout_destroy(&sc->sc_tick_ch); 365 366 /* Let go of the interrupts */ 367 intr_disestablish(sc->sc_rxthih); 368 intr_disestablish(sc->sc_rxih); 369 intr_disestablish(sc->sc_txih); 370 intr_disestablish(sc->sc_miscih); 371 372 /* Delete all media. */ 373 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 374 375 ether_ifdetach(ifp); 376 if_detach(ifp); 377 378 /* Free the packet padding buffer */ 379 kmem_free(sc->sc_txpad, ETHER_MIN_LEN); 380 bus_dmamap_destroy(sc->sc_bdt, sc->sc_txpad_dm); 381 382 /* Destroy all the descriptors */ 383 for (i = 0; i < CPSW_NTXDESCS; i++) 384 bus_dmamap_destroy(sc->sc_bdt, sc->sc_rdp->tx_dm[i]); 385 for (i = 0; i < CPSW_NRXDESCS; i++) 386 bus_dmamap_destroy(sc->sc_bdt, sc->sc_rdp->rx_dm[i]); 387 kmem_free(sc->sc_rdp, sizeof(*sc->sc_rdp)); 388 389 /* Unmap */ 390 bus_space_unmap(sc->sc_bst, sc->sc_bsh, sc->sc_bss); 391 392 393 return 0; 394 } 395 396 static void 397 cpsw_attach(device_t parent, device_t self, void *aux) 398 { 399 struct fdt_attach_args * const faa = aux; 400 struct cpsw_softc * const sc = device_private(self); 401 struct ethercom * const ec = &sc->sc_ec; 402 struct ifnet * const ifp = &ec->ec_if; 403 struct mii_data * const mii = &sc->sc_mii; 404 const int phandle = faa->faa_phandle; 405 const uint8_t *macaddr; 406 bus_addr_t addr; 407 bus_size_t size; 408 int error, slave, len; 409 u_int i; 410 411 KERNHIST_INIT(cpswhist, 4096); 412 413 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 414 aprint_error(": couldn't get registers\n"); 415 return; 416 } 417 418 sc->sc_dev = self; 419 420 aprint_normal(": TI Layer 2 3-Port Switch\n"); 421 aprint_naive("\n"); 422 423 callout_init(&sc->sc_tick_ch, 0); 424 callout_setfunc(&sc->sc_tick_ch, cpsw_tick, sc); 425 426 macaddr = NULL; 427 slave = of_find_firstchild_byname(phandle, "slave"); 428 if (slave > 0) { 429 macaddr = fdtbus_get_prop(slave, "mac-address", &len); 430 if (len != ETHER_ADDR_LEN) 431 macaddr = NULL; 432 } 433 if (macaddr == NULL) { 434 #if 0 435 /* grab mac_id0 from AM335x control module */ 436 uint32_t reg_lo, reg_hi; 437 438 if (sitara_cm_reg_read_4(OMAP2SCM_MAC_ID0_LO, ®_lo) == 0 && 439 sitara_cm_reg_read_4(OMAP2SCM_MAC_ID0_HI, ®_hi) == 0) { 440 sc->sc_enaddr[0] = (reg_hi >> 0) & 0xff; 441 sc->sc_enaddr[1] = (reg_hi >> 8) & 0xff; 442 sc->sc_enaddr[2] = (reg_hi >> 16) & 0xff; 443 sc->sc_enaddr[3] = (reg_hi >> 24) & 0xff; 444 sc->sc_enaddr[4] = (reg_lo >> 0) & 0xff; 445 sc->sc_enaddr[5] = (reg_lo >> 8) & 0xff; 446 } else 447 #endif 448 { 449 aprint_error_dev(sc->sc_dev, 450 "using fake station address\n"); 451 /* 'N' happens to have the Local bit set */ 452 #if 0 453 sc->sc_enaddr[0] = 'N'; 454 sc->sc_enaddr[1] = 'e'; 455 sc->sc_enaddr[2] = 't'; 456 sc->sc_enaddr[3] = 'B'; 457 sc->sc_enaddr[4] = 'S'; 458 sc->sc_enaddr[5] = 'D'; 459 #else 460 /* XXX Glor */ 461 sc->sc_enaddr[0] = 0xd4; 462 sc->sc_enaddr[1] = 0x94; 463 sc->sc_enaddr[2] = 0xa1; 464 sc->sc_enaddr[3] = 0x97; 465 sc->sc_enaddr[4] = 0x03; 466 sc->sc_enaddr[5] = 0x94; 467 #endif 468 } 469 } else { 470 memcpy(sc->sc_enaddr, macaddr, ETHER_ADDR_LEN); 471 } 472 473 #if 0 474 sc->sc_rxthih = intr_establish(oa->obio_intrbase + CPSW_INTROFF_RXTH, 475 IPL_VM, IST_LEVEL, cpsw_rxthintr, sc); 476 sc->sc_rxih = intr_establish(oa->obio_intrbase + CPSW_INTROFF_RX, 477 IPL_VM, IST_LEVEL, cpsw_rxintr, sc); 478 sc->sc_txih = intr_establish(oa->obio_intrbase + CPSW_INTROFF_TX, 479 IPL_VM, IST_LEVEL, cpsw_txintr, sc); 480 sc->sc_miscih = intr_establish(oa->obio_intrbase + CPSW_INTROFF_MISC, 481 IPL_VM, IST_LEVEL, cpsw_miscintr, sc); 482 #else 483 #define FDT_INTR_FLAGS 0 484 sc->sc_rxthih = fdtbus_intr_establish(phandle, CPSW_INTROFF_RXTH, IPL_VM, FDT_INTR_FLAGS, cpsw_rxthintr, sc); 485 sc->sc_rxih = fdtbus_intr_establish(phandle, CPSW_INTROFF_RX, IPL_VM, FDT_INTR_FLAGS, cpsw_rxintr, sc); 486 sc->sc_txih = fdtbus_intr_establish(phandle, CPSW_INTROFF_TX, IPL_VM, FDT_INTR_FLAGS, cpsw_txintr, sc); 487 sc->sc_miscih = fdtbus_intr_establish(phandle, CPSW_INTROFF_MISC, IPL_VM, FDT_INTR_FLAGS, cpsw_miscintr, sc); 488 #endif 489 490 sc->sc_bst = faa->faa_bst; 491 sc->sc_bss = size; 492 sc->sc_bdt = faa->faa_dmat; 493 494 error = bus_space_map(sc->sc_bst, addr, size, 0, 495 &sc->sc_bsh); 496 if (error) { 497 aprint_error_dev(sc->sc_dev, 498 "can't map registers: %d\n", error); 499 return; 500 } 501 502 sc->sc_txdescs_pa = addr + CPSW_CPPI_RAM_TXDESCS_BASE; 503 error = bus_space_subregion(sc->sc_bst, sc->sc_bsh, 504 CPSW_CPPI_RAM_TXDESCS_BASE, CPSW_CPPI_RAM_TXDESCS_SIZE, 505 &sc->sc_bsh_txdescs); 506 if (error) { 507 aprint_error_dev(sc->sc_dev, 508 "can't subregion tx ring SRAM: %d\n", error); 509 return; 510 } 511 aprint_debug_dev(sc->sc_dev, "txdescs at %p\n", 512 (void *)sc->sc_bsh_txdescs); 513 514 sc->sc_rxdescs_pa = addr + CPSW_CPPI_RAM_RXDESCS_BASE; 515 error = bus_space_subregion(sc->sc_bst, sc->sc_bsh, 516 CPSW_CPPI_RAM_RXDESCS_BASE, CPSW_CPPI_RAM_RXDESCS_SIZE, 517 &sc->sc_bsh_rxdescs); 518 if (error) { 519 aprint_error_dev(sc->sc_dev, 520 "can't subregion rx ring SRAM: %d\n", error); 521 return; 522 } 523 aprint_debug_dev(sc->sc_dev, "rxdescs at %p\n", 524 (void *)sc->sc_bsh_rxdescs); 525 526 sc->sc_rdp = kmem_alloc(sizeof(*sc->sc_rdp), KM_SLEEP); 527 528 for (i = 0; i < CPSW_NTXDESCS; i++) { 529 if ((error = bus_dmamap_create(sc->sc_bdt, MCLBYTES, 530 CPSW_TXFRAGS, MCLBYTES, 0, 0, 531 &sc->sc_rdp->tx_dm[i])) != 0) { 532 aprint_error_dev(sc->sc_dev, 533 "unable to create tx DMA map: %d\n", error); 534 } 535 sc->sc_rdp->tx_mb[i] = NULL; 536 } 537 538 for (i = 0; i < CPSW_NRXDESCS; i++) { 539 if ((error = bus_dmamap_create(sc->sc_bdt, MCLBYTES, 1, 540 MCLBYTES, 0, 0, &sc->sc_rdp->rx_dm[i])) != 0) { 541 aprint_error_dev(sc->sc_dev, 542 "unable to create rx DMA map: %d\n", error); 543 } 544 sc->sc_rdp->rx_mb[i] = NULL; 545 } 546 547 sc->sc_txpad = kmem_zalloc(ETHER_MIN_LEN, KM_SLEEP); 548 bus_dmamap_create(sc->sc_bdt, ETHER_MIN_LEN, 1, ETHER_MIN_LEN, 0, 549 BUS_DMA_WAITOK, &sc->sc_txpad_dm); 550 bus_dmamap_load(sc->sc_bdt, sc->sc_txpad_dm, sc->sc_txpad, 551 ETHER_MIN_LEN, NULL, BUS_DMA_WAITOK | BUS_DMA_WRITE); 552 bus_dmamap_sync(sc->sc_bdt, sc->sc_txpad_dm, 0, ETHER_MIN_LEN, 553 BUS_DMASYNC_PREWRITE); 554 555 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 556 ether_sprintf(sc->sc_enaddr)); 557 558 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 559 ifp->if_softc = sc; 560 ifp->if_capabilities = 0; 561 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 562 ifp->if_start = cpsw_start; 563 ifp->if_ioctl = cpsw_ioctl; 564 ifp->if_init = cpsw_init; 565 ifp->if_stop = cpsw_stop; 566 ifp->if_watchdog = cpsw_watchdog; 567 IFQ_SET_READY(&ifp->if_snd); 568 569 cpsw_stop(ifp, 0); 570 571 mii->mii_ifp = ifp; 572 mii->mii_readreg = cpsw_mii_readreg; 573 mii->mii_writereg = cpsw_mii_writereg; 574 mii->mii_statchg = cpsw_mii_statchg; 575 576 sc->sc_ec.ec_mii = mii; 577 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 578 579 /* Initialize MDIO */ 580 cpsw_write_4(sc, MDIOCONTROL, 581 MDIOCTL_ENABLE | MDIOCTL_FAULTENB | MDIOCTL_CLKDIV(0xff)); 582 /* Clear ALE */ 583 cpsw_write_4(sc, CPSW_ALE_CONTROL, ALECTL_CLEAR_TABLE); 584 585 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 0, 0); 586 if (LIST_FIRST(&mii->mii_phys) == NULL) { 587 aprint_error_dev(self, "no PHY found!\n"); 588 sc->sc_phy_has_1000t = false; 589 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 590 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 591 } else { 592 sc->sc_phy_has_1000t = cpsw_phy_has_1000t(sc); 593 if (sc->sc_phy_has_1000t) { 594 #if 0 595 aprint_normal_dev(sc->sc_dev, "1000baseT PHY found. " 596 "Setting RGMII Mode\n"); 597 /* 598 * Select the Interface RGMII Mode in the Control 599 * Module 600 */ 601 sitara_cm_reg_write_4(CPSW_GMII_SEL, 602 GMIISEL_GMII2_SEL(RGMII_MODE) | 603 GMIISEL_GMII1_SEL(RGMII_MODE)); 604 #endif 605 } 606 607 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 608 } 609 610 if_attach(ifp); 611 if_deferred_start_init(ifp, NULL); 612 ether_ifattach(ifp, sc->sc_enaddr); 613 614 /* The attach is successful. */ 615 sc->sc_attached = true; 616 617 return; 618 } 619 620 static void 621 cpsw_start(struct ifnet *ifp) 622 { 623 struct cpsw_softc * const sc = ifp->if_softc; 624 struct cpsw_ring_data * const rdp = sc->sc_rdp; 625 struct cpsw_cpdma_bd bd; 626 uint32_t * const dw = bd.word; 627 struct mbuf *m; 628 bus_dmamap_t dm; 629 u_int eopi __diagused = ~0; 630 u_int seg; 631 u_int txfree; 632 int txstart = -1; 633 int error; 634 bool pad; 635 u_int mlen; 636 637 KERNHIST_FUNC(__func__); 638 KERNHIST_CALLED_5(cpswhist, sc, 0, 0, 0); 639 640 if (__predict_false((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != 641 IFF_RUNNING)) { 642 return; 643 } 644 645 if (sc->sc_txnext >= sc->sc_txhead) 646 txfree = CPSW_NTXDESCS - 1 + sc->sc_txhead - sc->sc_txnext; 647 else 648 txfree = sc->sc_txhead - sc->sc_txnext - 1; 649 650 KERNHIST_LOG(cpswhist, "start txf %x txh %x txn %x txr %x\n", 651 txfree, sc->sc_txhead, sc->sc_txnext, sc->sc_txrun); 652 653 while (txfree > 0) { 654 IFQ_POLL(&ifp->if_snd, m); 655 if (m == NULL) 656 break; 657 658 dm = rdp->tx_dm[sc->sc_txnext]; 659 660 error = bus_dmamap_load_mbuf(sc->sc_bdt, dm, m, BUS_DMA_NOWAIT); 661 if (error == EFBIG) { 662 device_printf(sc->sc_dev, "won't fit\n"); 663 IFQ_DEQUEUE(&ifp->if_snd, m); 664 m_freem(m); 665 ifp->if_oerrors++; 666 continue; 667 } else if (error != 0) { 668 device_printf(sc->sc_dev, "error\n"); 669 break; 670 } 671 672 if (dm->dm_nsegs + 1 >= txfree) { 673 ifp->if_flags |= IFF_OACTIVE; 674 bus_dmamap_unload(sc->sc_bdt, dm); 675 break; 676 } 677 678 mlen = m_length(m); 679 pad = mlen < CPSW_PAD_LEN; 680 681 KASSERT(rdp->tx_mb[sc->sc_txnext] == NULL); 682 rdp->tx_mb[sc->sc_txnext] = m; 683 IFQ_DEQUEUE(&ifp->if_snd, m); 684 685 bus_dmamap_sync(sc->sc_bdt, dm, 0, dm->dm_mapsize, 686 BUS_DMASYNC_PREWRITE); 687 688 if (txstart == -1) 689 txstart = sc->sc_txnext; 690 eopi = sc->sc_txnext; 691 for (seg = 0; seg < dm->dm_nsegs; seg++) { 692 dw[0] = cpsw_txdesc_paddr(sc, 693 TXDESC_NEXT(sc->sc_txnext)); 694 dw[1] = dm->dm_segs[seg].ds_addr; 695 dw[2] = dm->dm_segs[seg].ds_len; 696 dw[3] = 0; 697 698 if (seg == 0) 699 dw[3] |= CPDMA_BD_SOP | CPDMA_BD_OWNER | 700 MAX(mlen, CPSW_PAD_LEN); 701 702 if ((seg == dm->dm_nsegs - 1) && !pad) 703 dw[3] |= CPDMA_BD_EOP; 704 705 cpsw_set_txdesc(sc, sc->sc_txnext, &bd); 706 txfree--; 707 eopi = sc->sc_txnext; 708 sc->sc_txnext = TXDESC_NEXT(sc->sc_txnext); 709 } 710 if (pad) { 711 dw[0] = cpsw_txdesc_paddr(sc, 712 TXDESC_NEXT(sc->sc_txnext)); 713 dw[1] = sc->sc_txpad_pa; 714 dw[2] = CPSW_PAD_LEN - mlen; 715 dw[3] = CPDMA_BD_EOP; 716 717 cpsw_set_txdesc(sc, sc->sc_txnext, &bd); 718 txfree--; 719 eopi = sc->sc_txnext; 720 sc->sc_txnext = TXDESC_NEXT(sc->sc_txnext); 721 } 722 723 bpf_mtap(ifp, m, BPF_D_OUT); 724 } 725 726 if (txstart >= 0) { 727 ifp->if_timer = 5; 728 /* terminate the new chain */ 729 KASSERT(eopi == TXDESC_PREV(sc->sc_txnext)); 730 cpsw_set_txdesc_next(sc, TXDESC_PREV(sc->sc_txnext), 0); 731 KERNHIST_LOG(cpswhist, "CP %x HDP %x s %x e %x\n", 732 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)), 733 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)), txstart, eopi); 734 /* link the new chain on */ 735 cpsw_set_txdesc_next(sc, TXDESC_PREV(txstart), 736 cpsw_txdesc_paddr(sc, txstart)); 737 if (sc->sc_txeoq) { 738 /* kick the dma engine */ 739 sc->sc_txeoq = false; 740 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 741 cpsw_txdesc_paddr(sc, txstart)); 742 } 743 } 744 KERNHIST_LOG(cpswhist, "end txf %x txh %x txn %x txr %x\n", 745 txfree, sc->sc_txhead, sc->sc_txnext, sc->sc_txrun); 746 } 747 748 static int 749 cpsw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 750 { 751 const int s = splnet(); 752 int error = 0; 753 754 switch (cmd) { 755 default: 756 error = ether_ioctl(ifp, cmd, data); 757 if (error == ENETRESET) { 758 error = 0; 759 } 760 break; 761 } 762 763 splx(s); 764 765 return error; 766 } 767 768 static void 769 cpsw_watchdog(struct ifnet *ifp) 770 { 771 struct cpsw_softc *sc = ifp->if_softc; 772 773 device_printf(sc->sc_dev, "device timeout\n"); 774 775 ifp->if_oerrors++; 776 cpsw_init(ifp); 777 cpsw_start(ifp); 778 } 779 780 static int 781 cpsw_mii_wait(struct cpsw_softc * const sc, int reg) 782 { 783 u_int tries; 784 785 for (tries = 0; tries < 1000; tries++) { 786 if ((cpsw_read_4(sc, reg) & __BIT(31)) == 0) 787 return 0; 788 delay(1); 789 } 790 return ETIMEDOUT; 791 } 792 793 static int 794 cpsw_mii_readreg(device_t dev, int phy, int reg, uint16_t *val) 795 { 796 struct cpsw_softc * const sc = device_private(dev); 797 uint32_t v; 798 799 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 800 return -1; 801 802 cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | 803 ((reg & 0x1F) << 21) | ((phy & 0x1F) << 16)); 804 805 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 806 return -1; 807 808 v = cpsw_read_4(sc, MDIOUSERACCESS0); 809 if (v & __BIT(29)) { 810 *val = v & 0xffff; 811 return 0; 812 } 813 814 return -1; 815 } 816 817 static int 818 cpsw_mii_writereg(device_t dev, int phy, int reg, uint16_t val) 819 { 820 struct cpsw_softc * const sc = device_private(dev); 821 uint32_t v; 822 823 KASSERT((val & 0xffff0000UL) == 0); 824 825 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 826 goto out; 827 828 cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | (1 << 30) | 829 ((reg & 0x1F) << 21) | ((phy & 0x1F) << 16) | val); 830 831 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 832 goto out; 833 834 v = cpsw_read_4(sc, MDIOUSERACCESS0); 835 if ((v & __BIT(29)) == 0) { 836 out: 837 device_printf(sc->sc_dev, "%s error\n", __func__); 838 return -1; 839 } 840 841 return 0; 842 } 843 844 static void 845 cpsw_mii_statchg(struct ifnet *ifp) 846 { 847 return; 848 } 849 850 static int 851 cpsw_new_rxbuf(struct cpsw_softc * const sc, const u_int i) 852 { 853 struct cpsw_ring_data * const rdp = sc->sc_rdp; 854 const u_int h = RXDESC_PREV(i); 855 struct cpsw_cpdma_bd bd; 856 uint32_t * const dw = bd.word; 857 struct mbuf *m; 858 int error = ENOBUFS; 859 860 MGETHDR(m, M_DONTWAIT, MT_DATA); 861 if (m == NULL) { 862 goto reuse; 863 } 864 865 MCLGET(m, M_DONTWAIT); 866 if ((m->m_flags & M_EXT) == 0) { 867 m_freem(m); 868 goto reuse; 869 } 870 871 /* We have a new buffer, prepare it for the ring. */ 872 873 if (rdp->rx_mb[i] != NULL) 874 bus_dmamap_unload(sc->sc_bdt, rdp->rx_dm[i]); 875 876 m->m_len = m->m_pkthdr.len = MCLBYTES; 877 878 rdp->rx_mb[i] = m; 879 880 error = bus_dmamap_load_mbuf(sc->sc_bdt, rdp->rx_dm[i], rdp->rx_mb[i], 881 BUS_DMA_READ | BUS_DMA_NOWAIT); 882 if (error) { 883 device_printf(sc->sc_dev, "can't load rx DMA map %d: %d\n", 884 i, error); 885 } 886 887 bus_dmamap_sync(sc->sc_bdt, rdp->rx_dm[i], 888 0, rdp->rx_dm[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 889 890 error = 0; 891 892 reuse: 893 /* (re-)setup the descriptor */ 894 dw[0] = 0; 895 dw[1] = rdp->rx_dm[i]->dm_segs[0].ds_addr; 896 dw[2] = MIN(0x7ff, rdp->rx_dm[i]->dm_segs[0].ds_len); 897 dw[3] = CPDMA_BD_OWNER; 898 899 cpsw_set_rxdesc(sc, i, &bd); 900 /* and link onto ring */ 901 cpsw_set_rxdesc_next(sc, h, cpsw_rxdesc_paddr(sc, i)); 902 903 return error; 904 } 905 906 static int 907 cpsw_init(struct ifnet *ifp) 908 { 909 struct cpsw_softc * const sc = ifp->if_softc; 910 struct mii_data * const mii = &sc->sc_mii; 911 int i; 912 913 cpsw_stop(ifp, 0); 914 915 sc->sc_txnext = 0; 916 sc->sc_txhead = 0; 917 918 /* Reset wrapper */ 919 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 920 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 921 ; 922 923 /* Reset SS */ 924 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 925 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 926 ; 927 928 /* Clear table and enable ALE */ 929 cpsw_write_4(sc, CPSW_ALE_CONTROL, 930 ALECTL_ENABLE_ALE | ALECTL_CLEAR_TABLE); 931 932 /* Reset and init Sliver port 1 and 2 */ 933 for (i = 0; i < CPSW_ETH_PORTS; i++) { 934 uint32_t macctl; 935 936 /* Reset */ 937 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 938 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 939 ; 940 /* Set Slave Mapping */ 941 cpsw_write_4(sc, CPSW_SL_RX_PRI_MAP(i), 0x76543210); 942 cpsw_write_4(sc, CPSW_PORT_P_TX_PRI_MAP(i+1), 0x33221100); 943 cpsw_write_4(sc, CPSW_SL_RX_MAXLEN(i), 0x5f2); 944 /* Set MAC Address */ 945 cpsw_write_4(sc, CPSW_PORT_P_SA_HI(i+1), 946 sc->sc_enaddr[0] | (sc->sc_enaddr[1] << 8) | 947 (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[3] << 24)); 948 cpsw_write_4(sc, CPSW_PORT_P_SA_LO(i+1), 949 sc->sc_enaddr[4] | (sc->sc_enaddr[5] << 8)); 950 951 /* Set MACCONTROL for ports 0,1 */ 952 macctl = SLMACCTL_FULLDUPLEX | SLMACCTL_GMII_EN | 953 SLMACCTL_IFCTL_A; 954 if (sc->sc_phy_has_1000t) 955 macctl |= SLMACCTL_GIG; 956 cpsw_write_4(sc, CPSW_SL_MACCONTROL(i), macctl); 957 958 /* Set ALE port to forwarding(3) */ 959 cpsw_write_4(sc, CPSW_ALE_PORTCTL(i+1), 3); 960 } 961 962 /* Set Host Port Mapping */ 963 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210); 964 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0); 965 966 /* Set ALE port to forwarding(3) */ 967 cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 3); 968 969 /* Initialize addrs */ 970 cpsw_ale_update_addresses(sc, 1); 971 972 cpsw_write_4(sc, CPSW_SS_PTYPE, 0); 973 cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7); 974 975 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 976 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 977 ; 978 979 for (i = 0; i < 8; i++) { 980 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0); 981 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0); 982 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0); 983 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0); 984 } 985 986 bus_space_set_region_4(sc->sc_bst, sc->sc_bsh_txdescs, 0, 0, 987 CPSW_CPPI_RAM_TXDESCS_SIZE/4); 988 989 sc->sc_txhead = 0; 990 sc->sc_txnext = 0; 991 992 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0); 993 994 bus_space_set_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, 0, 0, 995 CPSW_CPPI_RAM_RXDESCS_SIZE/4); 996 /* Initialize RX Buffer Descriptors */ 997 cpsw_set_rxdesc_next(sc, RXDESC_PREV(0), 0); 998 for (i = 0; i < CPSW_NRXDESCS; i++) { 999 cpsw_new_rxbuf(sc, i); 1000 } 1001 sc->sc_rxhead = 0; 1002 1003 /* turn off flow control */ 1004 cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0); 1005 1006 /* align layer 3 header to 32-bit */ 1007 cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, ETHER_ALIGN); 1008 1009 /* Clear all interrupt Masks */ 1010 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF); 1011 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF); 1012 1013 /* Enable TX & RX DMA */ 1014 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1); 1015 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1); 1016 1017 /* Enable TX and RX interrupt receive for core 0 */ 1018 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 1); 1019 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 1); 1020 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F); 1021 1022 /* Enable host Error Interrupt */ 1023 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 2); 1024 1025 /* Enable interrupts for TX and RX Channel 0 */ 1026 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1); 1027 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 1); 1028 1029 /* Ack stalled irqs */ 1030 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH); 1031 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX); 1032 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX); 1033 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC); 1034 1035 /* Initialize MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */ 1036 /* TODO Calculate MDCLK=CLK/(CLKDIV+1) */ 1037 cpsw_write_4(sc, MDIOCONTROL, 1038 MDIOCTL_ENABLE | MDIOCTL_FAULTENB | MDIOCTL_CLKDIV(0xff)); 1039 1040 mii_mediachg(mii); 1041 1042 /* Write channel 0 RX HDP */ 1043 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(0), cpsw_rxdesc_paddr(sc, 0)); 1044 sc->sc_rxrun = true; 1045 sc->sc_rxeoq = false; 1046 1047 sc->sc_txrun = true; 1048 sc->sc_txeoq = true; 1049 callout_schedule(&sc->sc_tick_ch, hz); 1050 ifp->if_flags |= IFF_RUNNING; 1051 ifp->if_flags &= ~IFF_OACTIVE; 1052 1053 return 0; 1054 } 1055 1056 static void 1057 cpsw_stop(struct ifnet *ifp, int disable) 1058 { 1059 struct cpsw_softc * const sc = ifp->if_softc; 1060 struct cpsw_ring_data * const rdp = sc->sc_rdp; 1061 u_int i; 1062 1063 aprint_debug_dev(sc->sc_dev, "%s: ifp %p disable %d\n", __func__, 1064 ifp, disable); 1065 1066 if ((ifp->if_flags & IFF_RUNNING) == 0) 1067 return; 1068 1069 callout_stop(&sc->sc_tick_ch); 1070 mii_down(&sc->sc_mii); 1071 1072 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 1); 1073 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 1); 1074 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0x0); 1075 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0x0); 1076 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x0); 1077 1078 cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0); 1079 cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0); 1080 i = 0; 1081 while ((sc->sc_txrun || sc->sc_rxrun) && i < 10000) { 1082 delay(10); 1083 if ((sc->sc_txrun == true) && cpsw_txintr(sc) == 0) 1084 sc->sc_txrun = false; 1085 if ((sc->sc_rxrun == true) && cpsw_rxintr(sc) == 0) 1086 sc->sc_rxrun = false; 1087 i++; 1088 } 1089 //printf("%s toredown complete in %u\n", __func__, i); 1090 1091 /* Reset wrapper */ 1092 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 1093 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 1094 ; 1095 1096 /* Reset SS */ 1097 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 1098 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 1099 ; 1100 1101 for (i = 0; i < CPSW_ETH_PORTS; i++) { 1102 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 1103 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 1104 ; 1105 } 1106 1107 /* Reset CPDMA */ 1108 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 1109 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 1110 ; 1111 1112 /* Release any queued transmit buffers. */ 1113 for (i = 0; i < CPSW_NTXDESCS; i++) { 1114 bus_dmamap_unload(sc->sc_bdt, rdp->tx_dm[i]); 1115 m_freem(rdp->tx_mb[i]); 1116 rdp->tx_mb[i] = NULL; 1117 } 1118 1119 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1120 ifp->if_timer = 0; 1121 1122 if (!disable) 1123 return; 1124 1125 for (i = 0; i < CPSW_NRXDESCS; i++) { 1126 bus_dmamap_unload(sc->sc_bdt, rdp->rx_dm[i]); 1127 m_freem(rdp->rx_mb[i]); 1128 rdp->rx_mb[i] = NULL; 1129 } 1130 } 1131 1132 static void 1133 cpsw_tick(void *arg) 1134 { 1135 struct cpsw_softc * const sc = arg; 1136 struct mii_data * const mii = &sc->sc_mii; 1137 const int s = splnet(); 1138 1139 mii_tick(mii); 1140 1141 splx(s); 1142 1143 callout_schedule(&sc->sc_tick_ch, hz); 1144 } 1145 1146 static int 1147 cpsw_rxthintr(void *arg) 1148 { 1149 struct cpsw_softc * const sc = arg; 1150 1151 /* this won't deassert the interrupt though */ 1152 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH); 1153 1154 return 1; 1155 } 1156 1157 static int 1158 cpsw_rxintr(void *arg) 1159 { 1160 struct cpsw_softc * const sc = arg; 1161 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1162 struct cpsw_ring_data * const rdp = sc->sc_rdp; 1163 struct cpsw_cpdma_bd bd; 1164 const uint32_t * const dw = bd.word; 1165 bus_dmamap_t dm; 1166 struct mbuf *m; 1167 u_int i; 1168 u_int len, off; 1169 1170 KERNHIST_FUNC(__func__); 1171 KERNHIST_CALLED_5(cpswhist, sc, 0, 0, 0); 1172 1173 for (;;) { 1174 KASSERT(sc->sc_rxhead < CPSW_NRXDESCS); 1175 1176 i = sc->sc_rxhead; 1177 KERNHIST_LOG(cpswhist, "rxhead %x CP %x\n", i, 1178 cpsw_read_4(sc, CPSW_CPDMA_RX_CP(0)), 0, 0); 1179 dm = rdp->rx_dm[i]; 1180 m = rdp->rx_mb[i]; 1181 1182 KASSERT(dm != NULL); 1183 KASSERT(m != NULL); 1184 1185 cpsw_get_rxdesc(sc, i, &bd); 1186 1187 if (ISSET(dw[3], CPDMA_BD_OWNER)) 1188 break; 1189 1190 if (ISSET(dw[3], CPDMA_BD_TDOWNCMPLT)) { 1191 sc->sc_rxrun = false; 1192 return 1; 1193 } 1194 1195 if ((dw[3] & (CPDMA_BD_SOP | CPDMA_BD_EOP)) != 1196 (CPDMA_BD_SOP | CPDMA_BD_EOP)) { 1197 //Debugger(); 1198 } 1199 1200 bus_dmamap_sync(sc->sc_bdt, dm, 0, dm->dm_mapsize, 1201 BUS_DMASYNC_POSTREAD); 1202 1203 if (cpsw_new_rxbuf(sc, i) != 0) { 1204 /* drop current packet, reuse buffer for new */ 1205 ifp->if_ierrors++; 1206 goto next; 1207 } 1208 1209 off = __SHIFTOUT(dw[2], (uint32_t)__BITS(26, 16)); 1210 len = __SHIFTOUT(dw[3], (uint32_t)__BITS(10, 0)); 1211 1212 if (ISSET(dw[3], CPDMA_BD_PASSCRC)) 1213 len -= ETHER_CRC_LEN; 1214 1215 m_set_rcvif(m, ifp); 1216 m->m_pkthdr.len = m->m_len = len; 1217 m->m_data += off; 1218 1219 if_percpuq_enqueue(ifp->if_percpuq, m); 1220 1221 next: 1222 sc->sc_rxhead = RXDESC_NEXT(sc->sc_rxhead); 1223 if (ISSET(dw[3], CPDMA_BD_EOQ)) { 1224 sc->sc_rxeoq = true; 1225 break; 1226 } else { 1227 sc->sc_rxeoq = false; 1228 } 1229 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(0), 1230 cpsw_rxdesc_paddr(sc, i)); 1231 } 1232 1233 if (sc->sc_rxeoq) { 1234 device_printf(sc->sc_dev, "rxeoq\n"); 1235 //Debugger(); 1236 } 1237 1238 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX); 1239 1240 return 1; 1241 } 1242 1243 static int 1244 cpsw_txintr(void *arg) 1245 { 1246 struct cpsw_softc * const sc = arg; 1247 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1248 struct cpsw_ring_data * const rdp = sc->sc_rdp; 1249 struct cpsw_cpdma_bd bd; 1250 const uint32_t * const dw = bd.word; 1251 bool handled = false; 1252 uint32_t tx0_cp; 1253 u_int cpi; 1254 1255 KERNHIST_FUNC(__func__); 1256 KERNHIST_CALLED_5(cpswhist, sc, 0, 0, 0); 1257 1258 KASSERT(sc->sc_txrun); 1259 1260 KERNHIST_LOG(cpswhist, "before txnext %x txhead %x txrun %x\n", 1261 sc->sc_txnext, sc->sc_txhead, sc->sc_txrun, 0); 1262 1263 tx0_cp = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)); 1264 1265 if (tx0_cp == 0xfffffffc) { 1266 /* Teardown, ack it */ 1267 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(0), 0xfffffffc); 1268 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 0); 1269 sc->sc_txrun = false; 1270 return 0; 1271 } 1272 1273 for (;;) { 1274 tx0_cp = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)); 1275 cpi = (tx0_cp - sc->sc_txdescs_pa) / sizeof(struct cpsw_cpdma_bd); 1276 KASSERT(sc->sc_txhead < CPSW_NTXDESCS); 1277 1278 KERNHIST_LOG(cpswhist, "txnext %x txhead %x txrun %x cpi %x\n", 1279 sc->sc_txnext, sc->sc_txhead, sc->sc_txrun, cpi); 1280 1281 cpsw_get_txdesc(sc, sc->sc_txhead, &bd); 1282 1283 if (dw[2] == 0) { 1284 //Debugger(); 1285 } 1286 1287 if (ISSET(dw[3], CPDMA_BD_SOP) == 0) 1288 goto next; 1289 1290 if (ISSET(dw[3], CPDMA_BD_OWNER)) { 1291 printf("pwned %x %x %x\n", cpi, sc->sc_txhead, 1292 sc->sc_txnext); 1293 break; 1294 } 1295 1296 if (ISSET(dw[3], CPDMA_BD_TDOWNCMPLT)) { 1297 sc->sc_txrun = false; 1298 return 1; 1299 } 1300 1301 bus_dmamap_sync(sc->sc_bdt, rdp->tx_dm[sc->sc_txhead], 1302 0, rdp->tx_dm[sc->sc_txhead]->dm_mapsize, 1303 BUS_DMASYNC_POSTWRITE); 1304 bus_dmamap_unload(sc->sc_bdt, rdp->tx_dm[sc->sc_txhead]); 1305 1306 m_freem(rdp->tx_mb[sc->sc_txhead]); 1307 rdp->tx_mb[sc->sc_txhead] = NULL; 1308 1309 ifp->if_opackets++; 1310 1311 handled = true; 1312 1313 ifp->if_flags &= ~IFF_OACTIVE; 1314 1315 next: 1316 if (ISSET(dw[3], CPDMA_BD_EOP) && ISSET(dw[3], CPDMA_BD_EOQ)) { 1317 sc->sc_txeoq = true; 1318 } 1319 if (sc->sc_txhead == cpi) { 1320 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(0), 1321 cpsw_txdesc_paddr(sc, cpi)); 1322 sc->sc_txhead = TXDESC_NEXT(sc->sc_txhead); 1323 break; 1324 } 1325 sc->sc_txhead = TXDESC_NEXT(sc->sc_txhead); 1326 if (ISSET(dw[3], CPDMA_BD_EOP) && ISSET(dw[3], CPDMA_BD_EOQ)) { 1327 sc->sc_txeoq = true; 1328 break; 1329 } 1330 } 1331 1332 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX); 1333 1334 if ((sc->sc_txnext != sc->sc_txhead) && sc->sc_txeoq) { 1335 if (cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)) == 0) { 1336 sc->sc_txeoq = false; 1337 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 1338 cpsw_txdesc_paddr(sc, sc->sc_txhead)); 1339 } 1340 } 1341 1342 KERNHIST_LOG(cpswhist, "after txnext %x txhead %x txrun %x\n", 1343 sc->sc_txnext, sc->sc_txhead, sc->sc_txrun, 0); 1344 KERNHIST_LOG(cpswhist, "CP %x HDP %x\n", 1345 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)), 1346 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)), 0, 0); 1347 1348 if (handled && sc->sc_txnext == sc->sc_txhead) 1349 ifp->if_timer = 0; 1350 1351 if (handled) 1352 if_schedule_deferred_start(ifp); 1353 1354 return handled; 1355 } 1356 1357 static int 1358 cpsw_miscintr(void *arg) 1359 { 1360 struct cpsw_softc * const sc = arg; 1361 uint32_t miscstat; 1362 uint32_t dmastat; 1363 uint32_t stat; 1364 1365 miscstat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0)); 1366 device_printf(sc->sc_dev, "%s %x FIRE\n", __func__, miscstat); 1367 1368 #define CPSW_MISC_HOST_PEND __BIT32(2) 1369 #define CPSW_MISC_STAT_PEND __BIT32(3) 1370 1371 if (ISSET(miscstat, CPSW_MISC_HOST_PEND)) { 1372 /* Host Error */ 1373 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 1374 printf("CPSW_CPDMA_DMA_INTSTAT_MASKED %x\n", dmastat); 1375 1376 printf("rxhead %02x\n", sc->sc_rxhead); 1377 1378 stat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS); 1379 printf("CPSW_CPDMA_DMASTATUS %x\n", stat); 1380 stat = cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)); 1381 printf("CPSW_CPDMA_TX0_HDP %x\n", stat); 1382 stat = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)); 1383 printf("CPSW_CPDMA_TX0_CP %x\n", stat); 1384 stat = cpsw_read_4(sc, CPSW_CPDMA_RX_HDP(0)); 1385 printf("CPSW_CPDMA_RX0_HDP %x\n", stat); 1386 stat = cpsw_read_4(sc, CPSW_CPDMA_RX_CP(0)); 1387 printf("CPSW_CPDMA_RX0_CP %x\n", stat); 1388 1389 //Debugger(); 1390 1391 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, dmastat); 1392 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 1393 printf("CPSW_CPDMA_DMA_INTSTAT_MASKED %x\n", dmastat); 1394 } 1395 1396 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC); 1397 1398 return 1; 1399 } 1400 1401 /* 1402 * 1403 * ALE support routines. 1404 * 1405 */ 1406 1407 static void 1408 cpsw_ale_entry_init(uint32_t *ale_entry) 1409 { 1410 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 1411 } 1412 1413 static void 1414 cpsw_ale_entry_set_mac(uint32_t *ale_entry, const uint8_t *mac) 1415 { 1416 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 1417 ale_entry[1] = mac[0] << 8 | mac[1]; 1418 } 1419 1420 static void 1421 cpsw_ale_entry_set_bcast_mac(uint32_t *ale_entry) 1422 { 1423 ale_entry[0] = 0xffffffff; 1424 ale_entry[1] = 0x0000ffff; 1425 } 1426 1427 static void 1428 cpsw_ale_entry_set(uint32_t *ale_entry, ale_entry_field_t field, uint32_t val) 1429 { 1430 /* Entry type[61:60] is addr entry(1), Mcast fwd state[63:62] is fw(3)*/ 1431 switch (field) { 1432 case ALE_ENTRY_TYPE: 1433 /* [61:60] */ 1434 ale_entry[1] |= (val & 0x3) << 28; 1435 break; 1436 case ALE_MCAST_FWD_STATE: 1437 /* [63:62] */ 1438 ale_entry[1] |= (val & 0x3) << 30; 1439 break; 1440 case ALE_PORT_MASK: 1441 /* [68:66] */ 1442 ale_entry[2] |= (val & 0x7) << 2; 1443 break; 1444 case ALE_PORT_NUMBER: 1445 /* [67:66] */ 1446 ale_entry[2] |= (val & 0x3) << 2; 1447 break; 1448 default: 1449 panic("Invalid ALE entry field: %d\n", field); 1450 } 1451 1452 return; 1453 } 1454 1455 static bool 1456 cpsw_ale_entry_mac_match(const uint32_t *ale_entry, const uint8_t *mac) 1457 { 1458 return (((ale_entry[1] >> 8) & 0xff) == mac[0]) && 1459 (((ale_entry[1] >> 0) & 0xff) == mac[1]) && 1460 (((ale_entry[0] >>24) & 0xff) == mac[2]) && 1461 (((ale_entry[0] >>16) & 0xff) == mac[3]) && 1462 (((ale_entry[0] >> 8) & 0xff) == mac[4]) && 1463 (((ale_entry[0] >> 0) & 0xff) == mac[5]); 1464 } 1465 1466 static void 1467 cpsw_ale_set_outgoing_mac(struct cpsw_softc *sc, int port, const uint8_t *mac) 1468 { 1469 cpsw_write_4(sc, CPSW_PORT_P_SA_HI(port), 1470 mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]); 1471 cpsw_write_4(sc, CPSW_PORT_P_SA_LO(port), 1472 mac[5] << 8 | mac[4]); 1473 } 1474 1475 static void 1476 cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 1477 { 1478 cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023); 1479 ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0); 1480 ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1); 1481 ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2); 1482 } 1483 1484 static void 1485 cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, 1486 const uint32_t *ale_entry) 1487 { 1488 cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]); 1489 cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]); 1490 cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]); 1491 cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023)); 1492 } 1493 1494 static int 1495 cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc) 1496 { 1497 int i; 1498 uint32_t ale_entry[3]; 1499 1500 /* First two entries are link address and broadcast. */ 1501 for (i = 2; i < CPSW_MAX_ALE_ENTRIES; i++) { 1502 cpsw_ale_read_entry(sc, i, ale_entry); 1503 if (((ale_entry[1] >> 28) & 3) == 1 && /* Address entry */ 1504 ((ale_entry[1] >> 8) & 1) == 1) { /* MCast link addr */ 1505 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 1506 cpsw_ale_write_entry(sc, i, ale_entry); 1507 } 1508 } 1509 return CPSW_MAX_ALE_ENTRIES; 1510 } 1511 1512 static int 1513 cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmask, uint8_t *mac) 1514 { 1515 int free_index = -1, matching_index = -1, i; 1516 uint32_t ale_entry[3]; 1517 1518 /* Find a matching entry or a free entry. */ 1519 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 1520 cpsw_ale_read_entry(sc, i, ale_entry); 1521 1522 /* Entry Type[61:60] is 0 for free entry */ 1523 if (free_index < 0 && ((ale_entry[1] >> 28) & 3) == 0) { 1524 free_index = i; 1525 } 1526 1527 if (cpsw_ale_entry_mac_match(ale_entry, mac)) { 1528 matching_index = i; 1529 break; 1530 } 1531 } 1532 1533 if (matching_index < 0) { 1534 if (free_index < 0) 1535 return ENOMEM; 1536 i = free_index; 1537 } 1538 1539 cpsw_ale_entry_init(ale_entry); 1540 1541 cpsw_ale_entry_set_mac(ale_entry, mac); 1542 cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS); 1543 cpsw_ale_entry_set(ale_entry, ALE_MCAST_FWD_STATE, ALE_FWSTATE_FWONLY); 1544 cpsw_ale_entry_set(ale_entry, ALE_PORT_MASK, portmask); 1545 1546 cpsw_ale_write_entry(sc, i, ale_entry); 1547 1548 return 0; 1549 } 1550 1551 static int 1552 cpsw_ale_update_addresses(struct cpsw_softc *sc, int purge) 1553 { 1554 uint8_t *mac = sc->sc_enaddr; 1555 uint32_t ale_entry[3]; 1556 int i; 1557 struct ethercom * const ec = &sc->sc_ec; 1558 struct ether_multi *ifma; 1559 1560 cpsw_ale_entry_init(ale_entry); 1561 /* Route incoming packets for our MAC address to Port 0 (host). */ 1562 /* For simplicity, keep this entry at table index 0 in the ALE. */ 1563 cpsw_ale_entry_set_mac(ale_entry, mac); 1564 cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS); 1565 cpsw_ale_entry_set(ale_entry, ALE_PORT_NUMBER, 0); 1566 cpsw_ale_write_entry(sc, 0, ale_entry); 1567 1568 /* Set outgoing MAC Address for Ports 1 and 2. */ 1569 for (i = CPSW_CPPI_PORTS; i < (CPSW_ETH_PORTS + CPSW_CPPI_PORTS); ++i) 1570 cpsw_ale_set_outgoing_mac(sc, i, mac); 1571 1572 /* Keep the broadcast address at table entry 1. */ 1573 cpsw_ale_entry_init(ale_entry); 1574 cpsw_ale_entry_set_bcast_mac(ale_entry); 1575 cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS); 1576 cpsw_ale_entry_set(ale_entry, ALE_MCAST_FWD_STATE, ALE_FWSTATE_FWONLY); 1577 cpsw_ale_entry_set(ale_entry, ALE_PORT_MASK, ALE_PORT_MASK_ALL); 1578 cpsw_ale_write_entry(sc, 1, ale_entry); 1579 1580 /* SIOCDELMULTI doesn't specify the particular address 1581 being removed, so we have to remove all and rebuild. */ 1582 if (purge) 1583 cpsw_ale_remove_all_mc_entries(sc); 1584 1585 /* Set other multicast addrs desired. */ 1586 LIST_FOREACH(ifma, &ec->ec_multiaddrs, enm_list) { 1587 cpsw_ale_mc_entry_set(sc, ALE_PORT_MASK_ALL, ifma->enm_addrlo); 1588 } 1589 1590 return 0; 1591 } 1592
Indexes created Tue Sep 30 11:09:46 GMT 2025