if_cpsw.c revision 1.8
1 /* $NetBSD: if_cpsw.c,v 1.8 2019/11/03 10:09:04 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 2012 Damjan Marion <dmarion (at) Freebsd.org> 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 43 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 46 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 48 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 52 * SUCH DAMAGE. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(1, "$NetBSD: if_cpsw.c,v 1.8 2019/11/03 10:09:04 jmcneill Exp $"); 57 58 #include <sys/param.h> 59 #include <sys/bus.h> 60 #include <sys/device.h> 61 #include <sys/ioctl.h> 62 #include <sys/intr.h> 63 #include <sys/kmem.h> 64 #include <sys/mutex.h> 65 #include <sys/systm.h> 66 #include <sys/kernel.h> 67 68 #include <net/if.h> 69 #include <net/if_ether.h> 70 #include <net/if_media.h> 71 #include <net/bpf.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/fdt/fdtvar.h> 77 78 #include <arm/ti/if_cpswreg.h> 79 80 #define FDT_INTR_FLAGS 0 81 82 #define CPSW_TXFRAGS 16 83 84 #define CPSW_CPPI_RAM_SIZE (0x2000) 85 #define CPSW_CPPI_RAM_TXDESCS_SIZE (CPSW_CPPI_RAM_SIZE/2) 86 #define CPSW_CPPI_RAM_RXDESCS_SIZE \ 87 (CPSW_CPPI_RAM_SIZE - CPSW_CPPI_RAM_TXDESCS_SIZE) 88 #define CPSW_CPPI_RAM_TXDESCS_BASE (CPSW_CPPI_RAM_OFFSET + 0x0000) 89 #define CPSW_CPPI_RAM_RXDESCS_BASE \ 90 (CPSW_CPPI_RAM_OFFSET + CPSW_CPPI_RAM_TXDESCS_SIZE) 91 92 #define CPSW_NTXDESCS (CPSW_CPPI_RAM_TXDESCS_SIZE/sizeof(struct cpsw_cpdma_bd)) 93 #define CPSW_NRXDESCS (CPSW_CPPI_RAM_RXDESCS_SIZE/sizeof(struct cpsw_cpdma_bd)) 94 95 CTASSERT(powerof2(CPSW_NTXDESCS)); 96 CTASSERT(powerof2(CPSW_NRXDESCS)); 97 98 #define CPSW_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 99 100 #define TXDESC_NEXT(x) cpsw_txdesc_adjust((x), 1) 101 #define TXDESC_PREV(x) cpsw_txdesc_adjust((x), -1) 102 103 #define RXDESC_NEXT(x) cpsw_rxdesc_adjust((x), 1) 104 #define RXDESC_PREV(x) cpsw_rxdesc_adjust((x), -1) 105 106 struct cpsw_ring_data { 107 bus_dmamap_t tx_dm[CPSW_NTXDESCS]; 108 struct mbuf *tx_mb[CPSW_NTXDESCS]; 109 bus_dmamap_t rx_dm[CPSW_NRXDESCS]; 110 struct mbuf *rx_mb[CPSW_NRXDESCS]; 111 }; 112 113 struct cpsw_softc { 114 device_t sc_dev; 115 bus_space_tag_t sc_bst; 116 bus_space_handle_t sc_bsh; 117 bus_size_t sc_bss; 118 bus_dma_tag_t sc_bdt; 119 bus_space_handle_t sc_bsh_txdescs; 120 bus_space_handle_t sc_bsh_rxdescs; 121 bus_addr_t sc_txdescs_pa; 122 bus_addr_t sc_rxdescs_pa; 123 struct ethercom sc_ec; 124 struct mii_data sc_mii; 125 bool sc_phy_has_1000t; 126 bool sc_attached; 127 callout_t sc_tick_ch; 128 void *sc_ih; 129 struct cpsw_ring_data *sc_rdp; 130 volatile u_int sc_txnext; 131 volatile u_int sc_txhead; 132 volatile u_int sc_rxhead; 133 void *sc_rxthih; 134 void *sc_rxih; 135 void *sc_txih; 136 void *sc_miscih; 137 void *sc_txpad; 138 bus_dmamap_t sc_txpad_dm; 139 #define sc_txpad_pa sc_txpad_dm->dm_segs[0].ds_addr 140 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 141 volatile bool sc_txrun; 142 volatile bool sc_rxrun; 143 volatile bool sc_txeoq; 144 volatile bool sc_rxeoq; 145 }; 146 147 static int cpsw_match(device_t, cfdata_t, void *); 148 static void cpsw_attach(device_t, device_t, void *); 149 static int cpsw_detach(device_t, int); 150 151 static void cpsw_start(struct ifnet *); 152 static int cpsw_ioctl(struct ifnet *, u_long, void *); 153 static void cpsw_watchdog(struct ifnet *); 154 static int cpsw_init(struct ifnet *); 155 static void cpsw_stop(struct ifnet *, int); 156 157 static int cpsw_mii_readreg(device_t, int, int, uint16_t *); 158 static int cpsw_mii_writereg(device_t, int, int, uint16_t); 159 static void cpsw_mii_statchg(struct ifnet *); 160 161 static int cpsw_new_rxbuf(struct cpsw_softc * const, const u_int); 162 static void cpsw_tick(void *); 163 164 static int cpsw_rxthintr(void *); 165 static int cpsw_rxintr(void *); 166 static int cpsw_txintr(void *); 167 static int cpsw_miscintr(void *); 168 169 /* ALE support */ 170 #define CPSW_MAX_ALE_ENTRIES 1024 171 172 static int cpsw_ale_update_addresses(struct cpsw_softc *, int purge); 173 174 CFATTACH_DECL_NEW(cpsw, sizeof(struct cpsw_softc), 175 cpsw_match, cpsw_attach, cpsw_detach, NULL); 176 177 #undef KERNHIST 178 #include <sys/kernhist.h> 179 KERNHIST_DEFINE(cpswhist); 180 181 #ifdef KERNHIST 182 #define KERNHIST_CALLED_5(NAME, i, j, k, l) \ 183 do { \ 184 _kernhist_call = atomic_inc_uint_nv(&_kernhist_cnt); \ 185 KERNHIST_LOG(NAME, "called! %x %x %x %x", i, j, k, l); \ 186 } while (/*CONSTCOND*/ 0) 187 #else 188 #define KERNHIST_CALLED_5(NAME, i, j, k, l) 189 #endif 190 191 static inline u_int 192 cpsw_txdesc_adjust(u_int x, int y) 193 { 194 return (((x) + y) & (CPSW_NTXDESCS - 1)); 195 } 196 197 static inline u_int 198 cpsw_rxdesc_adjust(u_int x, int y) 199 { 200 return (((x) + y) & (CPSW_NRXDESCS - 1)); 201 } 202 203 static inline uint32_t 204 cpsw_read_4(struct cpsw_softc * const sc, bus_size_t const offset) 205 { 206 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, offset); 207 } 208 209 static inline void 210 cpsw_write_4(struct cpsw_softc * const sc, bus_size_t const offset, 211 uint32_t const value) 212 { 213 bus_space_write_4(sc->sc_bst, sc->sc_bsh, offset, value); 214 } 215 216 static inline void 217 cpsw_set_txdesc_next(struct cpsw_softc * const sc, const u_int i, uint32_t n) 218 { 219 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i + 0; 220 221 KERNHIST_FUNC(__func__); 222 KERNHIST_CALLED_5(cpswhist, sc, i, n, 0); 223 224 bus_space_write_4(sc->sc_bst, sc->sc_bsh_txdescs, o, n); 225 } 226 227 static inline void 228 cpsw_set_rxdesc_next(struct cpsw_softc * const sc, const u_int i, uint32_t n) 229 { 230 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i + 0; 231 232 KERNHIST_FUNC(__func__); 233 KERNHIST_CALLED_5(cpswhist, sc, i, n, 0); 234 235 bus_space_write_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, n); 236 } 237 238 static inline void 239 cpsw_get_txdesc(struct cpsw_softc * const sc, const u_int i, 240 struct cpsw_cpdma_bd * const bdp) 241 { 242 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 243 uint32_t * const dp = bdp->word; 244 const bus_size_t c = __arraycount(bdp->word); 245 246 KERNHIST_FUNC(__func__); 247 KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0); 248 249 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh_txdescs, o, dp, c); 250 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 251 dp[0], dp[1], dp[2], dp[3]); 252 } 253 254 static inline void 255 cpsw_set_txdesc(struct cpsw_softc * const sc, const u_int i, 256 struct cpsw_cpdma_bd * const bdp) 257 { 258 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 259 uint32_t * const dp = bdp->word; 260 const bus_size_t c = __arraycount(bdp->word); 261 262 KERNHIST_FUNC(__func__); 263 KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0); 264 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 265 dp[0], dp[1], dp[2], dp[3]); 266 267 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh_txdescs, o, dp, c); 268 } 269 270 static inline void 271 cpsw_get_rxdesc(struct cpsw_softc * const sc, const u_int i, 272 struct cpsw_cpdma_bd * const bdp) 273 { 274 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 275 uint32_t * const dp = bdp->word; 276 const bus_size_t c = __arraycount(bdp->word); 277 278 KERNHIST_FUNC(__func__); 279 KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0); 280 281 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, dp, c); 282 283 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 284 dp[0], dp[1], dp[2], dp[3]); 285 } 286 287 static inline void 288 cpsw_set_rxdesc(struct cpsw_softc * const sc, const u_int i, 289 struct cpsw_cpdma_bd * const bdp) 290 { 291 const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i; 292 uint32_t * const dp = bdp->word; 293 const bus_size_t c = __arraycount(bdp->word); 294 295 KERNHIST_FUNC(__func__); 296 KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0); 297 KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n", 298 dp[0], dp[1], dp[2], dp[3]); 299 300 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, dp, c); 301 } 302 303 static inline bus_addr_t 304 cpsw_txdesc_paddr(struct cpsw_softc * const sc, u_int x) 305 { 306 KASSERT(x < CPSW_NTXDESCS); 307 return sc->sc_txdescs_pa + sizeof(struct cpsw_cpdma_bd) * x; 308 } 309 310 static inline bus_addr_t 311 cpsw_rxdesc_paddr(struct cpsw_softc * const sc, u_int x) 312 { 313 KASSERT(x < CPSW_NRXDESCS); 314 return sc->sc_rxdescs_pa + sizeof(struct cpsw_cpdma_bd) * x; 315 } 316 317 318 static int 319 cpsw_match(device_t parent, cfdata_t cf, void *aux) 320 { 321 struct fdt_attach_args * const faa = aux; 322 323 static const char * const compatible[] = { 324 "ti,am335x-cpsw", 325 "ti,cpsw", 326 NULL 327 }; 328 329 return of_match_compatible(faa->faa_phandle, compatible); 330 } 331 332 static bool 333 cpsw_phy_has_1000t(struct cpsw_softc * const sc) 334 { 335 struct ifmedia_entry *ifm; 336 337 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 338 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T) 339 return true; 340 } 341 return false; 342 } 343 344 static int 345 cpsw_detach(device_t self, int flags) 346 { 347 struct cpsw_softc * const sc = device_private(self); 348 struct ifnet *ifp = &sc->sc_ec.ec_if; 349 u_int i; 350 351 /* Succeed now if there's no work to do. */ 352 if (!sc->sc_attached) 353 return 0; 354 355 sc->sc_attached = false; 356 357 /* Stop the interface. Callouts are stopped in it. */ 358 cpsw_stop(ifp, 1); 359 360 /* Destroy our callout. */ 361 callout_destroy(&sc->sc_tick_ch); 362 363 /* Let go of the interrupts */ 364 intr_disestablish(sc->sc_rxthih); 365 intr_disestablish(sc->sc_rxih); 366 intr_disestablish(sc->sc_txih); 367 intr_disestablish(sc->sc_miscih); 368 369 /* Delete all media. */ 370 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 371 372 ether_ifdetach(ifp); 373 if_detach(ifp); 374 375 /* Free the packet padding buffer */ 376 kmem_free(sc->sc_txpad, ETHER_MIN_LEN); 377 bus_dmamap_destroy(sc->sc_bdt, sc->sc_txpad_dm); 378 379 /* Destroy all the descriptors */ 380 for (i = 0; i < CPSW_NTXDESCS; i++) 381 bus_dmamap_destroy(sc->sc_bdt, sc->sc_rdp->tx_dm[i]); 382 for (i = 0; i < CPSW_NRXDESCS; i++) 383 bus_dmamap_destroy(sc->sc_bdt, sc->sc_rdp->rx_dm[i]); 384 kmem_free(sc->sc_rdp, sizeof(*sc->sc_rdp)); 385 386 /* Unmap */ 387 bus_space_unmap(sc->sc_bst, sc->sc_bsh, sc->sc_bss); 388 389 390 return 0; 391 } 392 393 static void 394 cpsw_attach(device_t parent, device_t self, void *aux) 395 { 396 struct fdt_attach_args * const faa = aux; 397 struct cpsw_softc * const sc = device_private(self); 398 struct ethercom * const ec = &sc->sc_ec; 399 struct ifnet * const ifp = &ec->ec_if; 400 struct mii_data * const mii = &sc->sc_mii; 401 const int phandle = faa->faa_phandle; 402 const uint8_t *macaddr; 403 bus_addr_t addr; 404 bus_size_t size; 405 int error, slave, len; 406 u_int i; 407 408 KERNHIST_INIT(cpswhist, 4096); 409 410 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 411 aprint_error(": couldn't get registers\n"); 412 return; 413 } 414 415 sc->sc_dev = self; 416 417 aprint_normal(": TI Layer 2 3-Port Switch\n"); 418 aprint_naive("\n"); 419 420 callout_init(&sc->sc_tick_ch, 0); 421 callout_setfunc(&sc->sc_tick_ch, cpsw_tick, sc); 422 423 macaddr = NULL; 424 slave = of_find_firstchild_byname(phandle, "slave"); 425 if (slave > 0) { 426 macaddr = fdtbus_get_prop(slave, "mac-address", &len); 427 if (len != ETHER_ADDR_LEN) 428 macaddr = NULL; 429 } 430 if (macaddr == NULL) { 431 #if 0 432 /* grab mac_id0 from AM335x control module */ 433 uint32_t reg_lo, reg_hi; 434 435 if (sitara_cm_reg_read_4(OMAP2SCM_MAC_ID0_LO, ®_lo) == 0 && 436 sitara_cm_reg_read_4(OMAP2SCM_MAC_ID0_HI, ®_hi) == 0) { 437 sc->sc_enaddr[0] = (reg_hi >> 0) & 0xff; 438 sc->sc_enaddr[1] = (reg_hi >> 8) & 0xff; 439 sc->sc_enaddr[2] = (reg_hi >> 16) & 0xff; 440 sc->sc_enaddr[3] = (reg_hi >> 24) & 0xff; 441 sc->sc_enaddr[4] = (reg_lo >> 0) & 0xff; 442 sc->sc_enaddr[5] = (reg_lo >> 8) & 0xff; 443 } else 444 #endif 445 { 446 aprint_error_dev(sc->sc_dev, 447 "using fake station address\n"); 448 /* 'N' happens to have the Local bit set */ 449 #if 0 450 sc->sc_enaddr[0] = 'N'; 451 sc->sc_enaddr[1] = 'e'; 452 sc->sc_enaddr[2] = 't'; 453 sc->sc_enaddr[3] = 'B'; 454 sc->sc_enaddr[4] = 'S'; 455 sc->sc_enaddr[5] = 'D'; 456 #else 457 /* XXX Glor */ 458 sc->sc_enaddr[0] = 0xd4; 459 sc->sc_enaddr[1] = 0x94; 460 sc->sc_enaddr[2] = 0xa1; 461 sc->sc_enaddr[3] = 0x97; 462 sc->sc_enaddr[4] = 0x03; 463 sc->sc_enaddr[5] = 0x94; 464 #endif 465 } 466 } else { 467 memcpy(sc->sc_enaddr, macaddr, ETHER_ADDR_LEN); 468 } 469 470 sc->sc_rxthih = fdtbus_intr_establish(phandle, CPSW_INTROFF_RXTH, IPL_VM, FDT_INTR_FLAGS, cpsw_rxthintr, sc); 471 sc->sc_rxih = fdtbus_intr_establish(phandle, CPSW_INTROFF_RX, IPL_VM, FDT_INTR_FLAGS, cpsw_rxintr, sc); 472 sc->sc_txih = fdtbus_intr_establish(phandle, CPSW_INTROFF_TX, IPL_VM, FDT_INTR_FLAGS, cpsw_txintr, sc); 473 sc->sc_miscih = fdtbus_intr_establish(phandle, CPSW_INTROFF_MISC, IPL_VM, FDT_INTR_FLAGS, cpsw_miscintr, sc); 474 475 sc->sc_bst = faa->faa_bst; 476 sc->sc_bss = size; 477 sc->sc_bdt = faa->faa_dmat; 478 479 error = bus_space_map(sc->sc_bst, addr, size, 0, 480 &sc->sc_bsh); 481 if (error) { 482 aprint_error_dev(sc->sc_dev, 483 "can't map registers: %d\n", error); 484 return; 485 } 486 487 sc->sc_txdescs_pa = addr + CPSW_CPPI_RAM_TXDESCS_BASE; 488 error = bus_space_subregion(sc->sc_bst, sc->sc_bsh, 489 CPSW_CPPI_RAM_TXDESCS_BASE, CPSW_CPPI_RAM_TXDESCS_SIZE, 490 &sc->sc_bsh_txdescs); 491 if (error) { 492 aprint_error_dev(sc->sc_dev, 493 "can't subregion tx ring SRAM: %d\n", error); 494 return; 495 } 496 aprint_debug_dev(sc->sc_dev, "txdescs at %p\n", 497 (void *)sc->sc_bsh_txdescs); 498 499 sc->sc_rxdescs_pa = addr + CPSW_CPPI_RAM_RXDESCS_BASE; 500 error = bus_space_subregion(sc->sc_bst, sc->sc_bsh, 501 CPSW_CPPI_RAM_RXDESCS_BASE, CPSW_CPPI_RAM_RXDESCS_SIZE, 502 &sc->sc_bsh_rxdescs); 503 if (error) { 504 aprint_error_dev(sc->sc_dev, 505 "can't subregion rx ring SRAM: %d\n", error); 506 return; 507 } 508 aprint_debug_dev(sc->sc_dev, "rxdescs at %p\n", 509 (void *)sc->sc_bsh_rxdescs); 510 511 sc->sc_rdp = kmem_alloc(sizeof(*sc->sc_rdp), KM_SLEEP); 512 513 for (i = 0; i < CPSW_NTXDESCS; i++) { 514 if ((error = bus_dmamap_create(sc->sc_bdt, MCLBYTES, 515 CPSW_TXFRAGS, MCLBYTES, 0, 0, 516 &sc->sc_rdp->tx_dm[i])) != 0) { 517 aprint_error_dev(sc->sc_dev, 518 "unable to create tx DMA map: %d\n", error); 519 } 520 sc->sc_rdp->tx_mb[i] = NULL; 521 } 522 523 for (i = 0; i < CPSW_NRXDESCS; i++) { 524 if ((error = bus_dmamap_create(sc->sc_bdt, MCLBYTES, 1, 525 MCLBYTES, 0, 0, &sc->sc_rdp->rx_dm[i])) != 0) { 526 aprint_error_dev(sc->sc_dev, 527 "unable to create rx DMA map: %d\n", error); 528 } 529 sc->sc_rdp->rx_mb[i] = NULL; 530 } 531 532 sc->sc_txpad = kmem_zalloc(ETHER_MIN_LEN, KM_SLEEP); 533 bus_dmamap_create(sc->sc_bdt, ETHER_MIN_LEN, 1, ETHER_MIN_LEN, 0, 534 BUS_DMA_WAITOK, &sc->sc_txpad_dm); 535 bus_dmamap_load(sc->sc_bdt, sc->sc_txpad_dm, sc->sc_txpad, 536 ETHER_MIN_LEN, NULL, BUS_DMA_WAITOK | BUS_DMA_WRITE); 537 bus_dmamap_sync(sc->sc_bdt, sc->sc_txpad_dm, 0, ETHER_MIN_LEN, 538 BUS_DMASYNC_PREWRITE); 539 540 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 541 ether_sprintf(sc->sc_enaddr)); 542 543 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 544 ifp->if_softc = sc; 545 ifp->if_capabilities = 0; 546 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 547 ifp->if_start = cpsw_start; 548 ifp->if_ioctl = cpsw_ioctl; 549 ifp->if_init = cpsw_init; 550 ifp->if_stop = cpsw_stop; 551 ifp->if_watchdog = cpsw_watchdog; 552 IFQ_SET_READY(&ifp->if_snd); 553 554 cpsw_stop(ifp, 0); 555 556 mii->mii_ifp = ifp; 557 mii->mii_readreg = cpsw_mii_readreg; 558 mii->mii_writereg = cpsw_mii_writereg; 559 mii->mii_statchg = cpsw_mii_statchg; 560 561 sc->sc_ec.ec_mii = mii; 562 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 563 564 /* Initialize MDIO */ 565 cpsw_write_4(sc, MDIOCONTROL, 566 MDIOCTL_ENABLE | MDIOCTL_FAULTENB | MDIOCTL_CLKDIV(0xff)); 567 /* Clear ALE */ 568 cpsw_write_4(sc, CPSW_ALE_CONTROL, ALECTL_CLEAR_TABLE); 569 570 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 0, 0); 571 if (LIST_FIRST(&mii->mii_phys) == NULL) { 572 aprint_error_dev(self, "no PHY found!\n"); 573 sc->sc_phy_has_1000t = false; 574 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 575 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 576 } else { 577 sc->sc_phy_has_1000t = cpsw_phy_has_1000t(sc); 578 579 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 580 } 581 582 if_attach(ifp); 583 if_deferred_start_init(ifp, NULL); 584 ether_ifattach(ifp, sc->sc_enaddr); 585 586 /* The attach is successful. */ 587 sc->sc_attached = true; 588 589 return; 590 } 591 592 static void 593 cpsw_start(struct ifnet *ifp) 594 { 595 struct cpsw_softc * const sc = ifp->if_softc; 596 struct cpsw_ring_data * const rdp = sc->sc_rdp; 597 struct cpsw_cpdma_bd bd; 598 uint32_t * const dw = bd.word; 599 struct mbuf *m; 600 bus_dmamap_t dm; 601 u_int eopi __diagused = ~0; 602 u_int seg; 603 u_int txfree; 604 int txstart = -1; 605 int error; 606 bool pad; 607 u_int mlen; 608 609 KERNHIST_FUNC(__func__); 610 KERNHIST_CALLED_5(cpswhist, sc, 0, 0, 0); 611 612 if (__predict_false((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != 613 IFF_RUNNING)) { 614 return; 615 } 616 617 if (sc->sc_txnext >= sc->sc_txhead) 618 txfree = CPSW_NTXDESCS - 1 + sc->sc_txhead - sc->sc_txnext; 619 else 620 txfree = sc->sc_txhead - sc->sc_txnext - 1; 621 622 KERNHIST_LOG(cpswhist, "start txf %x txh %x txn %x txr %x\n", 623 txfree, sc->sc_txhead, sc->sc_txnext, sc->sc_txrun); 624 625 while (txfree > 0) { 626 IFQ_POLL(&ifp->if_snd, m); 627 if (m == NULL) 628 break; 629 630 dm = rdp->tx_dm[sc->sc_txnext]; 631 632 error = bus_dmamap_load_mbuf(sc->sc_bdt, dm, m, BUS_DMA_NOWAIT); 633 if (error == EFBIG) { 634 device_printf(sc->sc_dev, "won't fit\n"); 635 IFQ_DEQUEUE(&ifp->if_snd, m); 636 m_freem(m); 637 ifp->if_oerrors++; 638 continue; 639 } else if (error != 0) { 640 device_printf(sc->sc_dev, "error\n"); 641 break; 642 } 643 644 if (dm->dm_nsegs + 1 >= txfree) { 645 ifp->if_flags |= IFF_OACTIVE; 646 bus_dmamap_unload(sc->sc_bdt, dm); 647 break; 648 } 649 650 mlen = m_length(m); 651 pad = mlen < CPSW_PAD_LEN; 652 653 KASSERT(rdp->tx_mb[sc->sc_txnext] == NULL); 654 rdp->tx_mb[sc->sc_txnext] = m; 655 IFQ_DEQUEUE(&ifp->if_snd, m); 656 657 bus_dmamap_sync(sc->sc_bdt, dm, 0, dm->dm_mapsize, 658 BUS_DMASYNC_PREWRITE); 659 660 if (txstart == -1) 661 txstart = sc->sc_txnext; 662 eopi = sc->sc_txnext; 663 for (seg = 0; seg < dm->dm_nsegs; seg++) { 664 dw[0] = cpsw_txdesc_paddr(sc, 665 TXDESC_NEXT(sc->sc_txnext)); 666 dw[1] = dm->dm_segs[seg].ds_addr; 667 dw[2] = dm->dm_segs[seg].ds_len; 668 dw[3] = 0; 669 670 if (seg == 0) 671 dw[3] |= CPDMA_BD_SOP | CPDMA_BD_OWNER | 672 MAX(mlen, CPSW_PAD_LEN); 673 674 if ((seg == dm->dm_nsegs - 1) && !pad) 675 dw[3] |= CPDMA_BD_EOP; 676 677 cpsw_set_txdesc(sc, sc->sc_txnext, &bd); 678 txfree--; 679 eopi = sc->sc_txnext; 680 sc->sc_txnext = TXDESC_NEXT(sc->sc_txnext); 681 } 682 if (pad) { 683 dw[0] = cpsw_txdesc_paddr(sc, 684 TXDESC_NEXT(sc->sc_txnext)); 685 dw[1] = sc->sc_txpad_pa; 686 dw[2] = CPSW_PAD_LEN - mlen; 687 dw[3] = CPDMA_BD_EOP; 688 689 cpsw_set_txdesc(sc, sc->sc_txnext, &bd); 690 txfree--; 691 eopi = sc->sc_txnext; 692 sc->sc_txnext = TXDESC_NEXT(sc->sc_txnext); 693 } 694 695 bpf_mtap(ifp, m, BPF_D_OUT); 696 } 697 698 if (txstart >= 0) { 699 ifp->if_timer = 5; 700 /* terminate the new chain */ 701 KASSERT(eopi == TXDESC_PREV(sc->sc_txnext)); 702 cpsw_set_txdesc_next(sc, TXDESC_PREV(sc->sc_txnext), 0); 703 KERNHIST_LOG(cpswhist, "CP %x HDP %x s %x e %x\n", 704 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)), 705 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)), txstart, eopi); 706 /* link the new chain on */ 707 cpsw_set_txdesc_next(sc, TXDESC_PREV(txstart), 708 cpsw_txdesc_paddr(sc, txstart)); 709 if (sc->sc_txeoq) { 710 /* kick the dma engine */ 711 sc->sc_txeoq = false; 712 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 713 cpsw_txdesc_paddr(sc, txstart)); 714 } 715 } 716 KERNHIST_LOG(cpswhist, "end txf %x txh %x txn %x txr %x\n", 717 txfree, sc->sc_txhead, sc->sc_txnext, sc->sc_txrun); 718 } 719 720 static int 721 cpsw_ioctl(struct ifnet *ifp, u_long cmd, void *data) 722 { 723 const int s = splnet(); 724 int error = 0; 725 726 switch (cmd) { 727 default: 728 error = ether_ioctl(ifp, cmd, data); 729 if (error == ENETRESET) { 730 error = 0; 731 } 732 break; 733 } 734 735 splx(s); 736 737 return error; 738 } 739 740 static void 741 cpsw_watchdog(struct ifnet *ifp) 742 { 743 struct cpsw_softc *sc = ifp->if_softc; 744 745 device_printf(sc->sc_dev, "device timeout\n"); 746 747 ifp->if_oerrors++; 748 cpsw_init(ifp); 749 cpsw_start(ifp); 750 } 751 752 static int 753 cpsw_mii_wait(struct cpsw_softc * const sc, int reg) 754 { 755 u_int tries; 756 757 for (tries = 0; tries < 1000; tries++) { 758 if ((cpsw_read_4(sc, reg) & __BIT(31)) == 0) 759 return 0; 760 delay(1); 761 } 762 return ETIMEDOUT; 763 } 764 765 static int 766 cpsw_mii_readreg(device_t dev, int phy, int reg, uint16_t *val) 767 { 768 struct cpsw_softc * const sc = device_private(dev); 769 uint32_t v; 770 771 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 772 return -1; 773 774 cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | 775 ((reg & 0x1F) << 21) | ((phy & 0x1F) << 16)); 776 777 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 778 return -1; 779 780 v = cpsw_read_4(sc, MDIOUSERACCESS0); 781 if (v & __BIT(29)) { 782 *val = v & 0xffff; 783 return 0; 784 } 785 786 return -1; 787 } 788 789 static int 790 cpsw_mii_writereg(device_t dev, int phy, int reg, uint16_t val) 791 { 792 struct cpsw_softc * const sc = device_private(dev); 793 uint32_t v; 794 795 KASSERT((val & 0xffff0000UL) == 0); 796 797 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 798 goto out; 799 800 cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | (1 << 30) | 801 ((reg & 0x1F) << 21) | ((phy & 0x1F) << 16) | val); 802 803 if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0) 804 goto out; 805 806 v = cpsw_read_4(sc, MDIOUSERACCESS0); 807 if ((v & __BIT(29)) == 0) { 808 out: 809 device_printf(sc->sc_dev, "%s error\n", __func__); 810 return -1; 811 } 812 813 return 0; 814 } 815 816 static void 817 cpsw_mii_statchg(struct ifnet *ifp) 818 { 819 return; 820 } 821 822 static int 823 cpsw_new_rxbuf(struct cpsw_softc * const sc, const u_int i) 824 { 825 struct cpsw_ring_data * const rdp = sc->sc_rdp; 826 const u_int h = RXDESC_PREV(i); 827 struct cpsw_cpdma_bd bd; 828 uint32_t * const dw = bd.word; 829 struct mbuf *m; 830 int error = ENOBUFS; 831 832 MGETHDR(m, M_DONTWAIT, MT_DATA); 833 if (m == NULL) { 834 goto reuse; 835 } 836 837 MCLGET(m, M_DONTWAIT); 838 if ((m->m_flags & M_EXT) == 0) { 839 m_freem(m); 840 goto reuse; 841 } 842 843 /* We have a new buffer, prepare it for the ring. */ 844 845 if (rdp->rx_mb[i] != NULL) 846 bus_dmamap_unload(sc->sc_bdt, rdp->rx_dm[i]); 847 848 m->m_len = m->m_pkthdr.len = MCLBYTES; 849 850 rdp->rx_mb[i] = m; 851 852 error = bus_dmamap_load_mbuf(sc->sc_bdt, rdp->rx_dm[i], rdp->rx_mb[i], 853 BUS_DMA_READ | BUS_DMA_NOWAIT); 854 if (error) { 855 device_printf(sc->sc_dev, "can't load rx DMA map %d: %d\n", 856 i, error); 857 } 858 859 bus_dmamap_sync(sc->sc_bdt, rdp->rx_dm[i], 860 0, rdp->rx_dm[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 861 862 error = 0; 863 864 reuse: 865 /* (re-)setup the descriptor */ 866 dw[0] = 0; 867 dw[1] = rdp->rx_dm[i]->dm_segs[0].ds_addr; 868 dw[2] = MIN(0x7ff, rdp->rx_dm[i]->dm_segs[0].ds_len); 869 dw[3] = CPDMA_BD_OWNER; 870 871 cpsw_set_rxdesc(sc, i, &bd); 872 /* and link onto ring */ 873 cpsw_set_rxdesc_next(sc, h, cpsw_rxdesc_paddr(sc, i)); 874 875 return error; 876 } 877 878 static int 879 cpsw_init(struct ifnet *ifp) 880 { 881 struct cpsw_softc * const sc = ifp->if_softc; 882 struct mii_data * const mii = &sc->sc_mii; 883 int i; 884 885 cpsw_stop(ifp, 0); 886 887 sc->sc_txnext = 0; 888 sc->sc_txhead = 0; 889 890 /* Reset wrapper */ 891 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 892 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 893 ; 894 895 /* Reset SS */ 896 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 897 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 898 ; 899 900 /* Clear table and enable ALE */ 901 cpsw_write_4(sc, CPSW_ALE_CONTROL, 902 ALECTL_ENABLE_ALE | ALECTL_CLEAR_TABLE); 903 904 /* Reset and init Sliver port 1 and 2 */ 905 for (i = 0; i < CPSW_ETH_PORTS; i++) { 906 uint32_t macctl; 907 908 /* Reset */ 909 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 910 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 911 ; 912 /* Set Slave Mapping */ 913 cpsw_write_4(sc, CPSW_SL_RX_PRI_MAP(i), 0x76543210); 914 cpsw_write_4(sc, CPSW_PORT_P_TX_PRI_MAP(i+1), 0x33221100); 915 cpsw_write_4(sc, CPSW_SL_RX_MAXLEN(i), 0x5f2); 916 /* Set MAC Address */ 917 cpsw_write_4(sc, CPSW_PORT_P_SA_HI(i+1), 918 sc->sc_enaddr[0] | (sc->sc_enaddr[1] << 8) | 919 (sc->sc_enaddr[2] << 16) | (sc->sc_enaddr[3] << 24)); 920 cpsw_write_4(sc, CPSW_PORT_P_SA_LO(i+1), 921 sc->sc_enaddr[4] | (sc->sc_enaddr[5] << 8)); 922 923 /* Set MACCONTROL for ports 0,1 */ 924 macctl = SLMACCTL_FULLDUPLEX | SLMACCTL_GMII_EN | 925 SLMACCTL_IFCTL_A; 926 if (sc->sc_phy_has_1000t) 927 macctl |= SLMACCTL_GIG; 928 cpsw_write_4(sc, CPSW_SL_MACCONTROL(i), macctl); 929 930 /* Set ALE port to forwarding(3) */ 931 cpsw_write_4(sc, CPSW_ALE_PORTCTL(i+1), 3); 932 } 933 934 /* Set Host Port Mapping */ 935 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210); 936 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0); 937 938 /* Set ALE port to forwarding(3) */ 939 cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 3); 940 941 /* Initialize addrs */ 942 cpsw_ale_update_addresses(sc, 1); 943 944 cpsw_write_4(sc, CPSW_SS_PTYPE, 0); 945 cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7); 946 947 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 948 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 949 ; 950 951 for (i = 0; i < 8; i++) { 952 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0); 953 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0); 954 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0); 955 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0); 956 } 957 958 bus_space_set_region_4(sc->sc_bst, sc->sc_bsh_txdescs, 0, 0, 959 CPSW_CPPI_RAM_TXDESCS_SIZE/4); 960 961 sc->sc_txhead = 0; 962 sc->sc_txnext = 0; 963 964 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0); 965 966 bus_space_set_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, 0, 0, 967 CPSW_CPPI_RAM_RXDESCS_SIZE/4); 968 /* Initialize RX Buffer Descriptors */ 969 cpsw_set_rxdesc_next(sc, RXDESC_PREV(0), 0); 970 for (i = 0; i < CPSW_NRXDESCS; i++) { 971 cpsw_new_rxbuf(sc, i); 972 } 973 sc->sc_rxhead = 0; 974 975 /* turn off flow control */ 976 cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0); 977 978 /* align layer 3 header to 32-bit */ 979 cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, ETHER_ALIGN); 980 981 /* Clear all interrupt Masks */ 982 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF); 983 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF); 984 985 /* Enable TX & RX DMA */ 986 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1); 987 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1); 988 989 /* Enable TX and RX interrupt receive for core 0 */ 990 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 1); 991 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 1); 992 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F); 993 994 /* Enable host Error Interrupt */ 995 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 2); 996 997 /* Enable interrupts for TX and RX Channel 0 */ 998 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1); 999 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 1); 1000 1001 /* Ack stalled irqs */ 1002 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH); 1003 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX); 1004 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX); 1005 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC); 1006 1007 /* Initialize MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */ 1008 /* TODO Calculate MDCLK=CLK/(CLKDIV+1) */ 1009 cpsw_write_4(sc, MDIOCONTROL, 1010 MDIOCTL_ENABLE | MDIOCTL_FAULTENB | MDIOCTL_CLKDIV(0xff)); 1011 1012 mii_mediachg(mii); 1013 1014 /* Write channel 0 RX HDP */ 1015 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(0), cpsw_rxdesc_paddr(sc, 0)); 1016 sc->sc_rxrun = true; 1017 sc->sc_rxeoq = false; 1018 1019 sc->sc_txrun = true; 1020 sc->sc_txeoq = true; 1021 callout_schedule(&sc->sc_tick_ch, hz); 1022 ifp->if_flags |= IFF_RUNNING; 1023 ifp->if_flags &= ~IFF_OACTIVE; 1024 1025 return 0; 1026 } 1027 1028 static void 1029 cpsw_stop(struct ifnet *ifp, int disable) 1030 { 1031 struct cpsw_softc * const sc = ifp->if_softc; 1032 struct cpsw_ring_data * const rdp = sc->sc_rdp; 1033 u_int i; 1034 1035 aprint_debug_dev(sc->sc_dev, "%s: ifp %p disable %d\n", __func__, 1036 ifp, disable); 1037 1038 if ((ifp->if_flags & IFF_RUNNING) == 0) 1039 return; 1040 1041 callout_stop(&sc->sc_tick_ch); 1042 mii_down(&sc->sc_mii); 1043 1044 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 1); 1045 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 1); 1046 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0x0); 1047 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0x0); 1048 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x0); 1049 1050 cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0); 1051 cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0); 1052 i = 0; 1053 while ((sc->sc_txrun || sc->sc_rxrun) && i < 10000) { 1054 delay(10); 1055 if ((sc->sc_txrun == true) && cpsw_txintr(sc) == 0) 1056 sc->sc_txrun = false; 1057 if ((sc->sc_rxrun == true) && cpsw_rxintr(sc) == 0) 1058 sc->sc_rxrun = false; 1059 i++; 1060 } 1061 //printf("%s toredown complete in %u\n", __func__, i); 1062 1063 /* Reset wrapper */ 1064 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 1065 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 1066 ; 1067 1068 /* Reset SS */ 1069 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 1070 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 1071 ; 1072 1073 for (i = 0; i < CPSW_ETH_PORTS; i++) { 1074 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 1075 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 1076 ; 1077 } 1078 1079 /* Reset CPDMA */ 1080 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 1081 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 1082 ; 1083 1084 /* Release any queued transmit buffers. */ 1085 for (i = 0; i < CPSW_NTXDESCS; i++) { 1086 bus_dmamap_unload(sc->sc_bdt, rdp->tx_dm[i]); 1087 m_freem(rdp->tx_mb[i]); 1088 rdp->tx_mb[i] = NULL; 1089 } 1090 1091 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1092 ifp->if_timer = 0; 1093 1094 if (!disable) 1095 return; 1096 1097 for (i = 0; i < CPSW_NRXDESCS; i++) { 1098 bus_dmamap_unload(sc->sc_bdt, rdp->rx_dm[i]); 1099 m_freem(rdp->rx_mb[i]); 1100 rdp->rx_mb[i] = NULL; 1101 } 1102 } 1103 1104 static void 1105 cpsw_tick(void *arg) 1106 { 1107 struct cpsw_softc * const sc = arg; 1108 struct mii_data * const mii = &sc->sc_mii; 1109 const int s = splnet(); 1110 1111 mii_tick(mii); 1112 1113 splx(s); 1114 1115 callout_schedule(&sc->sc_tick_ch, hz); 1116 } 1117 1118 static int 1119 cpsw_rxthintr(void *arg) 1120 { 1121 struct cpsw_softc * const sc = arg; 1122 1123 /* this won't deassert the interrupt though */ 1124 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RXTH); 1125 1126 return 1; 1127 } 1128 1129 static int 1130 cpsw_rxintr(void *arg) 1131 { 1132 struct cpsw_softc * const sc = arg; 1133 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1134 struct cpsw_ring_data * const rdp = sc->sc_rdp; 1135 struct cpsw_cpdma_bd bd; 1136 const uint32_t * const dw = bd.word; 1137 bus_dmamap_t dm; 1138 struct mbuf *m; 1139 u_int i; 1140 u_int len, off; 1141 1142 KERNHIST_FUNC(__func__); 1143 KERNHIST_CALLED_5(cpswhist, sc, 0, 0, 0); 1144 1145 for (;;) { 1146 KASSERT(sc->sc_rxhead < CPSW_NRXDESCS); 1147 1148 i = sc->sc_rxhead; 1149 KERNHIST_LOG(cpswhist, "rxhead %x CP %x\n", i, 1150 cpsw_read_4(sc, CPSW_CPDMA_RX_CP(0)), 0, 0); 1151 dm = rdp->rx_dm[i]; 1152 m = rdp->rx_mb[i]; 1153 1154 KASSERT(dm != NULL); 1155 KASSERT(m != NULL); 1156 1157 cpsw_get_rxdesc(sc, i, &bd); 1158 1159 if (ISSET(dw[3], CPDMA_BD_OWNER)) 1160 break; 1161 1162 if (ISSET(dw[3], CPDMA_BD_TDOWNCMPLT)) { 1163 sc->sc_rxrun = false; 1164 return 1; 1165 } 1166 1167 if ((dw[3] & (CPDMA_BD_SOP | CPDMA_BD_EOP)) != 1168 (CPDMA_BD_SOP | CPDMA_BD_EOP)) { 1169 //Debugger(); 1170 } 1171 1172 bus_dmamap_sync(sc->sc_bdt, dm, 0, dm->dm_mapsize, 1173 BUS_DMASYNC_POSTREAD); 1174 1175 if (cpsw_new_rxbuf(sc, i) != 0) { 1176 /* drop current packet, reuse buffer for new */ 1177 ifp->if_ierrors++; 1178 goto next; 1179 } 1180 1181 off = __SHIFTOUT(dw[2], (uint32_t)__BITS(26, 16)); 1182 len = __SHIFTOUT(dw[3], (uint32_t)__BITS(10, 0)); 1183 1184 if (ISSET(dw[3], CPDMA_BD_PASSCRC)) 1185 len -= ETHER_CRC_LEN; 1186 1187 m_set_rcvif(m, ifp); 1188 m->m_pkthdr.len = m->m_len = len; 1189 m->m_data += off; 1190 1191 if_percpuq_enqueue(ifp->if_percpuq, m); 1192 1193 next: 1194 sc->sc_rxhead = RXDESC_NEXT(sc->sc_rxhead); 1195 if (ISSET(dw[3], CPDMA_BD_EOQ)) { 1196 sc->sc_rxeoq = true; 1197 break; 1198 } else { 1199 sc->sc_rxeoq = false; 1200 } 1201 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(0), 1202 cpsw_rxdesc_paddr(sc, i)); 1203 } 1204 1205 if (sc->sc_rxeoq) { 1206 device_printf(sc->sc_dev, "rxeoq\n"); 1207 //Debugger(); 1208 } 1209 1210 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_RX); 1211 1212 return 1; 1213 } 1214 1215 static int 1216 cpsw_txintr(void *arg) 1217 { 1218 struct cpsw_softc * const sc = arg; 1219 struct ifnet * const ifp = &sc->sc_ec.ec_if; 1220 struct cpsw_ring_data * const rdp = sc->sc_rdp; 1221 struct cpsw_cpdma_bd bd; 1222 const uint32_t * const dw = bd.word; 1223 bool handled = false; 1224 uint32_t tx0_cp; 1225 u_int cpi; 1226 1227 KERNHIST_FUNC(__func__); 1228 KERNHIST_CALLED_5(cpswhist, sc, 0, 0, 0); 1229 1230 KASSERT(sc->sc_txrun); 1231 1232 KERNHIST_LOG(cpswhist, "before txnext %x txhead %x txrun %x\n", 1233 sc->sc_txnext, sc->sc_txhead, sc->sc_txrun, 0); 1234 1235 tx0_cp = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)); 1236 1237 if (tx0_cp == 0xfffffffc) { 1238 /* Teardown, ack it */ 1239 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(0), 0xfffffffc); 1240 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 0); 1241 sc->sc_txrun = false; 1242 return 0; 1243 } 1244 1245 for (;;) { 1246 tx0_cp = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)); 1247 cpi = (tx0_cp - sc->sc_txdescs_pa) / sizeof(struct cpsw_cpdma_bd); 1248 KASSERT(sc->sc_txhead < CPSW_NTXDESCS); 1249 1250 KERNHIST_LOG(cpswhist, "txnext %x txhead %x txrun %x cpi %x\n", 1251 sc->sc_txnext, sc->sc_txhead, sc->sc_txrun, cpi); 1252 1253 cpsw_get_txdesc(sc, sc->sc_txhead, &bd); 1254 1255 if (dw[2] == 0) { 1256 //Debugger(); 1257 } 1258 1259 if (ISSET(dw[3], CPDMA_BD_SOP) == 0) 1260 goto next; 1261 1262 if (ISSET(dw[3], CPDMA_BD_OWNER)) { 1263 printf("pwned %x %x %x\n", cpi, sc->sc_txhead, 1264 sc->sc_txnext); 1265 break; 1266 } 1267 1268 if (ISSET(dw[3], CPDMA_BD_TDOWNCMPLT)) { 1269 sc->sc_txrun = false; 1270 return 1; 1271 } 1272 1273 bus_dmamap_sync(sc->sc_bdt, rdp->tx_dm[sc->sc_txhead], 1274 0, rdp->tx_dm[sc->sc_txhead]->dm_mapsize, 1275 BUS_DMASYNC_POSTWRITE); 1276 bus_dmamap_unload(sc->sc_bdt, rdp->tx_dm[sc->sc_txhead]); 1277 1278 m_freem(rdp->tx_mb[sc->sc_txhead]); 1279 rdp->tx_mb[sc->sc_txhead] = NULL; 1280 1281 ifp->if_opackets++; 1282 1283 handled = true; 1284 1285 ifp->if_flags &= ~IFF_OACTIVE; 1286 1287 next: 1288 if (ISSET(dw[3], CPDMA_BD_EOP) && ISSET(dw[3], CPDMA_BD_EOQ)) { 1289 sc->sc_txeoq = true; 1290 } 1291 if (sc->sc_txhead == cpi) { 1292 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(0), 1293 cpsw_txdesc_paddr(sc, cpi)); 1294 sc->sc_txhead = TXDESC_NEXT(sc->sc_txhead); 1295 break; 1296 } 1297 sc->sc_txhead = TXDESC_NEXT(sc->sc_txhead); 1298 if (ISSET(dw[3], CPDMA_BD_EOP) && ISSET(dw[3], CPDMA_BD_EOQ)) { 1299 sc->sc_txeoq = true; 1300 break; 1301 } 1302 } 1303 1304 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_TX); 1305 1306 if ((sc->sc_txnext != sc->sc_txhead) && sc->sc_txeoq) { 1307 if (cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)) == 0) { 1308 sc->sc_txeoq = false; 1309 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(0), 1310 cpsw_txdesc_paddr(sc, sc->sc_txhead)); 1311 } 1312 } 1313 1314 KERNHIST_LOG(cpswhist, "after txnext %x txhead %x txrun %x\n", 1315 sc->sc_txnext, sc->sc_txhead, sc->sc_txrun, 0); 1316 KERNHIST_LOG(cpswhist, "CP %x HDP %x\n", 1317 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)), 1318 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)), 0, 0); 1319 1320 if (handled && sc->sc_txnext == sc->sc_txhead) 1321 ifp->if_timer = 0; 1322 1323 if (handled) 1324 if_schedule_deferred_start(ifp); 1325 1326 return handled; 1327 } 1328 1329 static int 1330 cpsw_miscintr(void *arg) 1331 { 1332 struct cpsw_softc * const sc = arg; 1333 uint32_t miscstat; 1334 uint32_t dmastat; 1335 uint32_t stat; 1336 1337 miscstat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0)); 1338 device_printf(sc->sc_dev, "%s %x FIRE\n", __func__, miscstat); 1339 1340 #define CPSW_MISC_HOST_PEND __BIT32(2) 1341 #define CPSW_MISC_STAT_PEND __BIT32(3) 1342 1343 if (ISSET(miscstat, CPSW_MISC_HOST_PEND)) { 1344 /* Host Error */ 1345 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 1346 printf("CPSW_CPDMA_DMA_INTSTAT_MASKED %x\n", dmastat); 1347 1348 printf("rxhead %02x\n", sc->sc_rxhead); 1349 1350 stat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS); 1351 printf("CPSW_CPDMA_DMASTATUS %x\n", stat); 1352 stat = cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)); 1353 printf("CPSW_CPDMA_TX0_HDP %x\n", stat); 1354 stat = cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)); 1355 printf("CPSW_CPDMA_TX0_CP %x\n", stat); 1356 stat = cpsw_read_4(sc, CPSW_CPDMA_RX_HDP(0)); 1357 printf("CPSW_CPDMA_RX0_HDP %x\n", stat); 1358 stat = cpsw_read_4(sc, CPSW_CPDMA_RX_CP(0)); 1359 printf("CPSW_CPDMA_RX0_CP %x\n", stat); 1360 1361 //Debugger(); 1362 1363 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, dmastat); 1364 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 1365 printf("CPSW_CPDMA_DMA_INTSTAT_MASKED %x\n", dmastat); 1366 } 1367 1368 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, CPSW_INTROFF_MISC); 1369 1370 return 1; 1371 } 1372 1373 /* 1374 * 1375 * ALE support routines. 1376 * 1377 */ 1378 1379 static void 1380 cpsw_ale_entry_init(uint32_t *ale_entry) 1381 { 1382 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 1383 } 1384 1385 static void 1386 cpsw_ale_entry_set_mac(uint32_t *ale_entry, const uint8_t *mac) 1387 { 1388 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 1389 ale_entry[1] = mac[0] << 8 | mac[1]; 1390 } 1391 1392 static void 1393 cpsw_ale_entry_set_bcast_mac(uint32_t *ale_entry) 1394 { 1395 ale_entry[0] = 0xffffffff; 1396 ale_entry[1] = 0x0000ffff; 1397 } 1398 1399 static void 1400 cpsw_ale_entry_set(uint32_t *ale_entry, ale_entry_field_t field, uint32_t val) 1401 { 1402 /* Entry type[61:60] is addr entry(1), Mcast fwd state[63:62] is fw(3)*/ 1403 switch (field) { 1404 case ALE_ENTRY_TYPE: 1405 /* [61:60] */ 1406 ale_entry[1] |= (val & 0x3) << 28; 1407 break; 1408 case ALE_MCAST_FWD_STATE: 1409 /* [63:62] */ 1410 ale_entry[1] |= (val & 0x3) << 30; 1411 break; 1412 case ALE_PORT_MASK: 1413 /* [68:66] */ 1414 ale_entry[2] |= (val & 0x7) << 2; 1415 break; 1416 case ALE_PORT_NUMBER: 1417 /* [67:66] */ 1418 ale_entry[2] |= (val & 0x3) << 2; 1419 break; 1420 default: 1421 panic("Invalid ALE entry field: %d\n", field); 1422 } 1423 1424 return; 1425 } 1426 1427 static bool 1428 cpsw_ale_entry_mac_match(const uint32_t *ale_entry, const uint8_t *mac) 1429 { 1430 return (((ale_entry[1] >> 8) & 0xff) == mac[0]) && 1431 (((ale_entry[1] >> 0) & 0xff) == mac[1]) && 1432 (((ale_entry[0] >>24) & 0xff) == mac[2]) && 1433 (((ale_entry[0] >>16) & 0xff) == mac[3]) && 1434 (((ale_entry[0] >> 8) & 0xff) == mac[4]) && 1435 (((ale_entry[0] >> 0) & 0xff) == mac[5]); 1436 } 1437 1438 static void 1439 cpsw_ale_set_outgoing_mac(struct cpsw_softc *sc, int port, const uint8_t *mac) 1440 { 1441 cpsw_write_4(sc, CPSW_PORT_P_SA_HI(port), 1442 mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]); 1443 cpsw_write_4(sc, CPSW_PORT_P_SA_LO(port), 1444 mac[5] << 8 | mac[4]); 1445 } 1446 1447 static void 1448 cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 1449 { 1450 cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023); 1451 ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0); 1452 ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1); 1453 ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2); 1454 } 1455 1456 static void 1457 cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, 1458 const uint32_t *ale_entry) 1459 { 1460 cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]); 1461 cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]); 1462 cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]); 1463 cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023)); 1464 } 1465 1466 static int 1467 cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc) 1468 { 1469 int i; 1470 uint32_t ale_entry[3]; 1471 1472 /* First two entries are link address and broadcast. */ 1473 for (i = 2; i < CPSW_MAX_ALE_ENTRIES; i++) { 1474 cpsw_ale_read_entry(sc, i, ale_entry); 1475 if (((ale_entry[1] >> 28) & 3) == 1 && /* Address entry */ 1476 ((ale_entry[1] >> 8) & 1) == 1) { /* MCast link addr */ 1477 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 1478 cpsw_ale_write_entry(sc, i, ale_entry); 1479 } 1480 } 1481 return CPSW_MAX_ALE_ENTRIES; 1482 } 1483 1484 static int 1485 cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmask, uint8_t *mac) 1486 { 1487 int free_index = -1, matching_index = -1, i; 1488 uint32_t ale_entry[3]; 1489 1490 /* Find a matching entry or a free entry. */ 1491 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 1492 cpsw_ale_read_entry(sc, i, ale_entry); 1493 1494 /* Entry Type[61:60] is 0 for free entry */ 1495 if (free_index < 0 && ((ale_entry[1] >> 28) & 3) == 0) { 1496 free_index = i; 1497 } 1498 1499 if (cpsw_ale_entry_mac_match(ale_entry, mac)) { 1500 matching_index = i; 1501 break; 1502 } 1503 } 1504 1505 if (matching_index < 0) { 1506 if (free_index < 0) 1507 return ENOMEM; 1508 i = free_index; 1509 } 1510 1511 cpsw_ale_entry_init(ale_entry); 1512 1513 cpsw_ale_entry_set_mac(ale_entry, mac); 1514 cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS); 1515 cpsw_ale_entry_set(ale_entry, ALE_MCAST_FWD_STATE, ALE_FWSTATE_FWONLY); 1516 cpsw_ale_entry_set(ale_entry, ALE_PORT_MASK, portmask); 1517 1518 cpsw_ale_write_entry(sc, i, ale_entry); 1519 1520 return 0; 1521 } 1522 1523 static int 1524 cpsw_ale_update_addresses(struct cpsw_softc *sc, int purge) 1525 { 1526 uint8_t *mac = sc->sc_enaddr; 1527 uint32_t ale_entry[3]; 1528 int i; 1529 struct ethercom * const ec = &sc->sc_ec; 1530 struct ether_multi *ifma; 1531 1532 cpsw_ale_entry_init(ale_entry); 1533 /* Route incoming packets for our MAC address to Port 0 (host). */ 1534 /* For simplicity, keep this entry at table index 0 in the ALE. */ 1535 cpsw_ale_entry_set_mac(ale_entry, mac); 1536 cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS); 1537 cpsw_ale_entry_set(ale_entry, ALE_PORT_NUMBER, 0); 1538 cpsw_ale_write_entry(sc, 0, ale_entry); 1539 1540 /* Set outgoing MAC Address for Ports 1 and 2. */ 1541 for (i = CPSW_CPPI_PORTS; i < (CPSW_ETH_PORTS + CPSW_CPPI_PORTS); ++i) 1542 cpsw_ale_set_outgoing_mac(sc, i, mac); 1543 1544 /* Keep the broadcast address at table entry 1. */ 1545 cpsw_ale_entry_init(ale_entry); 1546 cpsw_ale_entry_set_bcast_mac(ale_entry); 1547 cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS); 1548 cpsw_ale_entry_set(ale_entry, ALE_MCAST_FWD_STATE, ALE_FWSTATE_FWONLY); 1549 cpsw_ale_entry_set(ale_entry, ALE_PORT_MASK, ALE_PORT_MASK_ALL); 1550 cpsw_ale_write_entry(sc, 1, ale_entry); 1551 1552 /* SIOCDELMULTI doesn't specify the particular address 1553 being removed, so we have to remove all and rebuild. */ 1554 if (purge) 1555 cpsw_ale_remove_all_mc_entries(sc); 1556 1557 /* Set other multicast addrs desired. */ 1558 LIST_FOREACH(ifma, &ec->ec_multiaddrs, enm_list) { 1559 cpsw_ale_mc_entry_set(sc, ALE_PORT_MASK_ALL, ifma->enm_addrlo); 1560 } 1561 1562 return 0; 1563 } 1564
Indexes created Tue Sep 30 11:09:46 GMT 2025