if_cpswreg.h revision 1.1
1 /*- 2 * Copyright (c) 2012 Damjan Marion <dmarion (at) Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _IF_CPSWREG_H 30 #define _IF_CPSWREG_H 31 32 #define CPSW_ETH_PORTS 2 33 #define CPSW_CPPI_PORTS 1 34 35 #define CPSW_SS_OFFSET 0x0000 36 #define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00) 37 #define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08) 38 #define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C) 39 #define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10) 40 #define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24) 41 #define CPSW_SS_RGMII_CTL (CPSW_SS_OFFSET + 0x88) 42 43 #define CPSW_PORT_OFFSET 0x0100 44 #define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100)) 45 #define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C) 46 #define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020) 47 #define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100)) 48 #define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100)) 49 50 #define CPSW_GMII_SEL 0x0650 51 52 #define CPSW_CPDMA_OFFSET 0x0800 53 #define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04) 54 #define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08) 55 #define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14) 56 #define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18) 57 #define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c) 58 #define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20) 59 #define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24) 60 #define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28) 61 #define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80) 62 #define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84) 63 #define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88) 64 #define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C) 65 #define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94) 66 #define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0) 67 #define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4) 68 #define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8) 69 #define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc) 70 #define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0) 71 #define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4) 72 #define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8) 73 #define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC) 74 #define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 + ((p) * 0x04)) 75 76 #define CPSW_STATS_OFFSET 0x0900 77 78 #define CPSW_STATERAM_OFFSET 0x0A00 79 #define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 + ((p) * 0x04)) 80 #define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 + ((p) * 0x04)) 81 #define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 + ((p) * 0x04)) 82 #define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 + ((p) * 0x04)) 83 84 #define CPSW_CPTS_OFFSET 0x0C00 85 86 #define CPSW_ALE_OFFSET 0x0D00 87 #define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08) 88 #define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20) 89 #define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34) 90 #define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38) 91 #define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C) 92 #define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04)) 93 94 #define CPSW_SL_OFFSET 0x0D80 95 #define CPSW_SL_IDVER(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x00) 96 #define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04) 97 #define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08) 98 #define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C) 99 #define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10) 100 #define CPSW_SL_BOFFTEST(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x14) 101 #define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18) 102 #define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C) 103 #define CPSW_SL_EMCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x20) 104 #define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24) 105 #define CPSW_SL_TX_GAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x28) 106 107 #define MDIO_OFFSET 0x1000 108 #define MDIOCONTROL (MDIO_OFFSET + 0x04) 109 #define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80) 110 #define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84) 111 112 #define CPSW_WR_OFFSET 0x1200 113 #define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04) 114 #define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08) 115 #define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c) 116 #define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x10) 117 #define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x14) 118 #define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18) 119 #define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C) 120 #define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40) 121 #define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44) 122 #define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48) 123 #define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C) 124 125 #define CPSW_CPPI_RAM_OFFSET 0x2000 126 127 128 #define __BIT32(x) ((uint32_t)__BIT(x)) 129 #define __BITS32(x, y) ((uint32_t)__BITS((x), (y))) 130 131 /* flags for descriptor word 3 */ 132 #define CPDMA_BD_SOP __BIT32(31) 133 #define CPDMA_BD_EOP __BIT32(30) 134 #define CPDMA_BD_OWNER __BIT32(29) 135 #define CPDMA_BD_EOQ __BIT32(28) 136 #define CPDMA_BD_TDOWNCMPLT __BIT32(27) 137 #define CPDMA_BD_PASSCRC __BIT32(26) 138 139 #define CPDMA_BD_LONG __BIT32(25) /* Rx descriptor only */ 140 #define CPDMA_BD_SHORT __BIT32(24) 141 #define CPDMA_BD_MAC_CTL __BIT32(23) 142 #define CPDMA_BD_OVERRUN __BIT32(22) 143 #define CPDMA_BD_PKT_ERR_MASK __BITS32(21,20) 144 #define CPDMA_BD_RX_VLAN_ENCAP __BIT32(19) 145 #define CPDMA_BD_FROM_PORT __BITS32(18,16) 146 147 #define CPDMA_BD_TO_PORT_EN __BIT32(20) /* Tx descriptor only */ 148 #define CPDMA_BD_TO_PORT __BITS32(17,16) 149 150 struct cpsw_cpdma_bd { 151 uint32_t word[4]; 152 } __packed __aligned(4); 153 154 /* Interrupt offsets */ 155 #define CPSW_INTROFF_RXTH 0 156 #define CPSW_INTROFF_RX 1 157 #define CPSW_INTROFF_TX 2 158 #define CPSW_INTROFF_MISC 3 159 160 /* MDIOCONTROL Register Field */ 161 #define MDIOCTL_IDLE __BIT32(31) 162 #define MDIOCTL_ENABLE __BIT32(30) 163 #define MDIOCTL_HIGHEST_USER_CHANNEL(val) ((0xf & (val)) << 24) 164 #define MDIOCTL_PREAMBLE __BIT32(20) 165 #define MDIOCTL_FAULT __BIT32(19) 166 #define MDIOCTL_FAULTENB __BIT32(18) 167 #define MDIOCTL_INTTESTENB __BIT32(17) 168 #define MDIOCTL_CLKDIV(val) (0xff & (val)) 169 170 /* ALE Control Register Field */ 171 #define ALECTL_ENABLE_ALE __BIT32(31) 172 #define ALECTL_CLEAR_TABLE __BIT32(30) 173 #define ALECTL_AGE_OUT_NOW __BIT32(29) 174 #define ALECTL_EN_P0_UNI_FLOOD __BIT32(8) 175 #define ALECTL_LEARN_NO_VID __BIT32(7) 176 #define ALECTL_EN_VID0_MODE __BIT32(6) 177 #define ALECTL_ENABLE_OUI_DENY __BIT32(5) 178 #define ALECTL_BYPASS __BIT32(4) 179 #define ALECTL_RATE_LIMIT_TX __BIT32(3) 180 #define ALECTL_VLAN_AWARE __BIT32(2) 181 #define ALECTL_ENABLE_AUTH_MODE __BIT32(1) 182 #define ALECTL_ENABLE_RATE_LIMIT __BIT32(0) 183 184 /* GMII_SEL Register Field */ 185 #define GMIISEL_RMII2_IO_CLK_EN __BIT32(7) 186 #define GMIISEL_RMII1_IO_CLK_EN __BIT32(6) 187 #define GMIISEL_RGMII2_IDMODE __BIT32(5) 188 #define GMIISEL_RGMII1_IDMODE __BIT32(4) 189 #define GMIISEL_GMII2_SEL(val) ((0x3 & (val)) << 2) 190 #define GMIISEL_GMII1_SEL(val) ((0x3 & (val)) << 0) 191 #define GMII_MODE 0 192 #define RMII_MODE 1 193 #define RGMII_MODE 2 194 195 /* Sliver MACCONTROL Register Field */ 196 #define SLMACCTL_RX_CMF_EN __BIT32(24) 197 #define SLMACCTL_RX_CSF_EN __BIT32(23) 198 #define SLMACCTL_RX_CEF_EN __BIT32(22) 199 #define SLMACCTL_TX_SHORT_GAP_LIM_EN __BIT32(21) 200 #define SLMACCTL_EXT_EN __BIT32(18) 201 #define SLMACCTL_GIG_FORCE __BIT32(17) 202 #define SLMACCTL_IFCTL_B __BIT32(16) 203 #define SLMACCTL_IFCTL_A __BIT32(15) 204 #define SLMACCTL_CMD_IDLE __BIT32(11) 205 #define SLMACCTL_TX_SHORT_GAP_EN __BIT32(10) 206 #define SLMACCTL_GIG __BIT32(7) 207 #define SLMACCTL_TX_PACE __BIT32(6) 208 #define SLMACCTL_GMII_EN __BIT32(5) 209 #define SLMACCTL_TX_FLOW_EN __BIT32(4) 210 #define SLMACCTL_RX_FLOW_EN __BIT32(3) 211 #define SLMACCTL_MTEST __BIT32(2) 212 #define SLMACCTL_LOOPBACK __BIT32(1) 213 #define SLMACCTL_FULLDUPLEX __BIT32(0) 214 215 /* ALE Address Table Entry Field */ 216 typedef enum { 217 ALE_ENTRY_TYPE, 218 ALE_MCAST_FWD_STATE, 219 ALE_PORT_MASK, 220 ALE_PORT_NUMBER, 221 } ale_entry_field_t; 222 223 #define ALE_TYPE_FREE 0 224 #define ALE_TYPE_ADDRESS 1 225 #define ALE_TYPE_VLAN 2 226 #define ALE_TYPE_VLAN_ADDRESS 3 227 228 /* 229 * The port state(s) required for the received port on a destination address lookup 230 * in order for the multicast packet to be forwarded to the transmit port(s) 231 */ 232 #define ALE_FWSTATE_ALL 1 /* Blocking/Forwarding/Learning */ 233 #define ALE_FWSTATE_NOBLOCK 2 /* Forwarding/Learning */ 234 #define ALE_FWSTATE_FWONLY 3 /* Forwarding */ 235 236 #define ALE_PORT_MASK_ALL 7 237 238 #endif /*_IF_CPSWREG_H */ 239
Indexes created Thu Oct 02 10:09:58 GMT 2025