omap3_cm.c revision 1.1
1 /* $NetBSD: omap3_cm.c,v 1.1 2019/10/29 22:19:13 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: omap3_cm.c,v 1.1 2019/10/29 22:19:13 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #define TI_PRCM_PRIVATE 41 #include <arm/ti/ti_prcm.h> 42 43 #define CM_CORE1_BASE 0x0a00 44 #define CM_CORE3_BASE 0x0a08 45 #define CM_WKUP_BASE 0x0c00 46 #define CM_PER_BASE 0x1000 47 #define CM_USBHOST_BASE 0x1400 48 49 #define CM_FCLKEN 0x00 50 #define CM_ICLKEN 0x10 51 52 static int omap3_cm_match(device_t, cfdata_t, void *); 53 static void omap3_cm_attach(device_t, device_t, void *); 54 55 static int 56 omap3_cm_hwmod_enable(struct ti_prcm_softc *sc, struct ti_prcm_clk *tc, int enable) 57 { 58 uint32_t val; 59 60 val = PRCM_READ(sc, tc->u.hwmod.reg + CM_FCLKEN); 61 if (enable) 62 val |= tc->u.hwmod.mask; 63 else 64 val &= ~tc->u.hwmod.mask; 65 PRCM_WRITE(sc, tc->u.hwmod.reg + CM_FCLKEN, val); 66 67 val = PRCM_READ(sc, tc->u.hwmod.reg + CM_ICLKEN); 68 if (enable) 69 val |= tc->u.hwmod.mask; 70 else 71 val &= ~tc->u.hwmod.mask; 72 PRCM_WRITE(sc, tc->u.hwmod.reg + CM_ICLKEN, val); 73 74 return 0; 75 } 76 77 #define OMAP3_CM_HWMOD_CORE1(_name, _bit, _parent) \ 78 TI_PRCM_HWMOD_MASK((_name), CM_CORE1_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable) 79 #define OMAP3_CM_HWMOD_CORE3(_name, _bit, _parent) \ 80 TI_PRCM_HWMOD_MASK((_name), CM_CORE3_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable) 81 #define OMAP3_CM_HWMOD_WKUP(_name, _bit, _parent) \ 82 TI_PRCM_HWMOD_MASK((_name), CM_WKUP_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable) 83 #define OMAP3_CM_HWMOD_PER(_name, _bit, _parent) \ 84 TI_PRCM_HWMOD_MASK((_name), CM_PER_BASE, __BIT(_bit), (_parent), omap3_cm_hwmod_enable) 85 #define OMAP3_CM_HWMOD_USBHOST(_name, _mask, _parent) \ 86 TI_PRCM_HWMOD_MASK((_name), CM_USBHOST_BASE, (_mask), (_parent), omap3_cm_hwmod_enable) 87 88 static const char * const compatible[] = { 89 "ti,omap3-cm", 90 NULL 91 }; 92 93 CFATTACH_DECL_NEW(omap3_cm, sizeof(struct ti_prcm_softc), 94 omap3_cm_match, omap3_cm_attach, NULL, NULL); 95 96 static struct ti_prcm_clk omap3_cm_clks[] = { 97 /* XXX until we get a proper clock tree */ 98 TI_PRCM_FIXED("FIXED_32K", 32768), 99 TI_PRCM_FIXED("FIXED_48MHZ", 48000000), 100 TI_PRCM_FIXED("FIXED_96MHZ", 96000000), 101 TI_PRCM_FIXED_FACTOR("PERIPH_CLK", 1, 1, "FIXED_48MHZ"), 102 TI_PRCM_FIXED_FACTOR("MMC_CLK", 1, 1, "FIXED_96MHZ"), 103 104 OMAP3_CM_HWMOD_CORE1("usb_otg_hs", 4, "PERIPH_CLK"), 105 OMAP3_CM_HWMOD_CORE1("mcbsp1", 9, "PERIPH_CLK"), 106 OMAP3_CM_HWMOD_CORE1("mcbsp5", 10, "PERIPH_CLK"), 107 OMAP3_CM_HWMOD_CORE1("timer10", 11, "PERIPH_CLK"), 108 OMAP3_CM_HWMOD_CORE1("timer11", 12, "PERIPH_CLK"), 109 OMAP3_CM_HWMOD_CORE1("uart1", 13, "PERIPH_CLK"), 110 OMAP3_CM_HWMOD_CORE1("uart2", 14, "PERIPH_CLK"), 111 OMAP3_CM_HWMOD_CORE1("i2c1", 15, "PERIPH_CLK"), 112 OMAP3_CM_HWMOD_CORE1("i2c2", 16, "PERIPH_CLK"), 113 OMAP3_CM_HWMOD_CORE1("i2c3", 17, "PERIPH_CLK"), 114 OMAP3_CM_HWMOD_CORE1("mcspi1", 18, "PERIPH_CLK"), 115 OMAP3_CM_HWMOD_CORE1("mcspi2", 19, "PERIPH_CLK"), 116 OMAP3_CM_HWMOD_CORE1("mcspi3", 20, "PERIPH_CLK"), 117 OMAP3_CM_HWMOD_CORE1("mcspi4", 21, "PERIPH_CLK"), 118 OMAP3_CM_HWMOD_CORE1("hdq1w", 22, "PERIPH_CLK"), 119 OMAP3_CM_HWMOD_CORE1("mmc1", 24, "MMC_CLK"), 120 OMAP3_CM_HWMOD_CORE1("mmc2", 25, "MMC_CLK"), 121 OMAP3_CM_HWMOD_CORE1("mmc3", 30, "MMC_CLK"), 122 123 OMAP3_CM_HWMOD_CORE3("usb_tll_hs", 2, "PERIPH_CLK"), 124 125 OMAP3_CM_HWMOD_WKUP("timer1", 0, "PERIPH_CLK"), 126 OMAP3_CM_HWMOD_WKUP("counter_32k", 2, "FIXED_32K"), 127 OMAP3_CM_HWMOD_WKUP("gpio1", 3, "PERIPH_CLK"), 128 OMAP3_CM_HWMOD_WKUP("wd_timer2", 5, "FIXED_32K"), 129 130 OMAP3_CM_HWMOD_PER("mcbsp2", 0, "PERIPH_CLK"), 131 OMAP3_CM_HWMOD_PER("mcbsp3", 1, "PERIPH_CLK"), 132 OMAP3_CM_HWMOD_PER("mcbsp4", 2, "PERIPH_CLK"), 133 OMAP3_CM_HWMOD_PER("timer2", 3, "PERIPH_CLK"), 134 OMAP3_CM_HWMOD_PER("timer3", 4, "PERIPH_CLK"), 135 OMAP3_CM_HWMOD_PER("timer4", 5, "PERIPH_CLK"), 136 OMAP3_CM_HWMOD_PER("timer5", 6, "PERIPH_CLK"), 137 OMAP3_CM_HWMOD_PER("timer6", 7, "PERIPH_CLK"), 138 OMAP3_CM_HWMOD_PER("timer7", 8, "PERIPH_CLK"), 139 OMAP3_CM_HWMOD_PER("timer8", 9, "PERIPH_CLK"), 140 OMAP3_CM_HWMOD_PER("timer9", 10, "PERIPH_CLK"), 141 OMAP3_CM_HWMOD_PER("uart3", 11, "PERIPH_CLK"), 142 OMAP3_CM_HWMOD_PER("wd_timer3", 12, "PERIPH_CLK"), 143 OMAP3_CM_HWMOD_PER("gpio2", 13, "PERIPH_CLK"), 144 OMAP3_CM_HWMOD_PER("gpio3", 14, "PERIPH_CLK"), 145 OMAP3_CM_HWMOD_PER("gpio4", 15, "PERIPH_CLK"), 146 OMAP3_CM_HWMOD_PER("gpio5", 16, "PERIPH_CLK"), 147 OMAP3_CM_HWMOD_PER("gpio6", 17, "PERIPH_CLK"), 148 149 OMAP3_CM_HWMOD_USBHOST("usb_host_hs", __BITS(1,0), "PERIPH_CLK"), 150 }; 151 152 static int 153 omap3_cm_match(device_t parent, cfdata_t cf, void *aux) 154 { 155 struct fdt_attach_args * const faa = aux; 156 157 return of_match_compatible(faa->faa_phandle, compatible); 158 } 159 160 static void 161 omap3_cm_attach(device_t parent, device_t self, void *aux) 162 { 163 struct ti_prcm_softc * const sc = device_private(self); 164 struct fdt_attach_args * const faa = aux; 165 int clocks; 166 167 sc->sc_dev = self; 168 sc->sc_phandle = faa->faa_phandle; 169 sc->sc_bst = faa->faa_bst; 170 171 sc->sc_clks = omap3_cm_clks; 172 sc->sc_nclks = __arraycount(omap3_cm_clks); 173 174 if (ti_prcm_attach(sc) != 0) 175 return; 176 177 aprint_naive("\n"); 178 aprint_normal(": OMAP3xxx CM\n"); 179 180 clocks = of_find_firstchild_byname(sc->sc_phandle, "clocks"); 181 if (clocks > 0) 182 fdt_add_bus(self, clocks, faa); 183 } 184
Indexes created Tue Sep 30 11:09:46 GMT 2025