ti_dpll_clock.c revision 1.2.2.3
1 1.2.2.3 martin /* $NetBSD: ti_dpll_clock.c,v 1.2.2.3 2020/06/07 13:28:02 martin Exp $ */ 2 1.2.2.2 martin 3 1.2.2.2 martin /*- 4 1.2.2.2 martin * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 1.2.2.2 martin * All rights reserved. 6 1.2.2.2 martin * 7 1.2.2.2 martin * Redistribution and use in source and binary forms, with or without 8 1.2.2.2 martin * modification, are permitted provided that the following conditions 9 1.2.2.2 martin * are met: 10 1.2.2.2 martin * 1. Redistributions of source code must retain the above copyright 11 1.2.2.2 martin * notice, this list of conditions and the following disclaimer. 12 1.2.2.2 martin * 2. Redistributions in binary form must reproduce the above copyright 13 1.2.2.2 martin * notice, this list of conditions and the following disclaimer in the 14 1.2.2.2 martin * documentation and/or other materials provided with the distribution. 15 1.2.2.2 martin * 16 1.2.2.2 martin * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.2.2.2 martin * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.2.2.2 martin * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.2.2.2 martin * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.2.2.2 martin * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.2.2.2 martin * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.2.2.2 martin * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.2.2.2 martin * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.2.2.2 martin * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.2.2.2 martin * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.2.2.2 martin * SUCH DAMAGE. 27 1.2.2.2 martin */ 28 1.2.2.2 martin 29 1.2.2.2 martin #include <sys/cdefs.h> 30 1.2.2.3 martin __KERNEL_RCSID(0, "$NetBSD: ti_dpll_clock.c,v 1.2.2.3 2020/06/07 13:28:02 martin Exp $"); 31 1.2.2.2 martin 32 1.2.2.2 martin #include <sys/param.h> 33 1.2.2.2 martin #include <sys/systm.h> 34 1.2.2.2 martin #include <sys/device.h> 35 1.2.2.2 martin #include <sys/kmem.h> 36 1.2.2.2 martin #include <sys/bus.h> 37 1.2.2.2 martin 38 1.2.2.2 martin #include <dev/clk/clk_backend.h> 39 1.2.2.2 martin 40 1.2.2.2 martin #include <dev/fdt/fdtvar.h> 41 1.2.2.2 martin 42 1.2.2.2 martin #define DPLL_MULT __BITS(18,8) 43 1.2.2.2 martin #define DPLL_DIV __BITS(6,0) 44 1.2.2.2 martin 45 1.2.2.2 martin #define AM3_ST_MN_BYPASS __BIT(8) 46 1.2.2.2 martin #define AM3_ST_DPLL_CLK __BIT(0) 47 1.2.2.2 martin 48 1.2.2.2 martin #define AM3_DPLL_EN __BITS(2,0) 49 1.2.2.2 martin #define AM3_DPLL_EN_NM_BYPASS 4 50 1.2.2.2 martin #define AM3_DPLL_EN_LOCK 7 51 1.2.2.2 martin 52 1.2.2.2 martin #define OMAP3_ST_MPU_CLK __BIT(0) 53 1.2.2.2 martin 54 1.2.2.2 martin #define OMAP3_EN_MPU_DPLL __BITS(2,0) 55 1.2.2.2 martin #define OMAP3_EN_MPU_DPLL_BYPASS 5 56 1.2.2.2 martin #define OMAP3_EN_MPU_DPLL_LOCK 7 57 1.2.2.2 martin 58 1.2.2.2 martin #define OMAP3_CORE_DPLL_CLKOUT_DIV __BITS(31,27) 59 1.2.2.2 martin #define OMAP3_CORE_DPLL_MULT __BITS(26,16) 60 1.2.2.2 martin #define OMAP3_CORE_DPLL_DIV __BITS(14,8) 61 1.2.2.2 martin 62 1.2.2.2 martin static int ti_dpll_clock_match(device_t, cfdata_t, void *); 63 1.2.2.2 martin static void ti_dpll_clock_attach(device_t, device_t, void *); 64 1.2.2.2 martin 65 1.2.2.2 martin static struct clk *ti_dpll_clock_decode(device_t, int, const void *, size_t); 66 1.2.2.2 martin 67 1.2.2.2 martin static const struct fdtbus_clock_controller_func ti_dpll_clock_fdt_funcs = { 68 1.2.2.2 martin .decode = ti_dpll_clock_decode 69 1.2.2.2 martin }; 70 1.2.2.2 martin 71 1.2.2.2 martin static struct clk *ti_dpll_clock_get(void *, const char *); 72 1.2.2.2 martin static void ti_dpll_clock_put(void *, struct clk *); 73 1.2.2.2 martin static u_int ti_dpll_clock_get_rate(void *, struct clk *); 74 1.2.2.2 martin static struct clk *ti_dpll_clock_get_parent(void *, struct clk *); 75 1.2.2.2 martin 76 1.2.2.2 martin static int am3_dpll_clock_set_rate(void *, struct clk *, u_int); 77 1.2.2.2 martin 78 1.2.2.2 martin static const struct clk_funcs am3_dpll_clock_clk_funcs = { 79 1.2.2.2 martin .get = ti_dpll_clock_get, 80 1.2.2.2 martin .put = ti_dpll_clock_put, 81 1.2.2.2 martin .set_rate = am3_dpll_clock_set_rate, 82 1.2.2.2 martin .get_rate = ti_dpll_clock_get_rate, 83 1.2.2.2 martin .get_parent = ti_dpll_clock_get_parent, 84 1.2.2.2 martin }; 85 1.2.2.2 martin 86 1.2.2.2 martin static int omap3_dpll_clock_set_rate(void *, struct clk *, u_int); 87 1.2.2.2 martin 88 1.2.2.2 martin static const struct clk_funcs omap3_dpll_clock_clk_funcs = { 89 1.2.2.2 martin .get = ti_dpll_clock_get, 90 1.2.2.2 martin .put = ti_dpll_clock_put, 91 1.2.2.2 martin .set_rate = omap3_dpll_clock_set_rate, 92 1.2.2.2 martin .get_rate = ti_dpll_clock_get_rate, 93 1.2.2.2 martin .get_parent = ti_dpll_clock_get_parent, 94 1.2.2.2 martin }; 95 1.2.2.2 martin 96 1.2.2.2 martin static u_int omap3_dpll_core_clock_get_rate(void *, struct clk *); 97 1.2.2.2 martin 98 1.2.2.2 martin static const struct clk_funcs omap3_dpll_core_clock_clk_funcs = { 99 1.2.2.2 martin .get = ti_dpll_clock_get, 100 1.2.2.2 martin .put = ti_dpll_clock_put, 101 1.2.2.2 martin .get_rate = omap3_dpll_core_clock_get_rate, 102 1.2.2.2 martin .get_parent = ti_dpll_clock_get_parent, 103 1.2.2.2 martin }; 104 1.2.2.2 martin 105 1.2.2.2 martin static const struct of_compat_data compat_data[] = { 106 1.2.2.2 martin { "ti,am3-dpll-clock", (uintptr_t)&am3_dpll_clock_clk_funcs }, 107 1.2.2.2 martin { "ti,omap3-dpll-clock", (uintptr_t)&omap3_dpll_clock_clk_funcs }, 108 1.2.2.2 martin { "ti,omap3-dpll-core-clock", (uintptr_t)&omap3_dpll_core_clock_clk_funcs }, 109 1.2.2.2 martin { NULL } 110 1.2.2.2 martin }; 111 1.2.2.2 martin 112 1.2.2.2 martin enum { 113 1.2.2.2 martin REG_CONTROL, 114 1.2.2.2 martin REG_IDLEST, 115 1.2.2.2 martin REG_MULT_DIV1, 116 1.2.2.2 martin NREG 117 1.2.2.2 martin }; 118 1.2.2.2 martin 119 1.2.2.2 martin struct ti_dpll_clock_softc { 120 1.2.2.2 martin device_t sc_dev; 121 1.2.2.2 martin int sc_phandle; 122 1.2.2.2 martin bus_space_tag_t sc_bst; 123 1.2.2.2 martin bus_space_handle_t sc_bsh[NREG]; 124 1.2.2.2 martin 125 1.2.2.2 martin struct clk_domain sc_clkdom; 126 1.2.2.2 martin struct clk sc_clk; 127 1.2.2.2 martin }; 128 1.2.2.2 martin 129 1.2.2.2 martin #define RD4(sc, space) \ 130 1.2.2.2 martin bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh[(space)], 0) 131 1.2.2.2 martin #define WR4(sc, space, val) \ 132 1.2.2.2 martin bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh[(space)], 0, (val)) 133 1.2.2.2 martin 134 1.2.2.2 martin CFATTACH_DECL_NEW(ti_dpll_clock, sizeof(struct ti_dpll_clock_softc), 135 1.2.2.2 martin ti_dpll_clock_match, ti_dpll_clock_attach, NULL, NULL); 136 1.2.2.2 martin 137 1.2.2.2 martin static int 138 1.2.2.2 martin ti_dpll_clock_match(device_t parent, cfdata_t cf, void *aux) 139 1.2.2.2 martin { 140 1.2.2.2 martin const struct fdt_attach_args *faa = aux; 141 1.2.2.2 martin 142 1.2.2.2 martin return of_match_compat_data(faa->faa_phandle, compat_data); 143 1.2.2.2 martin } 144 1.2.2.2 martin 145 1.2.2.2 martin static void 146 1.2.2.2 martin ti_dpll_clock_attach(device_t parent, device_t self, void *aux) 147 1.2.2.2 martin { 148 1.2.2.2 martin struct ti_dpll_clock_softc * const sc = device_private(self); 149 1.2.2.2 martin const struct fdt_attach_args *faa = aux; 150 1.2.2.2 martin const int phandle = faa->faa_phandle; 151 1.2.2.2 martin const struct clk_funcs *clkfuncs; 152 1.2.2.2 martin bus_addr_t addr[NREG], base_addr; 153 1.2.2.2 martin u_int n; 154 1.2.2.2 martin 155 1.2.2.2 martin const int prcm_phandle = OF_parent(OF_parent(phandle)); 156 1.2.2.2 martin if (fdtbus_get_reg(prcm_phandle, 0, &base_addr, NULL) != 0) { 157 1.2.2.2 martin aprint_error(": couldn't get prcm registers\n"); 158 1.2.2.2 martin return; 159 1.2.2.2 martin } 160 1.2.2.2 martin 161 1.2.2.2 martin for (n = 0; n < NREG; n++) { 162 1.2.2.2 martin if (fdtbus_get_reg(phandle, n, &addr[n], NULL) != 0) { 163 1.2.2.2 martin aprint_error(": couldn't get registers\n"); 164 1.2.2.2 martin return; 165 1.2.2.2 martin } 166 1.2.2.2 martin } 167 1.2.2.2 martin 168 1.2.2.2 martin sc->sc_dev = self; 169 1.2.2.2 martin sc->sc_phandle = phandle; 170 1.2.2.2 martin sc->sc_bst = faa->faa_bst; 171 1.2.2.2 martin for (n = 0; n < NREG; n++) { 172 1.2.2.2 martin if (bus_space_map(sc->sc_bst, base_addr + addr[n], 4, 0, &sc->sc_bsh[n]) != 0) { 173 1.2.2.2 martin aprint_error(": couldn't map registers\n"); 174 1.2.2.2 martin return; 175 1.2.2.2 martin } 176 1.2.2.2 martin } 177 1.2.2.2 martin 178 1.2.2.2 martin clkfuncs = (const void *)of_search_compatible(phandle, compat_data)->data; 179 1.2.2.2 martin 180 1.2.2.2 martin sc->sc_clkdom.name = device_xname(self); 181 1.2.2.2 martin sc->sc_clkdom.funcs = clkfuncs; 182 1.2.2.2 martin sc->sc_clkdom.priv = sc; 183 1.2.2.2 martin 184 1.2.2.2 martin sc->sc_clk.domain = &sc->sc_clkdom; 185 1.2.2.2 martin sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name); 186 1.2.2.2 martin clk_attach(&sc->sc_clk); 187 1.2.2.2 martin 188 1.2.2.2 martin aprint_naive("\n"); 189 1.2.2.2 martin aprint_normal(": TI DPLL clock (%s)\n", sc->sc_clk.name); 190 1.2.2.2 martin 191 1.2.2.2 martin fdtbus_register_clock_controller(self, phandle, &ti_dpll_clock_fdt_funcs); 192 1.2.2.2 martin } 193 1.2.2.2 martin 194 1.2.2.2 martin static struct clk * 195 1.2.2.2 martin ti_dpll_clock_decode(device_t dev, int cc_phandle, const void *data, 196 1.2.2.2 martin size_t len) 197 1.2.2.2 martin { 198 1.2.2.2 martin struct ti_dpll_clock_softc * const sc = device_private(dev); 199 1.2.2.2 martin 200 1.2.2.2 martin return &sc->sc_clk; 201 1.2.2.2 martin } 202 1.2.2.2 martin 203 1.2.2.2 martin static struct clk * 204 1.2.2.2 martin ti_dpll_clock_get(void *priv, const char *name) 205 1.2.2.2 martin { 206 1.2.2.2 martin struct ti_dpll_clock_softc * const sc = priv; 207 1.2.2.2 martin 208 1.2.2.2 martin return &sc->sc_clk; 209 1.2.2.2 martin } 210 1.2.2.2 martin 211 1.2.2.2 martin static void 212 1.2.2.2 martin ti_dpll_clock_put(void *priv, struct clk *clk) 213 1.2.2.2 martin { 214 1.2.2.2 martin } 215 1.2.2.2 martin 216 1.2.2.2 martin static u_int 217 1.2.2.2 martin ti_dpll_clock_get_rate(void *priv, struct clk *clk) 218 1.2.2.2 martin { 219 1.2.2.2 martin struct ti_dpll_clock_softc * const sc = priv; 220 1.2.2.2 martin struct clk *clk_parent = clk_get_parent(clk); 221 1.2.2.2 martin uint32_t val; 222 1.2.2.2 martin uint64_t parent_rate; 223 1.2.2.2 martin 224 1.2.2.2 martin if (clk_parent == NULL) 225 1.2.2.2 martin return 0; 226 1.2.2.2 martin 227 1.2.2.2 martin val = RD4(sc, REG_MULT_DIV1); 228 1.2.2.2 martin const u_int mult = __SHIFTOUT(val, DPLL_MULT); 229 1.2.2.2 martin const u_int div = __SHIFTOUT(val, DPLL_DIV) + 1; 230 1.2.2.2 martin 231 1.2.2.2 martin parent_rate = clk_get_rate(clk_parent); 232 1.2.2.2 martin 233 1.2.2.2 martin return (u_int)((mult * parent_rate) / div); 234 1.2.2.2 martin } 235 1.2.2.2 martin 236 1.2.2.2 martin static struct clk * 237 1.2.2.2 martin ti_dpll_clock_get_parent(void *priv, struct clk *clk) 238 1.2.2.2 martin { 239 1.2.2.2 martin struct ti_dpll_clock_softc * const sc = priv; 240 1.2.2.2 martin 241 1.2.2.2 martin /* XXX assume ref clk */ 242 1.2.2.2 martin return fdtbus_clock_get_index(sc->sc_phandle, 0); 243 1.2.2.2 martin } 244 1.2.2.2 martin 245 1.2.2.2 martin static int 246 1.2.2.2 martin am3_dpll_clock_set_rate(void *priv, struct clk *clk, u_int rate) 247 1.2.2.2 martin { 248 1.2.2.2 martin struct ti_dpll_clock_softc * const sc = priv; 249 1.2.2.2 martin struct clk *clk_parent = clk_get_parent(clk); 250 1.2.2.2 martin uint64_t parent_rate; 251 1.2.2.2 martin uint32_t control, mult_div1; 252 1.2.2.2 martin 253 1.2.2.2 martin if (clk_parent == NULL) 254 1.2.2.2 martin return ENXIO; 255 1.2.2.2 martin 256 1.2.2.2 martin parent_rate = clk_get_rate(clk_parent); 257 1.2.2.2 martin if (parent_rate == 0) 258 1.2.2.2 martin return EIO; 259 1.2.2.2 martin 260 1.2.2.2 martin const u_int div = (parent_rate / 1000000) - 1; 261 1.2.2.2 martin const u_int mult = rate / (parent_rate / (div + 1)); 262 1.2.2.2 martin if (mult < 2 || mult > 2047) 263 1.2.2.2 martin return EINVAL; 264 1.2.2.2 martin 265 1.2.2.2 martin control = RD4(sc, REG_CONTROL); 266 1.2.2.2 martin control &= ~AM3_DPLL_EN; 267 1.2.2.2 martin control |= __SHIFTIN(AM3_DPLL_EN_NM_BYPASS, AM3_DPLL_EN); 268 1.2.2.2 martin WR4(sc, REG_CONTROL, control); 269 1.2.2.2 martin 270 1.2.2.3 martin while (RD4(sc, REG_IDLEST) != AM3_ST_MN_BYPASS) 271 1.2.2.2 martin ; 272 1.2.2.2 martin 273 1.2.2.2 martin mult_div1 = __SHIFTIN(mult, DPLL_MULT); 274 1.2.2.2 martin mult_div1 |= __SHIFTIN(div, DPLL_DIV); 275 1.2.2.2 martin WR4(sc, REG_MULT_DIV1, mult_div1); 276 1.2.2.2 martin 277 1.2.2.2 martin control &= ~AM3_DPLL_EN; 278 1.2.2.2 martin control |= __SHIFTIN(AM3_DPLL_EN_LOCK, AM3_DPLL_EN); 279 1.2.2.2 martin WR4(sc, REG_CONTROL, control); 280 1.2.2.2 martin 281 1.2.2.3 martin while (RD4(sc, REG_IDLEST) != AM3_ST_DPLL_CLK) 282 1.2.2.2 martin ; 283 1.2.2.2 martin 284 1.2.2.2 martin return 0; 285 1.2.2.2 martin } 286 1.2.2.2 martin 287 1.2.2.2 martin static int 288 1.2.2.2 martin omap3_dpll_clock_set_rate(void *priv, struct clk *clk, u_int rate) 289 1.2.2.2 martin { 290 1.2.2.2 martin struct ti_dpll_clock_softc * const sc = priv; 291 1.2.2.2 martin struct clk *clk_parent = clk_get_parent(clk); 292 1.2.2.2 martin uint64_t parent_rate; 293 1.2.2.2 martin uint32_t control, mult_div1; 294 1.2.2.2 martin 295 1.2.2.2 martin if (clk_parent == NULL) 296 1.2.2.2 martin return ENXIO; 297 1.2.2.2 martin 298 1.2.2.2 martin parent_rate = clk_get_rate(clk_parent); 299 1.2.2.2 martin 300 1.2.2.2 martin const u_int div = (parent_rate / 1000000) - 1; 301 1.2.2.2 martin const u_int mult = rate / (parent_rate / (div + 1)); 302 1.2.2.2 martin if (mult < 2 || mult > 2047) 303 1.2.2.2 martin return EINVAL; 304 1.2.2.2 martin 305 1.2.2.2 martin control = RD4(sc, REG_CONTROL); 306 1.2.2.2 martin control &= ~OMAP3_EN_MPU_DPLL; 307 1.2.2.2 martin control |= __SHIFTIN(OMAP3_EN_MPU_DPLL_BYPASS, OMAP3_EN_MPU_DPLL); 308 1.2.2.2 martin WR4(sc, REG_CONTROL, control); 309 1.2.2.2 martin 310 1.2.2.2 martin delay(10); 311 1.2.2.2 martin 312 1.2.2.2 martin mult_div1 = __SHIFTIN(mult, DPLL_MULT); 313 1.2.2.2 martin mult_div1 |= __SHIFTIN(div, DPLL_DIV); 314 1.2.2.2 martin WR4(sc, REG_MULT_DIV1, mult_div1); 315 1.2.2.2 martin 316 1.2.2.2 martin control &= ~OMAP3_EN_MPU_DPLL; 317 1.2.2.2 martin control |= __SHIFTIN(OMAP3_EN_MPU_DPLL_LOCK, OMAP3_EN_MPU_DPLL); 318 1.2.2.2 martin WR4(sc, REG_CONTROL, control); 319 1.2.2.2 martin 320 1.2.2.2 martin while ((RD4(sc, REG_IDLEST) & OMAP3_ST_MPU_CLK) != 0) 321 1.2.2.2 martin ; 322 1.2.2.2 martin 323 1.2.2.2 martin return 0; 324 1.2.2.2 martin } 325 1.2.2.2 martin 326 1.2.2.2 martin static u_int 327 1.2.2.2 martin omap3_dpll_core_clock_get_rate(void *priv, struct clk *clk) 328 1.2.2.2 martin { 329 1.2.2.2 martin struct ti_dpll_clock_softc * const sc = priv; 330 1.2.2.2 martin struct clk *clk_parent = clk_get_parent(clk); 331 1.2.2.2 martin uint32_t val; 332 1.2.2.2 martin uint64_t parent_rate; 333 1.2.2.2 martin 334 1.2.2.2 martin if (clk_parent == NULL) 335 1.2.2.2 martin return 0; 336 1.2.2.2 martin 337 1.2.2.2 martin val = RD4(sc, REG_MULT_DIV1); 338 1.2.2.2 martin const u_int mult = __SHIFTOUT(val, OMAP3_CORE_DPLL_MULT); 339 1.2.2.2 martin const u_int div = __SHIFTOUT(val, OMAP3_CORE_DPLL_DIV) + 1; 340 1.2.2.2 martin const u_int postdiv = __SHIFTOUT(val, OMAP3_CORE_DPLL_CLKOUT_DIV); 341 1.2.2.2 martin 342 1.2.2.2 martin parent_rate = clk_get_rate(clk_parent); 343 1.2.2.2 martin 344 1.2.2.2 martin return (u_int)((mult * parent_rate) / div) / postdiv; 345 1.2.2.2 martin } 346
Indexes created Mon Oct 13 16:09:52 GMT 2025