ti_dpll_clock.c revision 1.2.2.3
1 /* $NetBSD: ti_dpll_clock.c,v 1.2.2.3 2020/06/07 13:28:02 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: ti_dpll_clock.c,v 1.2.2.3 2020/06/07 13:28:02 martin Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kmem.h> 36 #include <sys/bus.h> 37 38 #include <dev/clk/clk_backend.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #define DPLL_MULT __BITS(18,8) 43 #define DPLL_DIV __BITS(6,0) 44 45 #define AM3_ST_MN_BYPASS __BIT(8) 46 #define AM3_ST_DPLL_CLK __BIT(0) 47 48 #define AM3_DPLL_EN __BITS(2,0) 49 #define AM3_DPLL_EN_NM_BYPASS 4 50 #define AM3_DPLL_EN_LOCK 7 51 52 #define OMAP3_ST_MPU_CLK __BIT(0) 53 54 #define OMAP3_EN_MPU_DPLL __BITS(2,0) 55 #define OMAP3_EN_MPU_DPLL_BYPASS 5 56 #define OMAP3_EN_MPU_DPLL_LOCK 7 57 58 #define OMAP3_CORE_DPLL_CLKOUT_DIV __BITS(31,27) 59 #define OMAP3_CORE_DPLL_MULT __BITS(26,16) 60 #define OMAP3_CORE_DPLL_DIV __BITS(14,8) 61 62 static int ti_dpll_clock_match(device_t, cfdata_t, void *); 63 static void ti_dpll_clock_attach(device_t, device_t, void *); 64 65 static struct clk *ti_dpll_clock_decode(device_t, int, const void *, size_t); 66 67 static const struct fdtbus_clock_controller_func ti_dpll_clock_fdt_funcs = { 68 .decode = ti_dpll_clock_decode 69 }; 70 71 static struct clk *ti_dpll_clock_get(void *, const char *); 72 static void ti_dpll_clock_put(void *, struct clk *); 73 static u_int ti_dpll_clock_get_rate(void *, struct clk *); 74 static struct clk *ti_dpll_clock_get_parent(void *, struct clk *); 75 76 static int am3_dpll_clock_set_rate(void *, struct clk *, u_int); 77 78 static const struct clk_funcs am3_dpll_clock_clk_funcs = { 79 .get = ti_dpll_clock_get, 80 .put = ti_dpll_clock_put, 81 .set_rate = am3_dpll_clock_set_rate, 82 .get_rate = ti_dpll_clock_get_rate, 83 .get_parent = ti_dpll_clock_get_parent, 84 }; 85 86 static int omap3_dpll_clock_set_rate(void *, struct clk *, u_int); 87 88 static const struct clk_funcs omap3_dpll_clock_clk_funcs = { 89 .get = ti_dpll_clock_get, 90 .put = ti_dpll_clock_put, 91 .set_rate = omap3_dpll_clock_set_rate, 92 .get_rate = ti_dpll_clock_get_rate, 93 .get_parent = ti_dpll_clock_get_parent, 94 }; 95 96 static u_int omap3_dpll_core_clock_get_rate(void *, struct clk *); 97 98 static const struct clk_funcs omap3_dpll_core_clock_clk_funcs = { 99 .get = ti_dpll_clock_get, 100 .put = ti_dpll_clock_put, 101 .get_rate = omap3_dpll_core_clock_get_rate, 102 .get_parent = ti_dpll_clock_get_parent, 103 }; 104 105 static const struct of_compat_data compat_data[] = { 106 { "ti,am3-dpll-clock", (uintptr_t)&am3_dpll_clock_clk_funcs }, 107 { "ti,omap3-dpll-clock", (uintptr_t)&omap3_dpll_clock_clk_funcs }, 108 { "ti,omap3-dpll-core-clock", (uintptr_t)&omap3_dpll_core_clock_clk_funcs }, 109 { NULL } 110 }; 111 112 enum { 113 REG_CONTROL, 114 REG_IDLEST, 115 REG_MULT_DIV1, 116 NREG 117 }; 118 119 struct ti_dpll_clock_softc { 120 device_t sc_dev; 121 int sc_phandle; 122 bus_space_tag_t sc_bst; 123 bus_space_handle_t sc_bsh[NREG]; 124 125 struct clk_domain sc_clkdom; 126 struct clk sc_clk; 127 }; 128 129 #define RD4(sc, space) \ 130 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh[(space)], 0) 131 #define WR4(sc, space, val) \ 132 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh[(space)], 0, (val)) 133 134 CFATTACH_DECL_NEW(ti_dpll_clock, sizeof(struct ti_dpll_clock_softc), 135 ti_dpll_clock_match, ti_dpll_clock_attach, NULL, NULL); 136 137 static int 138 ti_dpll_clock_match(device_t parent, cfdata_t cf, void *aux) 139 { 140 const struct fdt_attach_args *faa = aux; 141 142 return of_match_compat_data(faa->faa_phandle, compat_data); 143 } 144 145 static void 146 ti_dpll_clock_attach(device_t parent, device_t self, void *aux) 147 { 148 struct ti_dpll_clock_softc * const sc = device_private(self); 149 const struct fdt_attach_args *faa = aux; 150 const int phandle = faa->faa_phandle; 151 const struct clk_funcs *clkfuncs; 152 bus_addr_t addr[NREG], base_addr; 153 u_int n; 154 155 const int prcm_phandle = OF_parent(OF_parent(phandle)); 156 if (fdtbus_get_reg(prcm_phandle, 0, &base_addr, NULL) != 0) { 157 aprint_error(": couldn't get prcm registers\n"); 158 return; 159 } 160 161 for (n = 0; n < NREG; n++) { 162 if (fdtbus_get_reg(phandle, n, &addr[n], NULL) != 0) { 163 aprint_error(": couldn't get registers\n"); 164 return; 165 } 166 } 167 168 sc->sc_dev = self; 169 sc->sc_phandle = phandle; 170 sc->sc_bst = faa->faa_bst; 171 for (n = 0; n < NREG; n++) { 172 if (bus_space_map(sc->sc_bst, base_addr + addr[n], 4, 0, &sc->sc_bsh[n]) != 0) { 173 aprint_error(": couldn't map registers\n"); 174 return; 175 } 176 } 177 178 clkfuncs = (const void *)of_search_compatible(phandle, compat_data)->data; 179 180 sc->sc_clkdom.name = device_xname(self); 181 sc->sc_clkdom.funcs = clkfuncs; 182 sc->sc_clkdom.priv = sc; 183 184 sc->sc_clk.domain = &sc->sc_clkdom; 185 sc->sc_clk.name = kmem_asprintf("%s", faa->faa_name); 186 clk_attach(&sc->sc_clk); 187 188 aprint_naive("\n"); 189 aprint_normal(": TI DPLL clock (%s)\n", sc->sc_clk.name); 190 191 fdtbus_register_clock_controller(self, phandle, &ti_dpll_clock_fdt_funcs); 192 } 193 194 static struct clk * 195 ti_dpll_clock_decode(device_t dev, int cc_phandle, const void *data, 196 size_t len) 197 { 198 struct ti_dpll_clock_softc * const sc = device_private(dev); 199 200 return &sc->sc_clk; 201 } 202 203 static struct clk * 204 ti_dpll_clock_get(void *priv, const char *name) 205 { 206 struct ti_dpll_clock_softc * const sc = priv; 207 208 return &sc->sc_clk; 209 } 210 211 static void 212 ti_dpll_clock_put(void *priv, struct clk *clk) 213 { 214 } 215 216 static u_int 217 ti_dpll_clock_get_rate(void *priv, struct clk *clk) 218 { 219 struct ti_dpll_clock_softc * const sc = priv; 220 struct clk *clk_parent = clk_get_parent(clk); 221 uint32_t val; 222 uint64_t parent_rate; 223 224 if (clk_parent == NULL) 225 return 0; 226 227 val = RD4(sc, REG_MULT_DIV1); 228 const u_int mult = __SHIFTOUT(val, DPLL_MULT); 229 const u_int div = __SHIFTOUT(val, DPLL_DIV) + 1; 230 231 parent_rate = clk_get_rate(clk_parent); 232 233 return (u_int)((mult * parent_rate) / div); 234 } 235 236 static struct clk * 237 ti_dpll_clock_get_parent(void *priv, struct clk *clk) 238 { 239 struct ti_dpll_clock_softc * const sc = priv; 240 241 /* XXX assume ref clk */ 242 return fdtbus_clock_get_index(sc->sc_phandle, 0); 243 } 244 245 static int 246 am3_dpll_clock_set_rate(void *priv, struct clk *clk, u_int rate) 247 { 248 struct ti_dpll_clock_softc * const sc = priv; 249 struct clk *clk_parent = clk_get_parent(clk); 250 uint64_t parent_rate; 251 uint32_t control, mult_div1; 252 253 if (clk_parent == NULL) 254 return ENXIO; 255 256 parent_rate = clk_get_rate(clk_parent); 257 if (parent_rate == 0) 258 return EIO; 259 260 const u_int div = (parent_rate / 1000000) - 1; 261 const u_int mult = rate / (parent_rate / (div + 1)); 262 if (mult < 2 || mult > 2047) 263 return EINVAL; 264 265 control = RD4(sc, REG_CONTROL); 266 control &= ~AM3_DPLL_EN; 267 control |= __SHIFTIN(AM3_DPLL_EN_NM_BYPASS, AM3_DPLL_EN); 268 WR4(sc, REG_CONTROL, control); 269 270 while (RD4(sc, REG_IDLEST) != AM3_ST_MN_BYPASS) 271 ; 272 273 mult_div1 = __SHIFTIN(mult, DPLL_MULT); 274 mult_div1 |= __SHIFTIN(div, DPLL_DIV); 275 WR4(sc, REG_MULT_DIV1, mult_div1); 276 277 control &= ~AM3_DPLL_EN; 278 control |= __SHIFTIN(AM3_DPLL_EN_LOCK, AM3_DPLL_EN); 279 WR4(sc, REG_CONTROL, control); 280 281 while (RD4(sc, REG_IDLEST) != AM3_ST_DPLL_CLK) 282 ; 283 284 return 0; 285 } 286 287 static int 288 omap3_dpll_clock_set_rate(void *priv, struct clk *clk, u_int rate) 289 { 290 struct ti_dpll_clock_softc * const sc = priv; 291 struct clk *clk_parent = clk_get_parent(clk); 292 uint64_t parent_rate; 293 uint32_t control, mult_div1; 294 295 if (clk_parent == NULL) 296 return ENXIO; 297 298 parent_rate = clk_get_rate(clk_parent); 299 300 const u_int div = (parent_rate / 1000000) - 1; 301 const u_int mult = rate / (parent_rate / (div + 1)); 302 if (mult < 2 || mult > 2047) 303 return EINVAL; 304 305 control = RD4(sc, REG_CONTROL); 306 control &= ~OMAP3_EN_MPU_DPLL; 307 control |= __SHIFTIN(OMAP3_EN_MPU_DPLL_BYPASS, OMAP3_EN_MPU_DPLL); 308 WR4(sc, REG_CONTROL, control); 309 310 delay(10); 311 312 mult_div1 = __SHIFTIN(mult, DPLL_MULT); 313 mult_div1 |= __SHIFTIN(div, DPLL_DIV); 314 WR4(sc, REG_MULT_DIV1, mult_div1); 315 316 control &= ~OMAP3_EN_MPU_DPLL; 317 control |= __SHIFTIN(OMAP3_EN_MPU_DPLL_LOCK, OMAP3_EN_MPU_DPLL); 318 WR4(sc, REG_CONTROL, control); 319 320 while ((RD4(sc, REG_IDLEST) & OMAP3_ST_MPU_CLK) != 0) 321 ; 322 323 return 0; 324 } 325 326 static u_int 327 omap3_dpll_core_clock_get_rate(void *priv, struct clk *clk) 328 { 329 struct ti_dpll_clock_softc * const sc = priv; 330 struct clk *clk_parent = clk_get_parent(clk); 331 uint32_t val; 332 uint64_t parent_rate; 333 334 if (clk_parent == NULL) 335 return 0; 336 337 val = RD4(sc, REG_MULT_DIV1); 338 const u_int mult = __SHIFTOUT(val, OMAP3_CORE_DPLL_MULT); 339 const u_int div = __SHIFTOUT(val, OMAP3_CORE_DPLL_DIV) + 1; 340 const u_int postdiv = __SHIFTOUT(val, OMAP3_CORE_DPLL_CLKOUT_DIV); 341 342 parent_rate = clk_get_rate(clk_parent); 343 344 return (u_int)((mult * parent_rate) / div) / postdiv; 345 } 346
Indexes created Sun Oct 12 09:09:55 GMT 2025